JP4752784B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

For example, in a frequency converter or the like of a communication device, a semiconductor device in which an insulated gate field effect transistor and a bipolar transistor are formed on a common semiconductor substrate is used.
In this case, high-frequency bipolar transistors are required to operate at high speed. In order to increase the speed of the bipolar transistor, it is important to shorten the base running time and reduce the resistance of the base by making the base shallow.

Therefore, in order to increase the speed of the bipolar transistor, it is indispensable to form a high concentration and thin base layer.
However, in the formation of the base layer using the conventional ion implantation technique, it has been difficult to realize a base having a narrow shallow junction due to the problem of channeling tail of implanted impurities.

As a solution to this problem, a heterojunction bipolar transistor (hereinafter referred to as HBT) that applies a technique of epitaxially growing a silicon-germanium (Si _1-x Ge _x , hereinafter referred to as SiGe) mixed crystal layer on a silicon substrate. ) Is attracting attention.

The shallow junction of the base region increases the impurity concentration of the base region, and the injection of holes into the emitter becomes a problem.
With respect to this problem, SiGe HBT has a potential barrier between the emitter and the base by using SiGe having a narrower band gap than silicon in the base region, so that the injection of holes into the emitter is greatly reduced.
Therefore, the base resistance can be reduced by increasing the base concentration, and a sufficiently large current amplification factor (h _FE ) can be obtained. As a result, high frequency characteristics can be realized while ensuring a sufficient breakdown voltage.
Further, by tilting the germanium profile, it is possible to realize a high-speed bipolar transistor having excellent high-frequency characteristics with a shortened carrier base travel time (τ _B ).

Here, the cutoff frequency (hereinafter referred to as f _T ) of the bipolar transistor is given by the following equation (1).

However,
τ _E : Emitter depletion layer charge time τ _B : Base travel time τ _X : Collector depletion layer travel time τ _C : Collector charge time

From equation (1), in order to improve f _T is the emitter, base, that it is necessary to shallow each of the junction of the collector can be seen.

Further, as an index of high speed of the bipolar transistor, there is a maximum oscillation frequency (hereinafter, referred to as f _max ) in addition to f _T , which is given by the following formula 2.

Where R _B : Base resistance C _jC : Collector junction capacitance

From equation (2), in order to improve f _max , it is necessary to reduce the base resistance and the collector junction capacitance. Here, the base resistance is expressed by the following equation.
R _B = R _BI + R _BX
R _BI : Resistance just below the emitter R _BX : Resistance of the portion from the emitter to the base electrode It is important to reduce this base resistance R _B in order to improve f _max .

Here, the base resistance reduction method in the prior art will be described with reference to FIGS.
4 and 5 are enlarged sectional views showing only the base and emitter regions of SiGeHBT.

First, the manufacturing procedure of SiGeHBT will be described with reference to FIG.
As shown in FIG. 4, an epitaxial layer 9 made of a SiGe mixed crystal layer is formed by an epitaxial technique so as to be in contact with the underlying semiconductor substrate (not shown) in the region opened using the silicon oxide films 5 and 8 as a mask. Grow. The SiGe mixed crystal layer has a three-layer structure in which a silicon-only buffer layer 9A is formed first, followed by a SiGe layer 9B, and then a silicon-only cap layer 9C.
As a result, the epitaxial layer 9 made of the SiGe mixed crystal layer is formed non-selectively with respect to the silicon oxide films 5 and 8, and a polycrystalline SiGe mixed crystal layer is formed on the silicon oxide films 5 and 8, and the semiconductor is formed through the openings. A single crystal SiGe mixed crystal layer is formed in a region in contact with the substrate.
The polycrystalline SiGe mixed crystal layer formed on the silicon oxide films 5 and 8 is used as a base extraction electrode and is connected to a wiring or the like in a later process.

  Here, when the epitaxial region 9 is formed non-selectively and the base region is formed as described above, the polycrystalline SiGe mixed layer is formed at the end of the opening formed by the silicon oxide films 5 and 8 as shown in FIG. The crystal layer protrudes to the single crystal SiGe mixed crystal layer side. Since the protruding portion has poor crystallinity, when the emitter is formed in the base region, it is necessary to be inside the protruding portion of the polycrystalline SiGe mixed crystal layer.

Thereafter, after the silicon oxide film 12 is formed on the entire surface, a portion to be an emitter region is opened with respect to the silicon oxide film 12, and a polycrystalline silicon film 14 is formed thereon.
Next, arsenic (As) as an emitter impurity is introduced into the polycrystalline silicon film 14 using an ion implantation technique, and thereafter, a silicon oxide film is formed on the polycrystalline silicon film 14 (not shown).
Subsequently, by performing heat treatment, the emitter impurity is activated and diffused from the polycrystalline silicon film 14 to the base region, thereby forming the emitter region 15 in the base region.

Next, the silicon oxide film formed on the polycrystalline silicon film 14 is etched using an existing dry etching technique so that the base extraction electrode is exposed. That is, the polycrystalline silicon film 14 and the silicon oxide film 12 thereunder are etched together with the silicon oxide film to pattern them.
Next, for the purpose of reducing the resistance of the base lead electrode portion, cobalt silicide 11 is formed on the surface of the epitaxial layer 9 (that is, the surface of the silicon cap layer 9C) that becomes the base lead electrode.
Thereafter, unnecessary unreacted cobalt is removed by desired washing.

By using the above-described technique, the resistance (R _BX2 ) in the portion from the emitter to the base electrode can be reduced by the cobalt silicide 11, so that it is considered that f _max can be improved.
However, on the other hand, the following problems occur.

As shown in FIG. 4, when the silicon oxide film 12 is opened on the single crystal SiGe mixed crystal layer by the above patterning, the cobalt silicide 11 is formed on the surface of the silicon cap layer 9C on the single crystal SiGe mixed crystal layer side. Will be formed.
In this case, since the single crystal SiGe mixed crystal layer has a strain, when the cobalt silicide 11 reacts with the silicon cap layer 9C, the strain of the single crystal SiGe mixed crystal layer is relaxed and a spike 31 enters.
As a result, a leak occurs between the base and the collector, and the yield is significantly reduced.

In order to avoid this, the silicon cap layer 9C may be thickened. However, in order to manufacture a high-performance SiGeHBT, for example, the silicon cap layer 9C is made as thin as about 20 to 50 nm as much as possible, and the emitter is shallow. This is not preferable because it is necessary to reduce τ _E by bonding.

  On the other hand, the above-described spike phenomenon at the time of cobalt silicide formation cannot be prevented unless the silicon cap layer 9C is about 100 nm or more (S. Kolodinski, M. Caymax, P. Roussel, H. Bender, B. Brijs and K. Maex, Applied Surface Science 91 (1995) pp. 77-81).

  Therefore, as shown in FIG. 5, if the silicon oxide film 12 is patterned so as to cover the single crystal SiGe mixed crystal layer, the cobalt silicide 11 is not formed on the single crystal SiGe mixed crystal layer. The spike phenomenon at the time of forming the silicide 11 can be avoided.

However, in such a configuration, since the width of the silicon oxide film 12 serving as an insulating film mask in the emitter opening is increased, the base resistance (R _BX1 ) immediately below it cannot be lowered.
For this reason, the resistance (R _BX = R _BX1 + R _BX2 ) in the portion from the emitter to the base electrode cannot be sufficiently reduced, and a high-performance SiGeHBT cannot be manufactured.

  In order to solve the above-described problems, the present invention provides a semiconductor device having a high-performance bipolar transistor that can reduce the resistance between the emitter and the base electrode, can operate at high speed, and a method for manufacturing the same. is there.

A semiconductor device of the present invention is formed by forming a bipolar transistor having a base region made of an epitaxial layer so as to include an opening of an insulating film formed on a semiconductor substrate, and comprising a silicon layer, silicon and germanium, A base region composed of an epitaxial layer is formed by a silicon mixed crystal layer composed of a layer having carbon, and the uppermost layer of the silicon mixed crystal layer is a silicon layer. Of the base region composed of the silicon mixed crystal layer, a single crystal Cobalt silicide is formed on the silicon mixed crystal layer and the polycrystalline silicon mixed crystal layer via a polycrystalline silicon film.
A semiconductor device according to the present invention is formed by forming a bipolar transistor having a base region made of an epitaxial layer so as to include an opening of an insulating film formed on a semiconductor substrate. A base region made of an epitaxial layer is formed by a silicon mixed crystal layer having a three-layer structure of a SiGeC layer and a silicon cap layer. Among the base regions made of the silicon mixed crystal layer, the single crystal silicon mixed crystal layer and the polycrystalline layer are formed. Cobalt silicide is formed on the silicon mixed crystal layer via a polycrystalline silicon film.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a bipolar transistor having a base region made of an epitaxial layer is formed on a semiconductor substrate, and an insulating film is formed on the semiconductor substrate. A step of forming an opening in the bipolar transistor forming region of the insulating film, and a silicon mixed crystal layer comprising a silicon layer, a layer containing silicon, germanium, and carbon so as to include the opening, the uppermost layer being a silicon layer Forming a polycrystalline silicon film on the single crystal silicon mixed crystal layer and the polycrystalline silicon mixed crystal layer in the base region composed of the silicon mixed crystal layer, and polycrystalline silicon. And forming a cobalt silicide on the surface of the film.
A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a bipolar transistor having a base region made of an epitaxial layer is formed on a semiconductor substrate, and an insulating film is formed on the semiconductor substrate. A step of forming an opening in the bipolar transistor forming region of the insulating film, and a silicon mixed crystal layer composed of a three-layer structure including a buffer layer of a silicon layer, a SiGeC layer, and a silicon cap layer from the lower layer by epitaxial growth so as to include the opening. A step of forming, a step of forming a polycrystalline silicon film on the single crystal silicon mixed crystal layer and the polycrystalline silicon mixed crystal layer in the base region comprising the silicon mixed crystal layer, and a surface of the polycrystalline silicon film And a step of forming cobalt silicide.

According to the configuration of the semiconductor device of the present invention described above, the base region formed of the silicon mixed crystal layer including the silicon layer and the layer including silicon, germanium, and carbon is formed on the single crystal silicon mixed crystal layer and on the multiple layers. By forming cobalt silicide on the crystalline silicon mixed crystal layer through the polycrystalline silicon film, the resistance of the portion serving as the base extraction electrode portion is reduced by the cobalt silicide, and by passing through the polycrystalline silicon film. It is possible to adopt a configuration that does not affect the silicon mixed crystal layer in the manufacturing process.
Thereby, for example, the spike phenomenon in the silicon mixed crystal layer can be avoided.
According to the configuration of the above-described semiconductor device of the present invention, the single crystal silicon mixed layer out of the base region formed of the silicon mixed crystal layer having the three-layer structure of the buffer layer of the silicon layer, the SiGeC layer, and the silicon cap layer from the lower layer. Cobalt silicide is formed on the crystalline layer and the polycrystalline silicon mixed crystal layer via the polycrystalline silicon film, whereby the resistance of the portion serving as the base extraction electrode portion is reduced by the cobalt silicide. By using the silicon film, it is possible to adopt a configuration that does not affect the silicon mixed crystal layer in the manufacturing process.
Thereby, for example, the spike phenomenon in the silicon mixed crystal layer can be avoided.

According to the method of manufacturing a semiconductor device of the present invention described above, the single crystal silicon mixed crystal at a position outside the insulating mask of the emitter opening is formed before the formation of cobalt silicide in the base extraction electrode portion on the surface of the silicon mixed crystal layer. A polycrystalline silicon film is formed on the layer and on the polycrystalline silicon layer.
Thus, the polycrystalline silicon film can prevent the silicon mixed crystal layer from being affected in the manufacturing process, and for example, a spike phenomenon in the silicon mixed crystal layer can be avoided. Further, by forming cobalt silicide, it is possible to reduce the resistance of a portion that is not covered by the mask layer, that is, a portion that becomes a base extraction electrode portion.

  According to the above-mentioned present invention, a spike phenomenon at the time of forming a silicide can be avoided and a base resistance can be reduced, whereby a semiconductor device having a high-performance bipolar transistor capable of high-speed operation is provided. Can be realized.

The present invention relates to a semiconductor device in which a bipolar transistor having a base region made of an epitaxial layer is formed so as to include an opening of an insulating film formed on a semiconductor substrate, and includes a silicon layer, silicon, germanium, and carbon . A base region made of an epitaxial layer is formed by a silicon mixed crystal layer made of a layer having a silicon layer, and the uppermost layer of the silicon mixed crystal layer is a silicon layer. In this semiconductor device, cobalt silicide is formed on a crystalline layer and a polycrystalline silicon mixed crystal layer via a polycrystalline silicon film.
The present invention relates to a semiconductor device in which a bipolar transistor having a base region made of an epitaxial layer is formed so as to include an opening of an insulating film formed on a semiconductor substrate. A base region made of an epitaxial layer is formed by a silicon mixed crystal layer having a three-layer structure of a layer and a silicon cap layer. Among the base regions made of a silicon mixed crystal layer, a single crystal silicon mixed crystal layer and a polycrystalline silicon mixed layer are formed. In this semiconductor device, cobalt silicide is formed on a crystal layer via a polycrystalline silicon film.

According to the present invention, in the semiconductor device, the thickness of the uppermost silicon layer of the silicon mixed crystal layer is 20 to 40 nm .

The present invention relates to a method of manufacturing a semiconductor device in which a bipolar transistor having a base region composed of an epitaxial layer is formed on a semiconductor substrate, wherein an insulating film is formed on the semiconductor substrate, and the bipolar transistor of this insulating film is formed. And forming a silicon mixed crystal layer having a silicon layer, a layer containing silicon, germanium, and carbon , the uppermost layer being a silicon layer, by epitaxial growth. A step of forming a polycrystalline silicon film on the single crystal silicon mixed crystal layer and the polycrystalline silicon mixed crystal layer in the base region composed of the silicon mixed crystal layer, and cobalt on the surface of the polycrystalline silicon film. And a step of forming a silicide.
The present invention relates to a method of manufacturing a semiconductor device in which a bipolar transistor having a base region composed of an epitaxial layer is formed on a semiconductor substrate, wherein an insulating film is formed on the semiconductor substrate, and the bipolar transistor of this insulating film is formed. A step of forming an opening in the forming region, and a step of forming a silicon mixed crystal layer having a three-layer structure of a buffer layer of a silicon layer, a SiGeC layer, and a silicon cap layer by epitaxial growth so as to include the opening, A step of forming a polycrystalline silicon film on the single crystal silicon mixed crystal layer and the polycrystalline silicon mixed crystal layer in the base region composed of the silicon mixed crystal layer, and forming cobalt silicide on the surface of the polycrystalline silicon film. A method for manufacturing a semiconductor device.

According to the present invention, in the method of manufacturing a semiconductor device, the thickness of the uppermost silicon of the silicon mixed crystal layer is 20 to 40 nm .

FIG. 1A shows a schematic configuration diagram of a semiconductor device according to an embodiment of the present invention.
This semiconductor device has a configuration in which the above-described HBT (heterojunction bipolar transistor) using a SiGe mixed crystal layer is formed on a semiconductor substrate.

As shown in FIG. 1A, a second conductive type, for example, n-type semiconductor epitaxial layer 3 is grown on, for example, a first conductive type, for example, p-type silicon substrate 2, and the silicon substrate 2 and the silicon epitaxial layer 3 are grown. Thus, the semiconductor substrate 1 is constituted.
An element isolation film 5 made of, for example, a silicon oxide film is formed on the surface of the semiconductor substrate 1, and an element isolation region 6 of the first conductivity type, for example, p ⁺ is formed below the element isolation film 5. The element isolation film 5 and the element isolation region 6 separate the bipolar transistor formation region from other circuit element formation regions.

An n ⁺ collector buried region 4 is formed from the silicon substrate 2 of the semiconductor substrate 1 to the epitaxial layer 3, and a collector electrode extraction region 7 is formed so as to reach the collector buried region 4.

On the surface of the n-type collector region formed by the epitaxial layer 3, a base region (so-called epitaxial base region) composed of a silicon-germanium mixed crystal layer 9 is formed by epitaxial growth. This epitaxial base region is in contact with the surface of the semiconductor substrate 1 through an opening formed in the silicon oxide film 8 on the element isolation film 5.
In the silicon-germanium mixed crystal layer 9 constituting the epitaxial base region, a portion in contact with the surface of the semiconductor substrate 1 is a single crystal layer, and a portion on the silicon oxide film 8 is a polycrystalline layer.

Further, a silicon oxide film 12 is formed on the epitaxial base region, and an polycrystalline silicon film 14 containing, for example, an n-type impurity is in contact with the surface of the epitaxial base region through an opening formed in the silicon oxide film 12. An emitter region 15 is formed on the surface of the epitaxial base region by diffusion of n-type impurities from the polycrystalline silicon film 14.
The silicon oxide film 12 and the polycrystalline silicon film 14 are patterned to a width narrower than the width of the region of the single crystal layer in the silicon-germanium mixed crystal layer 9 as in the case of FIG.

Note that a region indicated by 13 in the figure indicates an n ⁺ region in which an n-type impurity is introduced into the surface of the n-type collector region of the epitaxial layer 3.

  Here, a cross-sectional view schematically showing the vicinity of the base region in FIG. 1A is shown in FIG. 1B. In FIG. 1B, a portion indicated by X1 indicates a portion where the polycrystalline SiGe mixed crystal layer protrudes to the single crystal SiGe mixed crystal layer side.

FIG. 2 is an enlarged cross-sectional view of the vicinity of the base region in FIG.
In the present embodiment, as shown in FIG. 2, a polycrystalline silicon film 10 is formed on the silicon-germanium mixed crystal layer 9 outside the silicon oxide film 12, and cobalt silicide 11 is formed on the polycrystalline silicon film 10. Forming.

  That is, as shown in FIGS. 4 and 5, the cobalt silicide 11 is not directly formed on the silicon cap layer 9C, but the cobalt silicide 11 is formed on the silicon cap layer 9C via the polycrystalline silicon film 10.

Thus, the resistance of the base lead electrode portion can be reduced by the cobalt silicide 11.
Further, when the cobalt silicide 11 is formed, it can be blocked by the polycrystalline silicon film 10 so as not to affect the SiGe layer 9B portion of the single crystal SiGe mixed crystal layer. Can be prevented.
Furthermore, since the distance from the emitter region 15 to the base lead electrode portion is shortened and the resistance R _BX1 under the silicon oxide film 12 can be reduced, the resistance R _BX from the emitter to the base can be reduced. .

Then, as shown in FIG. 1, a base electrode 18 is formed on the surface of the base extraction electrode portion, that is, on the polycrystalline silicon film 10 and the cobalt silicide 11, and is connected on the polycrystalline silicon film 14 on the emitter region 15. Thus, an emitter electrode 17 is formed, and a collector electrode 19 is formed in connection with the collector electrode extraction region 7. These electrodes 17, 18 and 19 are all connected to each part of the SiGeHBT through openings formed in the silicon oxide film 16 covering the surface.
Thus, SiGeHBT is formed on the semiconductor substrate 1 to constitute a semiconductor device.

According to the semiconductor device of the present embodiment described above, since the cobalt silicide 11 is formed on the silicon cap layer 9C via the polycrystalline silicon film 10, the resistance of the base extraction electrode portion is reduced by the cobalt silicide 11. In addition, the polycrystalline silicon film 10 can prevent the occurrence of the spike phenomenon so as not to affect the portion of the SiGe layer 9B of the single crystal SiGe mixed crystal layer.
Further, by shortening the distance from the emitter region 15 to the base extraction electrode portion, the resistance R _BX from the emitter to the base can be reduced.

  Therefore, according to this embodiment, the problem of the cobalt silicide spike phenomenon can be avoided and the base resistance can be reduced, so that a semiconductor device with excellent performance can be manufactured.

The semiconductor device of the present embodiment described above can be manufactured as follows.
A silicon substrate 2 having a first conductivity type, for example, a p-type substrate plane orientation with a (100) crystal plane is prepared.
Next, a second conductivity type, for example, n ⁺ collector buried region 4 is formed in a portion of the silicon substrate 2 to be a collector region of SiGeHBT. For example, a silicon oxide film (not shown) is formed by thermal oxidation, and a portion of the silicon oxide film that becomes a collector region of SiGeHBT is opened. Through this opening, solid source diffusion by Sb ₂ O ₃ is performed on the silicon substrate 2. Thus, an n ⁺ collector buried region 4 is formed.

  Next, a semiconductor epitaxial layer 3 of a second conductivity type, for example, n-type, for example, having a resistivity of 1 to 5 Ωcm and a thickness of 0.6 to 2.0 μm is grown on the silicon substrate 2 by an existing technique. A semiconductor substrate 1 comprising a substrate 2 and a silicon semiconductor epitaxial layer 3 is formed.

Thereafter, an element isolation film 5 made of, for example, a silicon oxide film is formed by a LOCOS (Local Oxidation of Silicon) method.
That is, first, for example, the surface of the semiconductor substrate 1 is thermally oxidized to form a pad layer made of silicon oxide having a thickness of 50 nm, and a silicon nitride (Si ₃ N ₄ ) film having a thickness of 100 nm, for example, is formed thereon by CVD. Then, the silicon nitride film is subjected to pattern etching by photolithography to form an oxidation resistant mask layer having an opening in a portion where the element isolation film 5 is to be formed. Thereafter, steam oxidation at 1000 to 1050 ° C. is performed to form the element isolation layer 5 having a thickness of 300 to 800 nm, for example.

Next, after removing the oxidation-resistant mask layer, boron (B) ions are implanted with a dose of 100 to 720 keV and 1 × 10 ^{12 to} 5 × 10 ¹³ cm ⁻² , A p-type element isolation region 6 is formed between portions to be electrically isolated from each other.

Subsequently, for example, phosphorus (P) ions are implanted with a dose of 150 to 720 keV and 1 × 10 ^{12 to} 5 × 10 ¹³ cm ⁻² , and a collector electrode extraction region 7 connected to the n ⁺ collector buried region 4 is formed. Form.

Next, a silicon oxide film 8 is formed to a thickness of about 100 nm on the entire surface using tetraethoxysilane (TEOS) by low pressure CVD. Thereafter, heat treatment at 800 to 900 ° C. is performed to densify the silicon oxide film 8.
Subsequently, the silicon oxide film 8 is subjected to low damage etching, for example, dry etching and wet etching, using a resist mask matched with the opening in the base region, thereby forming the opening shown in FIG. 1B.

Next, the SiGe mixed crystal layer 9 (9A, 9B, 9C) is formed non-selectively at least in the formation region of the SiGe HBT by using an epitaxial technique.
In the SiGe mixed crystal layer 9, as described above, a single crystal SiGe mixed crystal layer is formed at a portion in contact with the semiconductor substrate 1, and a polycrystalline SiGe mixed crystal layer is formed on the silicon oxide 8.
The SiGe mixed crystal layer 9 is formed by using any one of an ultra-high vacuum CVD method, a molecular beam epitaxy method, and a reduced pressure chemical vapor deposition (RPCVD) method.

Here, a procedure for forming the SiGe mixed crystal layer 9 using the low pressure CVD method will be described below.
First, in order to remove organic substances adhering to the surface of the semiconductor substrate 1, for example, cleaning is performed using a mixed solution of sulfuric acid and hydrogen peroxide heated to a predetermined temperature.
Next, in order to remove particles on the semiconductor substrate 1, for example, cleaning is performed using a mixed solution of ammonia and hydrogen peroxide heated to a predetermined temperature.
Further, in order to remove metal contaminants and natural oxide film on the surface of the semiconductor substrate 1, cleaning is performed using a dilute hydrofluoric acid aqueous solution. In this cleaning with dilute hydrofluoric acid solution, hydrogen passivation treatment is also performed, and the exposed surface of the semiconductor substrate 1 is terminated with hydrogen.
Subsequently, the cleaned semiconductor substrate 1 is introduced into a film forming apparatus, carried into a load lock having a vacuum exhaust function, and vacuum exhaust is performed for a predetermined time.
Next, the semiconductor substrate 1 is carried into a reaction furnace connected to a load lock without opening it to the atmosphere, and the semiconductor substrate 1 is heated to about 900 ° C. while introducing hydrogen gas into the reaction furnace, and the semiconductor substrate 1 is heated for about 5 minutes. Perform hydrogen bake.
Further, after the temperature is lowered to a temperature of about 750 to 650 ° C. while introducing hydrogen gas, monosilane (SiH ₄ ), germane (GeH ₄ ) as raw material gases, and diborane (B ₂ H ₂ ) as impurity gas are used. Supply epitaxial growth. The pressure in the furnace at this time is set to 1.3 kPa to 13.3 kPa.

Then, the formation of the SiGe mixed crystal layer 9 by epitaxial growth is specifically performed by, for example, forming a silicon buffer layer 9A having a thickness of 5 to 20 nm and then forming a SiGe layer 9B having a germanium concentration of 15 atomic% by a thickness of 20 to 40 nm. After that, a silicon cap layer 9C is formed to a thickness of 20 to 40 nm. Further, during this growth, for example, a boron concentration of 5 × 10 ^{18 to} 3 × 10 ¹⁹ cm ^{−3 is applied} to a desired portion of the silicon germanium mixed crystal layer 9 (9A, 9B, 9C) as necessary. Impurities are doped so that

Next, a method of forming cobalt silicide in the base lead electrode portion will be described in detail with reference to FIGS.
First, after the SiGe mixed crystal layer 9 is formed as described above, the polycrystalline SiGe mixed crystal layer 9 other than the portion serving as the base extraction electrode portion is removed by dry etching.
Next, a silicon oxide film 20 is entirely formed to a thickness of about 100 nm by low pressure CVD using tetraethoxysilane (TEOS) by low pressure CVD.
Subsequently, a resist mask 21 is formed on the silicon oxide film 20 so as to extend to a portion slightly outside the silicon oxide film 12 in the emitter forming portion shown in FIG. Then, using this resist mask 21, the silicon oxide film 20 is patterned by dry etching so as to cover the emitter forming portion.
Then, using the same resist mask 21, boron (B) is applied to the polycrystalline layer portion of the SiGe mixed crystal layer 9 with a dose of, for example, 10 to 50 keV, 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ^−2. Ion implantation is performed (see FIG. 3A above).

Next, after removing the resist mask 21 by an existing technique, a polycrystalline silicon film 10 having a thickness of, for example, 50 to 100 nm is formed by a low pressure CVD method.
Thereafter, boron (B) is ion-implanted into the polycrystalline silicon film 10 with a dose of, for example, 10 to 50 keV, 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² (see FIG. 3B above).

Next, by using photolithography and dry etching, the silicon oxide film 20, the polycrystalline silicon film 10 thereon, and the polycrystalline silicon film 10 outside the mixed crystal layer 9 are removed.
Thereafter, a silicon oxide film 12 is entirely formed to a thickness of about 100 nm by low pressure CVD using tetraethoxysilane (TEOS). Furthermore, pattern etching is performed by photolithography and dry etching on the silicon oxide film 12 in a portion to be an emitter region, and the resist used as an etching mask is removed (see FIG. 3C above).

Thereafter, phosphorus (P) is ion-implanted into the surface of the semiconductor substrate 1 through the opening with a dose of, for example, 100 to 360 keV, 1 × 10 ^{12 to} 5 × 10 ¹² cm ⁻² . The region shown in FIG.

Next, a polycrystalline silicon film 14 having a thickness of, for example, 100 to 150 nm is formed on the entire surface by low pressure CVD.
Thereafter, an n-type impurity, for example, arsenic (As) is ion-implanted into the polycrystalline silicon film 14 at a dose of 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² at 30 to 70 keV.
Next, a silicon oxide film 22 having a thickness of, for example, 100 to 200 nm is formed on the entire surface of the polycrystalline silicon film 14 by using a low pressure CVD method using tetraethoxysilane (TEOS).

  Subsequently, arsenic (As) in the polycrystalline silicon film 14 is diffused by annealing at 1000 to 1100 ° C. for 5 to 30 seconds, so that an emitter region is formed in the single crystal layer portion of the SiGe mixed crystal layer 9. 15 is formed (see FIG. 3D above).

  Next, pattern etching is performed on the silicon oxide film 22, the polycrystalline silicon film 14, and the silicon oxide film 12 by photolithography and dry etching to form a multi-layer on the polycrystalline SiGe mixed crystal layer 9 serving as a base extraction electrode portion. After exposing the crystalline silicon film 10, the resist used as an etching mask is removed.

Next, the natural oxide film on the surface of the polycrystalline silicon film 10 is removed by dilute hydrofluoric acid (Dilute HF).
Thereafter, cobalt Co and titanium nitride TiN are formed by sputtering. At this time, cobalt Co is formed to a thickness of about 10 nm, and titanium nitride is formed to a thickness of 30 nm.
Subsequently, unreacted cobalt and titanium nitride adhering to the silicon oxide film other than the polycrystalline silicon film 10 are removed. For removal of the unreacted material, first, titanium nitride is removed using a mixed solution of sulfuric acid and hydrogen peroxide solution, and then cobalt is removed using a mixed solution of ammonia and hydrogen peroxide solution.
Thereafter, heat treatment is performed again to form a cobalt silicide layer (CoSi ₂ ) 11 (see FIG. 3E above).

Thereafter, a silicon oxide film 16 shown in FIG. 1A is entirely formed using tetraethoxysilane (TEOS) by low pressure CVD, and then an emitter electrode 17 is formed in the opening formed in the silicon oxide film 16. Metal electrodes to be the base electrode 18 and the collector electrode 19 are formed.
Thereby, the semiconductor device shown in FIG. 1A can be manufactured.

Here, FIG. 6 shows an impurity profile in the depth direction of SiGeHBT manufactured based on the above-described embodiment.
FIG. 6 shows that the base resistance can be reduced, and a semiconductor device with excellent performance can be manufactured.

In the above-described embodiment, the SiGe mixed crystal layer 9 is epitaxially grown in the base region. However, the mixed crystal layer may have other configurations.
The mixed crystal layer may be composed of silicon-germanium and carbon (Si _1-xy Ge _x Cy, abbreviated as SiGeC). In this case as well, the mixed crystal layer includes a necessary impurity (for example, boron) in the base portion.

  Further, the mixed crystal layer is not limited to the above-described three-layer structure 9A, 9B, 9C, and may be, for example, a two-layer structure of a silicon-germanium layer and a silicon layer.

  In the present invention, the silicon mixed crystal layer is composed of at least a silicon layer and a layer containing silicon and a group IV element (carbon, germanium, etc.).

  Further, not only the above-described cobalt silicide 11 but also other silicide films (for example, titanium silicide) can be formed on the surface of the base lead electrode portion to similarly reduce the resistance.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

1A is a schematic configuration diagram (cross-sectional view) of a semiconductor device according to an embodiment of the present invention. FIG. B is a cross-sectional view schematically showing the vicinity of a base region in FIG. 1A. It is sectional drawing to which the base region vicinity of FIG. 1A was expanded. 1A to 1E are process diagrams showing manufacturing steps of the semiconductor device of FIG. 1A. It is an expanded sectional view near the base region of the conventional SiGeHBT. FIG. 5 is an enlarged cross-sectional view of a configuration in which the silicon oxide film pattern is wider than in FIG. 4. It is a figure which shows the impurity profile of the depth direction of SiGeHBT in the semiconductor device of FIG. 1A.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Silicon substrate, 3 Semiconductor epitaxial layer, 4 Collector embedding area, 5 Element isolation film, 6 Element isolation area, 8, 12, 16 Silicon oxide film, 9 (silicon-germanium) mixed crystal layer, 9A (silicon ) Buffer layer, 9B SiGe layer, 9C (silicon) cap layer, 10,14 polycrystalline silicon film, 11 cobalt silicide

Claims (8)

A semiconductor device formed by forming a bipolar transistor having a base region made of an epitaxial layer so as to include an opening of an insulating film formed on a semiconductor substrate,
A base region composed of the epitaxial layer is formed by a silicon mixed crystal layer composed of a silicon layer, a layer including silicon, germanium, and carbon ,
The uppermost layer of the silicon mixed crystal layer is a silicon layer,
Cobalt silicide is formed on the single crystal silicon mixed crystal layer and the polycrystalline silicon mixed crystal layer in the base region composed of the silicon mixed crystal layer through a polycrystalline silicon film. apparatus.   2. The semiconductor device according to claim 1, wherein the thickness of the silicon layer as the uppermost layer of the silicon mixed crystal layer is 20 to 40 nm. A semiconductor device formed by forming a bipolar transistor having a base region made of an epitaxial layer so as to include an opening of an insulating film formed on a semiconductor substrate,
A base region composed of the above epitaxial layer is formed by a silicon mixed crystal layer having a three-layer structure of a buffer layer of a silicon layer, a SiGeC layer, and a silicon cap layer from the lower layer,
Cobalt silicide is formed on the single crystal silicon mixed crystal layer and the polycrystalline silicon mixed crystal layer in the base region composed of the silicon mixed crystal layer through a polycrystalline silicon film. apparatus.   4. The semiconductor device according to claim 3, wherein the thickness of the uppermost silicon layer of the silicon mixed crystal layer is 20 to 40 nm. A method of manufacturing a semiconductor device in which a bipolar transistor having a base region made of an epitaxial layer is formed on a semiconductor substrate,
Forming an insulating film on the semiconductor substrate and forming an opening in the bipolar transistor forming region of the insulating film;
Forming a silicon mixed crystal layer formed by a silicon layer, a layer having silicon, germanium, and carbon so as to include the opening, the uppermost layer being a silicon layer by epitaxial growth;
Forming a polycrystalline silicon film on the single crystal silicon mixed crystal layer and the polycrystalline silicon mixed crystal layer in the base region composed of the silicon mixed crystal layer; and
And a step of forming cobalt silicide on the surface of the polycrystalline silicon film.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the thickness of the silicon layer as the uppermost layer of the silicon mixed crystal layer is 20 to 40 nm. A method of manufacturing a semiconductor device in which a bipolar transistor having a base region made of an epitaxial layer is formed on a semiconductor substrate,
Forming an insulating film on the semiconductor substrate and forming an opening in the bipolar transistor forming region of the insulating film;
Forming a silicon mixed crystal layer having a three-layer structure of a buffer layer of a silicon layer, a SiGeC layer, and a silicon cap layer by epitaxial growth so as to include the opening;
Forming a polycrystalline silicon film on the single crystal silicon mixed crystal layer and the polycrystalline silicon mixed crystal layer in the base region composed of the silicon mixed crystal layer; and
And a step of forming cobalt silicide on the surface of the polycrystalline silicon film.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the thickness of the uppermost silicon layer of the silicon mixed crystal layer is 20 to 40 nm.

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