JP2003017601A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously perform both a high yield and a low manufacturing cost in the case of manufacturing a semiconductor device in which an insulated gate field effect transistor and a bipolar transistor are formed on a common semiconductor base. SOLUTION: A method for manufacturing the semiconductor device comprises a step of forming an epitaxial layer 35a as a base layer of the bipolar transistor, in a state in which a gate electrode 31 of the insulated gate field effect transistor having at least a compound film of a high melting point metal is covered with a diffusion preventive film 57 of the high melting point metal. Thus, the layer 35a can be formed in a state in which an exposed surface of the semiconductor base is not contaminated by the high melting point metal without depending upon a forming time and forming method of the compound film of the high melting point metal included in the electrode 31, and a base layer having no current leakage between a collector and an emitter can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which an insulated gate field effect transistor and a bipolar transistor are formed on a common semiconductor substrate.

[0002]

2. Description of the Related Art A semiconductor device in which an insulated gate field effect transistor and a bipolar transistor are formed on a common semiconductor substrate is used for a frequency converter of a communication device. In this case, high frequency bipolar transistors are required to operate at high speed. In order to increase the speed of the bipolar transistor, it is necessary to reduce the base width and increase the carrier concentration. However, if the base layer is formed by ion implantation of impurities, it is difficult to realize a thin base width due to channeling of impurities during ion implantation. Therefore, silicon (S
i) A method of epitaxially growing a base layer on a substrate has been considered.

However, even if a homojunction base layer is formed by epitaxial growth, if the carrier concentration of the base is increased, the number of holes injected from the base to the emitter is increased and the current gain is reduced. Therefore, silicon germanium (Si _1-x G having a narrower band gap than Si)
e _x , hereinafter referred to as SiGe) is epitaxially grown on a single-crystal Si substrate, and the fact that the potential barrier for holes is higher than that for electrons is used to inject holes into the emitter. Heterojunction bipolar transistors are being considered that can be significantly reduced.

In a heterojunction bipolar transistor,
The base carrier concentration can be increased to reduce the base resistance, and the current amplification factor (h _FE ) is sufficiently large.
Can be obtained. As a result, high frequency characteristics can be realized while ensuring a sufficient breakdown voltage. Further, by grading the concentration profile of germanium (Ge), it is possible to realize a high-speed bipolar transistor having excellent high-frequency characteristics in which the carrier base transit time (τ _B ) is shortened.

On the other hand, in order to increase the speed of an insulated gate field effect transistor and the like, by using a gate electrode in which a silicide film of a refractory metal such as tungsten (W) is laminated on a polycrystalline Si film, The resistance of the electrodes is reduced. Then, in manufacturing a semiconductor device in which the insulated gate field effect transistor and the bipolar transistor are formed on a common semiconductor substrate as described above, contamination, damage, etc. on the surface of the semiconductor substrate after several manufacturing steps are performed. In order to prevent the dielectric strength failure of the gate insulating film caused by the above, the gate electrode of the insulated gate field effect transistor is formed before forming the base layer of the bipolar transistor.

FIGS. 3 and 4 show a method for manufacturing a BiCMOS semiconductor device in which an npn type SiGe heterojunction bipolar transistor, an npn type normal bipolar transistor and a CMOS transistor are formed on a common semiconductor substrate. A first conventional example is shown.

In this first conventional example, as shown in FIG. 4, an oxide film (not shown) is formed on the surface of a semiconductor substrate 11 which is a p-type and a (100) plane orientation such as a Si substrate by thermal oxidation. No)
Then, an opening is formed in the oxide film to define a buried collector formation region in the transistor formation region 12 for the SiGe heterojunction bipolar transistor and the transistor formation region 13 for the normal bipolar transistor.

Next, antimony oxide (Sb) is formed on the semiconductor substrate 11 and the oxide film exposed through the opening of the oxide film.
₂ O ₃ ) film (not shown) is formed, and Sb is solid-phase diffused from the Sb ₂ O ₃ film to the semiconductor substrate 11 through the opening of the oxide film to form n ⁺ -type buried collectors 14 and 15. To do. After that, the Sb ₂ O ₃ film and the oxide film are removed. Then, for example, the resistivity is 1 to 5 Ωcm and the thickness is 0.6 to 2.
An n-type semiconductor layer 16 such as a 0 μm Si layer is epitaxially grown on the semiconductor substrate 11,
And the semiconductor layer 16 form a semiconductor substrate 17.

Next, the element isolation insulating film 18 is formed by the following selective oxidation method. That is, the surface of the semiconductor layer 16 is thermally oxidized to form an oxide film (not shown) such as a SiO ₂ film having a thickness of 50 nm as a pad film, and a thickness of 100 nm is formed on the oxide film by a CVD method. Silicon nitride (S
An oxidation resistant mask film such as an i ₃ N ₄ ) film is formed. Then, an opening corresponding to the formation region of the element isolation insulating film 18 is formed in the oxide film and the oxidation resistant mask film by lithography and etching. Then, by steam oxidation at a temperature of about 1000 to 1050 ° C., for example, a thickness of 300 to 8
Element isolation insulating film 18 such as a SiO ₂ film having a thickness of about 00 nm
To form.

Next, after removing the oxidation-resistant mask film in the selective oxidation method, for example, the acceleration energy is 100 to 720.
By repeating the ion implantation of boron (B) having a dose of 1 × 10 ^{12 to} 5 × 10 ¹³ / cm ² at keV, a p ⁺ type element isolation region is formed between portions to be electrically isolated from each other. At the same time as 21 is formed, a p-type well 23 is formed in the transistor formation region 22 for nMOS transistor.

Subsequently, for example, the acceleration energy is 150 to
Dosage amount is 1 × 10 at 720 keV ¹²~ 5 x 10¹³/ C
m²The phosphorus (P) ion implantation is repeated multiple times.
To connect to the buried collectors 14 and 15 by
At the same time when the collector extraction regions 24 and 25 are formed, pM
N-type transistor forming region 26 for OS transistor
Well 27 is formed.

Then, by thermal oxidation at 800 to 900 ° C., for example, a SiO ₂ film having a thickness of 7 to 10 nm is formed on the surface of the semiconductor substrate 17 on which the element isolation insulating film 18 in the transistor forming regions 22 and 26 is not formed. Forming the gate insulating film 28. Then, a semiconductor film such as a polycrystalline Si film doped with a high concentration of n-type impurities and a silicide film of a refractory metal such as W are sequentially deposited on the entire surface by a CVD method. Then, these films are patterned by lithography and dry etching to form the transistor formation region 2
A gate electrode 31 is formed at 2 and 26.

Next, the transistor forming regions 12, 22,
26 and collector extraction region of transistor formation region 13
Areas 25 and are covered with resist (not shown). And this
1x10 using the resist as a mask¹²~ 5 x 10¹³/ C
m²BF with the dose amount₂By implanting
The p-type link base 3 in the transistor formation region 13.
Form 2. Then, the resist is removed. And
For example, tetraethoxysilane (TEOS) is used as the source gas.
SiO of about 100 nm thickness by low pressure CVD method ₂Membrane, etc.
The insulating film 33 is deposited on the entire surface.

Next, a resist (not shown) having a pattern having an opening corresponding to the base formation region of the transistor formation region 12 is formed on the insulating film 33. Then, the opening 34 is formed in the insulating film 33 by, for example, dry etching using this resist as a mask and subsequent wet etching.
To form. At this time, dry etching is performed to increase the dimensional accuracy of the openings 34 and the like due to its anisotropy, and wet etching is performed to suppress damage to the surface of the semiconductor substrate 17 exposed through the openings 34. Is. After that, the resist on the insulating film 33 is removed. Figure
3 (a) shows the transistor forming regions 12 and 2 in this state.
2 is shown.

Next, in order to remove the organic substances such as the residue of the resist adhering to the surface of the semiconductor substrate 17, for example, a mixed liquid of sulfuric acid and hydrogen peroxide solution heated to a predetermined temperature is used to form the semiconductor substrate. Wash 17. In addition, the semiconductor substrate 1
In order to remove the particles on the semiconductor substrate 7, the semiconductor substrate 17 is washed with, for example, a mixed liquid of ammonia water and hydrogen peroxide water heated to a predetermined temperature. Further, the semiconductor substrate 17 is washed with dilute hydrofluoric acid in order to remove the metal contaminants and the natural oxide film on the surface of the semiconductor substrate 17. In the cleaning with dilute hydrofluoric acid, hydrogen passivation processing is also performed, and the exposed surface of the semiconductor substrate 17 is terminated with hydrogen.

Next, the semiconductor substrate 17 which has been subjected to the cleaning treatment.
Are loaded into a low pressure CVD apparatus. At this time, first, the semiconductor substrate 17 is loaded into the load lock chamber having a vacuum evacuation function, and the load lock chamber is evacuated for a predetermined time. After that, the semiconductor substrate 17 is carried into the reaction furnace connected to the load lock chamber without exposing the semiconductor substrate 17 to the atmosphere. Then, while introducing hydrogen gas into the reaction furnace, about 90
The temperature of the semiconductor substrate 17 is raised to 0 ° C., and hydrogen baking is performed for about 5 minutes.

After that, while continuing the introduction of hydrogen gas,
The temperature in the reaction furnace is lowered to about 750 to 650 ° C., and monosilane (SiH ₄ ) gas and germane (GeH ₄ ) gas as a source gas and diborane (B as an impurity gas are used.
₂ H ₆ ) gas is supplied into the reaction furnace to deposit a semiconductor layer 35, which is a SiGe mixed crystal layer, on the entire surface of the semiconductor substrate 17 and the insulating film 33 exposed through the opening 34.
The pressure in the reaction furnace at this time is 1.3 kPa to 13.3 k.
Pa. The thickness of the semiconductor layer 35 is 40 to 60 n.
m, the germanium concentration is 5 to 20 atomic%, and the boron concentration is 5 × 10 ^{18 to} 3 × 10 ¹⁹ / cm ^{3 so} that the flow rate of each gas and the deposition time are controlled.

FIG. 3B shows the transistor type in this state.
The formation area 12 is shown. Before starting this low pressure CVD
Exposes the semiconductor substrate 17 through the opening 34 in the insulating film 33.
Since it is exposed, half of the semiconductor layer 35 exposed
The portion on the conductor base 17 becomes the epitaxial layer 35a.
Thus, the portion on the insulating film 33 becomes the polycrystalline layer 35b. Semi-conductor
The body layer 35 is formed by ultra high vacuum C in addition to the low pressure CVD method as described above.
It may be formed by the VD method or the molecular beam epitaxy method.
It Further, as the semiconductor layer 35, the SiGe mixture as described above is used.
Germanium containing impurities necessary for the base in addition to the crystalline layer
Nium carbon (Si _1-xyGe_xC_y) Mixed crystal layers and Si
A layer etc. may be formed.

After that, the semiconductor layer 35 is covered with a resist (not shown) having a pattern of the base layer and the base take-out electrode in the transistor formation region 12, and the polycrystalline layer 35b is subjected to dry etching using this resist as a mask. Then, using a resist (not shown) that exposes only the transistor formation region 26 as a mask, for example, 1 ×
By implanting BF ₂ with a dose amount of 10 ^{12 to} 5 × 10 ¹³ / cm ² , the p-type source / drain 36 is formed.
To form. Further, the n-type source / drain 37 is formed in the transistor formation region 22 by the same method.

Next, the intrinsic base 38 is formed by ion implantation of impurities using a resist (not shown) that exposes only the intrinsic base formation region of the transistor formation region 13. After removing the resist, for example, 80
By performing heat treatment at 0 to 850 ° C. for 10 to 30 minutes, the source / drain 36 and 37 and the intrinsic base 38 are formed.
Activates the impurities in it.

Next, for example, an insulating film 41 such as a SiO ₂ film having a thickness of 100 to 150 nm is deposited on the entire surface by a low pressure CVD method using TEOS as a raw material gas. Then, the insulating films 4 are formed in the openings 42 and 43 corresponding to the emitter forming regions of the transistor forming regions 12 and 13 by lithography and RIE.
1, 33 and the gate insulating film 28. Then R
The resist used as the IE mask is removed.

Next, a semiconductor film 44 such as a polycrystal Si film having a thickness of 100 to 150 nm is deposited on the entire surface by a low pressure CVD method, and an acceleration energy of 30 to 70 keV and 1 is applied.
Arsenic (A) at a dose of × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ²
n-type impurities such as s) are ion-implanted into the semiconductor film 44. Then, the semiconductor film 44 is processed by lithography and RIE into a pattern of a conductive film to which the emitter electrode wirings of the transistor formation regions 12 and 13 are connected.

Next, for example, an insulating film 45 such as a SiO ₂ film having a thickness of 200 to 300 nm is deposited on the entire surface by a low pressure CVD method using TEOS as a source gas. And 100
By heat treatment at 0 to 1100 ° C. for 5 to 30 seconds, As is diffused from the semiconductor film 44 into the epitaxial layer 35a and the intrinsic base 38 through the openings 42 and 43 to form the emitters 46 and 47. After that, the semiconductor film 44, the polycrystalline layer 35b, the link base 32, the collector extraction regions 24 and 25, the source / drain 36 and 37, and the connection hole 48 reaching the gate electrode 31 are formed into the insulating films 45, 41 and 33.
And the gate insulating film 28.

Then, the emitter electrode wiring 51, the base electrode wiring 52, the collector electrode wiring 53 of the bipolar transistor, the source / drain electrode wiring 54 and the gate electrode wiring 55 of the MOS transistor are formed, and further a surface protective film (not shown). Etc. are formed to complete this BiCMOS semiconductor device. In the above manufacturing method, the opening 3
On the semiconductor substrate 17 and the insulating film 3 exposed through
Although the semiconductor layer 35 is deposited on the entire surface of the semiconductor substrate 3, the semiconductor layer 35 may be selectively deposited only on the exposed semiconductor substrate 17.

Next, a second conventional example of the invention of the present application, which is a method of manufacturing a BiCMOS semiconductor device, will be described. In this second conventional example, a gate insulating film is formed for a MOS transistor, and a semiconductor film doped with a high concentration of impurities is processed into a pattern of a gate electrode, followed by a low pressure CVD method using TEOS as a source gas. Then, an insulating film such as a SiO ₂ film is deposited on the entire surface. Then, an opening corresponding to the base formation region of the heterojunction bipolar transistor is formed in this insulating film or the like to form an epitaxial layer or the like as a base layer.

After that, an insulating film is again deposited on the entire surface, and M
An opening is formed in the insulating film to expose only the semiconductor film processed into the pattern of the OS transistor gate electrode. In this state, a refractory metal film such as titanium (Ti) is deposited on the semiconductor film and the insulating film by the sputtering method.
Then, a so-called salicide method is performed in which a silicide film of a refractory metal is formed in a self-aligned manner only on the gate electrode of the MOS transistor by the reaction between the exposed surface portion of the semiconductor film and the refractory metal film. Except for the above steps, this second conventional example also performs the same steps as the above-mentioned first conventional example.

[0027]

By the way, in the above-mentioned first conventional example, as shown in FIG. 3A, a semiconductor layer 35 for forming a base layer and a base take-out electrode of a heterojunction bipolar transistor. At the time of forming, the gate electrode 31 of the MOS transistor including the silicide film of the refractory metal is only covered with the insulating film 33 such as the SiO ₂ film. However, the SiO ₂ film cannot prevent the diffusion of the refractory metal, and when the semiconductor layer 35 is formed, the refractory metal that has diffused from the silicide film of the gate electrode 31 and floated in the cleaning liquid is contaminated. Semiconductor substrate 17
It also occurs on the exposed surface of.

As a result, as shown in FIG. 3B, the projection-like abnormal growth portion 56 is formed in the epitaxial layer 35a.
Occurs. In this abnormal growth portion 56, the crystal quality is remarkably impaired and disturbed from the single crystal state, so that current leakage occurs between the collector and emitter of the heterojunction bipolar transistor. Therefore, in this first conventional example, B
The yield of the iCMOS semiconductor device was extremely low.

On the other hand, in the above-mentioned second conventional example, the silicide film is not yet formed on the gate electrode at the time of forming the epitaxial layer or the like as the base layer of the heterojunction bipolar transistor. Therefore, the epitaxial layer as the base layer of the bipolar transistor can be formed in a state where the exposed surface of the semiconductor substrate 17 is not contaminated with the refractory metal, and the base layer having no current leakage between the collector and the emitter is formed. be able to. However, in this second conventional example, since the refractory metal film is deposited by the sputtering method as described above, a film forming apparatus by the sputtering method is required, and the manufacturing cost of the BiCMOS semiconductor device is high.

That is, in both the above-mentioned first and second conventional examples, it was difficult to simultaneously achieve both a high yield and a low manufacturing cost when manufacturing a BiCMOS semiconductor device. Therefore, an object of the invention of the present application is a semiconductor capable of simultaneously achieving both a high yield and a low manufacturing cost in manufacturing a semiconductor device in which an insulated gate field effect transistor and a bipolar transistor are formed on a common semiconductor substrate. A method of manufacturing a device is provided.

[0031]

In a method of manufacturing a semiconductor device according to the present invention, a gate electrode of an insulated gate field effect transistor including at least a compound film of refractory metal is covered with a diffusion preventive film of refractory metal. Then, an epitaxial layer is formed as a base layer of the bipolar transistor.

Therefore, the exposed surface of the semiconductor substrate is not contaminated with the refractory metal without depending on the formation timing and the formation method of the compound film of the refractory metal contained in the gate electrode of the insulated gate field effect transistor. In this state, an epitaxial layer as a base layer of the bipolar transistor can be formed, and a base layer of the bipolar transistor without current leakage between the collector and the emitter can be formed.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION The invention of the present application applied to a method for manufacturing a BiCMOS semiconductor device in which an npn type SiGe heterojunction bipolar transistor, an npn type normal bipolar transistor and a CMOS transistor are formed on a common semiconductor substrate. One embodiment will be described with reference to FIGS. Also in this embodiment, the same steps as those in the above-described first conventional example are performed until the insulating film 33 is deposited on the entire surface. However, in this embodiment, the thickness 30
A diffusion preventing film 57 of a refractory metal such as a Si ₃ N ₄ film of about 50 nm is deposited on the entire surface of the insulating film 33 by the low pressure CVD method.

Next, a resist (not shown) having a pattern having an opening extending to the outside of the base formation region of the transistor formation region 12 is formed on the diffusion prevention film 57, and dry etching is performed using this resist as a mask to prevent diffusion. Membrane 5
Apply to 7. Then, a resist (not shown) having a pattern having an opening corresponding to the base formation region of the transistor formation region 12 is formed on the diffusion prevention film 57 and the insulating film 33, and, for example, dry etching using this resist as a mask and An opening 34 is formed in the insulating film 33 by subsequent wet etching. FIG. 1A shows the transistor formation regions 12 and 22 in this state.

Then, again in the same process as in the above-mentioned first conventional example, as shown in FIG. 1B, the semiconductor layer 35, which is a SiGe mixed crystal layer, is exposed through the opening 34. It is deposited on the entire surface of the semiconductor substrate 17, the diffusion barrier film 57, and the insulating film 33. Also in this embodiment, the exposed portion of the semiconductor layer 35 on the semiconductor substrate 17 becomes the epitaxial layer 35a, and the diffusion prevention film 57 and the insulating film 33 are formed.
The upper portion becomes the polycrystalline layer 35b.

Then, the semiconductor layer 35 is covered with a resist (not shown) having a pattern of the base layer and the base extraction electrode in the transistor formation region 12, and the polycrystalline layer 35b and the diffusion preventive film 57 are dry-etched using the resist as a mask. Apply to. Since the diffusion prevention film 57 such as a Si ₃ N ₄ film and the gate electrode 31 including a refractory metal silicide film and the like are separated by the insulating film 33 such as a SiO ₂ film, Also, the diffusion prevention film 57 can be easily removed. After this dry etching, the same steps as those of the above-mentioned first conventional example are performed,
The BiCMOS semiconductor device shown in FIG. 2 is manufactured.

In this embodiment as described above, as shown in FIG. 1A, when the semiconductor layer 35 is formed, the gate electrode 31 of the MOS transistor including a silicide film of refractory metal or the like. Are covered with a diffusion preventing film 57 of a refractory metal. Therefore, the semiconductor layer 35 can be formed in a state where the exposed surface of the semiconductor substrate 17 is not contaminated by the refractory metal diffused from the silicide film of the gate electrode 31. Therefore, as shown in FIG. 1B, the epitaxial layer 35a having good crystal quality is formed without the protrusion-like abnormal growth portion 56 being generated.

Although the gate electrode 31 is formed in the transistor forming regions 22 and 26 by the polycrystalline Si film and the W silicide film in the above embodiment, the refractory metal compound film other than the W silicide film is W silicide. Even if it is used instead of the film, the same effect as that of the above embodiment can be obtained. Further, in the above-described embodiment, the Si ₃ N ₄ film is used as the diffusion preventing film 57 for the refractory metal, but any film other than the Si ₃ N ₄ film can be used as long as it can prevent the diffusion of the refractory metal. Membranes may be used.

Further, in the above-mentioned embodiments, all bipolar transistors are npn type, but these bipolar transistors may be pnp type. In addition, the above-described embodiments apply the invention of the present application to a method for manufacturing a BiCMOS semiconductor device in which an npn-type SiGe heterojunction bipolar transistor, an npn-type normal bipolar transistor, and a CMOS transistor are formed on a common semiconductor substrate. However, the invention of the present application can also be applied to a method of manufacturing a semiconductor device that does not include a normal bipolar transistor or a semiconductor device in which MOS transistors are either nMOS transistors or pMOS transistors.

[0040]

According to the method of manufacturing a semiconductor device according to the present invention, the collector-emitter is independent of the time and method of forming the compound film of the refractory metal contained in the gate electrode of the insulated gate field effect transistor. Since it is possible to form a base layer of a bipolar transistor having no current leakage in the semiconductor device, a high yield and a low manufacturing cost are required in manufacturing a semiconductor device in which an insulated gate field effect transistor and a bipolar transistor are formed on a common semiconductor substrate. Both can be achieved at the same time.

[Brief description of drawings]

FIG. 1 is a side cross-sectional view of a semiconductor device in the process of an embodiment of the present invention, (a) is a state before a base layer of a bipolar transistor is formed, and (b) is a base of the bipolar transistor. The respective states are shown after the layers are formed.

FIG. 2 is a side sectional view of a semiconductor device manufactured according to an embodiment of the present invention.

FIG. 3 is a side sectional view of a semiconductor device in the middle of a process of a conventional example of the present invention, in which (a) is a state before a base layer of a bipolar transistor is formed, and (b) is a base of the bipolar transistor. The respective states are shown after the layers are formed.

FIG. 4 is a side sectional view of a semiconductor device manufactured by a conventional example of the present invention.

[Explanation of symbols]

17 ... Semiconductor substrate, 31 ... Gate electrode, 35a ... Epitaxial layer (base layer), 57 ... Diffusion prevention film

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F003 BA13 BB04 BB07 BB08 BC08                       BE04 BF06 BF10 BH06 BH07                       BH08 BJ15 BM01 BP33                 5F048 AA07 AA10 AC05 BA14 BB05                       BB08 BB09 BG12 BG14 BH01                       CA03 CA13 CA14                 5F082 BA05 BA26 BA31 BC01 BC09                       EA24 EA25

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device in which an insulated gate field effect transistor having a gate electrode including at least a compound film of a refractory metal and a bipolar transistor having a base layer which is an epitaxial layer are formed on a common semiconductor substrate. 3. The method of manufacturing a semiconductor device, wherein the epitaxial layer is formed in a state in which at least the gate electrode is covered with the diffusion preventing film of the refractory metal. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the compound film is a tungsten silicide film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the diffusion barrier film is a silicon nitride film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the epitaxial layer is any one of a silicon germanium mixed crystal layer, a silicon germanium carbon mixed crystal layer, and a silicon layer. 5. The epitaxial layer is formed on the exposed semiconductor substrate, and at the same time, a polycrystalline layer is formed on a portion other than the exposed semiconductor substrate, or the exposed semiconductor substrate. The method of manufacturing a semiconductor device according to claim 1, wherein the epitaxial layer is selectively formed on the upper surface.