JP4748563B2 - Storage device - Google Patents

Description

  The present invention relates to a storage device, and relates to a technique effective for use in a storage device configured using a flash memory, for example.

A file memory having a storage capacity for a plurality of pages is configured by using a flash memory, a buffer memory for storing data for one page is provided, and one page unit between the buffer memory and the file memory is provided. When the power-off detection circuit detects a power-off on the system side during the data write operation from the buffer memory to the file memory, the battery backup function performs the data write operation for one page during the write operation. Japanese Laid-Open Patent Publication No. 7-44468 proposes a storage device which is continued.
Japanese Patent Laid-Open No. 7-44468

  When a battery is used as described above, there are many restrictions such as securing a battery storage part or providing a replacement mechanism in the package constituting the storage device, and the original function cannot be exhibited due to poor contact or the like. There is a problem in terms of reliability. Further, since the battery is expensive as a part, the cost is increased.

  An object of the present invention is to provide a storage device that is easy to use while achieving high reliability with a simple configuration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. Semiconductor non-volatile memory, control unit for performing memory access to such semiconductor non-volatile memory, power detection circuit for detecting presence / absence of power supply, and semiconductor memory and control unit charged up by power supply and when power is cut off A capacitor for supplying an operating voltage to the power supply and an interface circuit for transmitting / receiving signals to / from the outside are mounted in one package, and the power supply detection circuit detects the power-off state and the operating voltage formed by the capacitor is While preventing backflow to the outside, the interface circuit is controlled so as to be disconnected from the outside.

  A storage device that can be downsized and reduced in cost and is easy to use while achieving high reliability can be realized.

  FIG. 1 is a schematic block diagram showing an embodiment of a storage device according to the present invention. The storage device FlashMemoryDrive (hereinafter referred to as FMD) of this embodiment is not particularly limited, but a plurality of flash memories FLASH having a storage capacity of 512 Mbits are mounted in one package such as 32 or 64, for example. A file memory having a storage capacity for pages is configured. In these flash memories FLASH, data is exchanged with a driver provided in an interface circuit, that is, data is written and read out by a control unit CONT composed of a one-chip microcomputer or the like.

  The package further includes a power detection circuit and a capacitor for securing an operating voltage when the power is shut off. This capacitor operates so as to maintain the operating voltage until the normal termination of the flash memory FLASH is possible by the accumulated charge even when an unexpected power interruption occurs on the system side. In the flash memory FLASH, if the power supply on the system side is interrupted due to a power failure, operation, or mishandling during writing, the writing operation is interrupted. In general, data stored in a file format storage device is stored with an error detection / correction code added to a portion of a piece of data for the purpose of detecting or correcting error bits. If it is interrupted, the new and old data will be mixed, so the error detection and correction code will not match with the new or old code. Data is destroyed. Even during the erasing operation, a similar error occurs if erasing is left unfinished.

  In addition, when the operating voltage drops due to power interruption during writing and sufficient writing is not performed, it is erroneously determined that writing to the page is impossible, and it is registered as a defective page, resulting in a device failure substantially. Inconvenience occurs. The capacitor has a relatively large capacitance value of, for example, about 0.1 F in order to prevent the malfunction as described above and to ensure an operation voltage that always terminates normally in the flash memory FLASH. The

  The power supply detection circuit receives the power supply voltage VCC from the host HOST side such as a microcomputer and forms the operating voltage VDD of the internal circuit of the storage device FMD. The power supply detection circuit also has a function of preventing the accumulated charge of the capacitor from flowing back to the system side so that the holding voltage of the capacitor can be used effectively. In the simplest configuration, the power supply voltage VCC from the system side is charged up to the capacitor as the power supply voltage VDD of the storage device FMD through a unidirectional element such as a diode, and the control unit CONT, flash memory FLASH, interface circuit INF and power supply detection circuit. Further, the interface circuit INF keeps the signal to the control unit CONT side as it is so as not to respond to the meaningless input signal from the host HOST side by the power interruption detection signal of the voltage detection circuit. Keep state. The interface circuit INF exchanges data Data and control signal control signal Control with a host HOST such as a microcomputer.

  When an unexpected power cut-off occurs on the system side, the power cut-off detection circuit as described above prevents back-flow that maintains the operating voltage from the capacitor in the control unit CONT and the flash memory FLASH, and the interface circuit INF The system is controlled so as not to respond to the signal from the system side, and in order to maintain the signal state immediately before the power is turned off, if the write operation is in progress, the write operation is continued as it is, so the write operation is terminated normally. be able to. Similarly, even during erasure, the erasing operation is continued and the erasing operation is normally terminated.

  The storage device FMD has, for example, the same outer size (70.0 × 100.0 × 9.5 mm) as that of a 2.5-inch hard disk drive device or the same outer size (101. 6 × 146.0 × 25.4 mm), and the connector pin connected to the interface circuit INF is the same as the 2.5 inch hard disk drive device or the 3.5 inch hard disk drive device. It is done. Thus, the storage device FMD of this embodiment is an HDD (Hard Disk Drive) compatible storage device.

  FIG. 2 is a schematic block diagram showing another embodiment of the storage device according to the present invention. In the storage device FMD of this embodiment, a reset signal generation circuit RSG is further mounted. The reset signal generation circuit RSG receives the power cutoff signal of the power supply detection circuit and the operation end signal IRQ from the control unit CONT, generates a reset signal, resets the control unit CONT, and returns to the initial state. Done. As a result, in order to maintain the signal state immediately before the power is shut off as described above, the write operation is continued and the write operation is terminated normally, or the erase operation is continued and the erase operation is normal. The reset signal generation circuit RSG detects that the operation has been terminated, and the control unit CONT is returned to the initial state to prevent unexpected operation. In other words, if a predetermined signal is left supplied by maintaining the signal of the interface circuit INF, an unexpected operation may occur when the voltage of the capacitor drops near the lower limit voltage of the control unit CONT. Prevent in advance.

  FIG. 3 shows a schematic circuit diagram of an embodiment of the flash memory used in the present invention. This embodiment is directed to a so-called NOR type flash memory FLASH, and a memory array section is typically provided with four main bit lines MBL and extending directions of the bit lines with respect to each main bit line MBL. The two sub-bit lines SBL, the two word lines, and the common source line provided corresponding to the sub-bit lines SBL arranged in the word line direction and arranged in the extending direction of the word lines are exemplarily shown. It is shown.

  A nonvolatile memory cell includes a source, a drain, a floating gate formed on a semiconductor substrate sandwiched between the source and the drain via a gate insulating film, and a control gate provided on the floating gate via an insulating film A stacked structure consisting of Such a memory cell is arranged at the intersection of the sub bit line SBL and the word line, the control gate is connected to the word line, the drain is connected to the sub bit line SBL, and the source is connected to the source line.

  A selection switch MOSFET is provided between the main bit line MBL and the sub bit line SBL. Among these switch MOSFETs, one switch MOSFET (SEL-Gate) is turned on by a selection signal formed by the sub gate decoder / driver SG-Dec + Dr, and one sub bit line SBL is connected to each main bit line MBL. Connected. Among the plurality of word lines WL, one word line WL is selected by a selection signal formed by the X decoder / driver X-Dec + Dr.

  The main bit line MBL is connected to the output node of the write pulse application circuit via a Y gate (Y-Gate) made of a switch MOSFET. The Y gate is selected by a Y decoder Y-Dec. The write pulse application circuit constitutes a write circuit. The main bit line MBL is divided into two sets, and the write circuit is provided for each. A pair of signal lines to which the output nodes of the two write circuits are connected are connected to the input terminals of the differential sense amplifier SA via the selection switch MOSFET. The switch MOSFET is controlled by a verify enable signal (Verify_EN).

  For example, in a normal read operation or write verify operation, a pair of main bit lines MBL is selected by the Y gate (Y-Gate), and the memory that flows through the selected sub bit line SBL to one main bit line MBL. A current flows, and the precharge voltage of the other main bit line MBL is used as a reference voltage. The sense amplifier SA senses the potential change of the main bit line MBL corresponding to the presence or absence of the memory current flowing through the selected sub bit line SBL using the reference voltage.

  FIG. 4 is a schematic circuit diagram showing another embodiment of the flash memory used in the present invention. This embodiment is directed to a so-called NAND flash memory FLASH, in which memory cells are connected in series to form a sub-bit line.

  An example of the operation of the flash memory FLASH used in the present invention will be described. Although not particularly limited, the following description is directed to a multi-level (four-level) flash memory FLASH. In the erase operation, a negative high voltage is applied to the word line, and an electron FN tunnel current is caused to flow from the floating gate to the substrate side through the gate insulating film accumulated in the floating gate to release the electrons of the floating gate. .

  In the erase operation, first, a first erase verify is performed. For example, the read operation is performed by setting the voltage of the word line to 1.6V, and if the threshold voltage of the storage transistor is 1.6 V or less, the erase operation is terminated without doing anything because it is in the erase state. If at least one of the storage transistors corresponding to the word line is on, an erase operation is performed. That is, a negative high voltage such as −16 V is applied to the word line, and an FN tunnel current of electrons flows from the floating gate to the substrate side through the gate insulating film accumulated in the floating gate, thereby causing electrons in the floating gate to flow. To release.

  Thereafter, a second erase verify is performed. This erase verify is the same as the first erase verify, and the read operation is performed by setting the voltage of the word line to 1.6 V, and the erase operation is repeated until the threshold voltage of the storage transistor becomes 1.6 V or less. And erase verify are repeated. In such an erasing operation, the erasing operation is repeated in batches in units of word lines including the memory transistors already in the erasing state or the erasing state, so that the threshold voltage distribution in the erasing state ("11") Will become relatively wide. Therefore, a depletion prevention process is performed to narrow the threshold voltage to the erased state (“11”).

  When the batch erase operation is completed as described above, the depletion detection is performed. In this depletion detection, the voltage of the word line is set to 1.2 V, and if there is no storage transistor having a threshold voltage lower than that, the erase operation ends there. If at least one memory transistor has a threshold voltage of 1.2 V or less, a write bit is set correspondingly, and the designated word line, that is, the control gate of the memory transistor to be written is set as described above, for example. Is applied by applying a write word line voltage such as 18.1 V (volt) to the drain or channel thereof, for example. This writing is aimed at minute writing back.

  As a result, in the memory transistor to be written, an FN (Fowler Nordheim) tunnel phenomenon occurs between the control gate and the channel, electrons are injected from the channel to the floating gate, and the threshold voltage rises. Further, a write inhibit voltage of, for example, 5V is applied to the drain or channel of the memory cell that is coupled to the designated word line and is not to be written, and the voltage between the control gate and the channel is compressed, so that the FN tunnel phenomenon does not occur. The threshold voltage of the memory cell does not change.

  By repeatedly performing such write (write-back) write verify, the threshold voltage of the memory transistor detected as depleted is set to 1.2 V or higher. Then, an erase state ("11") word disturb detection is performed, the word line voltage is set to 2.0 V, and it is confirmed that the disturb voltage to which the threshold voltage of the storage transistor is applied is 2.0 V or less. To complete the erase operation. If even one memory transistor has a threshold voltage exceeding 2.0 V, it is treated as an erasure failure (abnormal termination) and switched to another sector as necessary.

  The write operation of the multilevel flash memory FLASH of this embodiment is started from a write bias operation for a storage transistor, that is, a “01” cell having the highest fourth threshold voltage as a target value after writing. The write bias operation for the “01” cell is performed by a search write operation, a normal write operation, and respective verify operations. That is, data latch processing corresponding to the presence / absence of writing is performed on the data latch corresponding to the “01” cell, and a write operation is performed with a relatively long pulse width such as 100 μs after a plurality of search writes and verifications. Is done.

  In the writing to the “01” cell, the threshold voltage should be 4.8 V or higher. Therefore, as described above, the pulse width is relatively increased to 100 μs, and the change ΔVth in the threshold voltage at one time is performed. Is increased so as to shorten the writing time. For example, in the case of a device having normal write characteristics, the write operation is completed by about twice. In this way, except for the search writing, the application time of the write word line voltage is increased from the beginning to make it relatively rough, and the required number of verify operations is, for example, 2 times, and the required write time is also corresponding. It is set to be short.

  The write operation for the “00” cell and the “10” cell is performed in the same manner as described above. That is, at the start of writing, search writing and verification as described above are inserted a plurality of times. Since the threshold voltage distribution by the write operation for the “00” cell and the “10” cell needs to be controlled with high accuracy so as to be within a relatively narrow range, for example, for the “00” cell, In the normal write operation after the search write, the write pulse application time TN (the pulse width of the Nth write pulse) is TN = 1.2 × (TN-1 cumulative time) − (TN-1 cumulative time). Set to This is not particularly limited, but is similarly performed for the “10” cell. As a result, the amount of change ΔVth in the threshold voltage is reduced, the required number of verify operations is increased to 8 times, for example, and the required write time is increased to several times that of the “01” cell.

  During a write operation, a high word line voltage such as 18.1 V is commonly applied to a designated word line of the memory array, that is, a control gate of a storage transistor coupled to the selected word line. At this time, among the storage transistors coupled to the selected word line of the memory array, the bit line to which the drain of the storage transistor to be written (hereinafter referred to as the write target cell) is coupled, that is, the global bit line and the local bit line (Hereinafter, referred to as a write target bit line) is selectively applied with 0V, 2V, 3V in accordance with the logical value of the write data, and the memory cells (hereinafter referred to as write non-target cells) that are not set as write targets. All of the bit lines to which the drains are coupled (hereinafter referred to as write non-target bit lines) are set to a write inhibit voltage of 5V.

  As a result, a voltage of 18V, 16V, or 15V is applied between the control gates and channels of the “01” cell, “00” cell, and “10” cell, respectively. Due to the FN tunnel phenomenon, an amount of electrons corresponding to the voltage between the control gate and the channel is injected, and the threshold voltage rises accordingly. That is, the “00” cell has a smaller threshold voltage change width than the “01” cell, and the “10” cell may have a smaller threshold voltage change width than the “01” cell. The applied voltage is reduced to increase the threshold controllability and prevent the device characteristics from deteriorating.

  When the write operation is completed for the “01” cell, “00” cell and “10” cell as described above, the elastic / disturb detection is performed in the order of “11” cell, “10” cell and “00” cell. To be implemented. First, the word line selection level is set to 2.0 V for the “11” cell, and it is detected that the threshold voltage does not exceed the upper limit of the erased state (disturbance). Hereinafter, the “10” cell and the “00” cell are detected. On the other hand, the selection level of the word line is set to 3.2 V and 4.5 V, and it is detected that the upper limit value of each threshold voltage is not exceeded, that is, that no erotic writing is performed.

  In the verify operation after the search write, it is possible to detect that the voltage has been written higher than the set voltage, but it is not possible to detect that the write is performed beyond the threshold voltage distribution. Such an elastic detection operation is required. When an error occurs due to the above-described elastic / disturb detection, an erase operation is performed, and a series of write operations from the “01” cell is performed again. If it is determined that the defect is the second time in the elastic / disturb detection, the process ends. For example, the word line (sector) is switched to a spare sector if possible.

  As described above, the erasing / writing operation is performed by a plurality of times of erasing / erasing verification or writing / writing verification. Therefore, it is necessary to spend a relatively long time to complete the normal operation. For this reason, during an erase operation or a write operation, when an unexpected power interruption occurs on the system side, the time required for the end of normal operation is continuously performed by the voltage (charge) held in the capacitor. Thus, a storage device FMD that can be reduced in size and cost and is easy to use while achieving high reliability with a simple configuration can be realized.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, as the nonvolatile memory element, a ferroelectric memory can be used in addition to the flash memory FLASH. The power supply detection circuit may supply power to the internal circuit by a switch such as a MOSFET and turn off the MOSFET when the host (system) side power supply is shut off. The package can be applied to a smaller and thinner card in addition to the same outer size of the HDD. In the package in the card state, the capacitance value of the capacitor mounted on the package may be small, but the number of flash memories mounted on the package is also small, so that the function as described above can be sufficiently exhibited. In this case, it is convenient to configure the control unit CONT, the power supply detection circuit, and the interface circuit INF with one semiconductor chip. The present invention can be widely used as a storage device.

It is a schematic block diagram which shows one Example of the memory | storage device based on this invention. It is a schematic block diagram which shows another Example of the memory | storage device based on this invention. 1 is a schematic circuit diagram showing an embodiment of a flash memory used in the present invention. It is a schematic circuit diagram which shows another Example of the flash memory used for this invention.

Explanation of symbols

HOST ... Host (system), FLASH ... Flash memory, CONT ... Control unit, INF ... Interface circuit, FMD ... Storage device.

Claims (7)

A semiconductor non-volatile memory, a control unit that performs memory access to the semiconductor non-volatile memory, and a power detection circuit that detects the presence or absence of power supply are mounted in one package, and are connected to the host via an HDD compatible connector. An HDD compatible storage device that is connected and operated by the power supplied from the host when the host is operating, and performs data writing and data reading from the host,
In the above package,
A capacitor having a capacitance value of at least 0.1 F, and arranged so that charge accumulation is performed by a power source supplied from the host when the host is operating;
Means for disconnecting the connection between the host and the storage device and preventing the backflow of the operating voltage formed by the capacitor to the host side when the power supply detection circuit detects the interruption of the power supply from the host ;
Is further installed,
In a state of being disconnected from the host, which is arranged to perform the operations by the operation voltage formed by the capacitor, or means not receive a command from the subsequent host, it was ordered from the host power off before operation A storage device characterized by having a part that terminates. In claim 1,
As a means not to receive commands from the host, it has an interface circuit that exchanges signals with the outside,
The power supply detection circuit detects a power cut-off state, controls the interface circuit to disconnect from the outside, and terminates the operation commanded by the host. In claim 2,
The interface circuit includes a driver,
A storage device, wherein data is input / output to / from the outside via the driver. In claim 1,
From the charge-up the capacitor by the power supply from the host when the operation of the host, storage device, wherein the benzalkonium to supply operating voltage to the semiconductor nonvolatile memory and the control unit at the time of power-off. In claim 1,
The part that finishes the operation instructed by the host before the power is cut off outputs a predetermined memory operation end signal from the control unit, and a reset signal is obtained by a logical operation of the power cut-off state from the power detection circuit and the end signal And a reset signal generation circuit for resetting the control unit. In claim 5,
The package includes an outer size and a connector pin corresponding to a 2.5 inch or 3.5 inch hard disk drive device,
A storage device having compatibility with the 2.5-inch or 3.5-inch hard disk drive. A storage device that operates with the power supplied from the host while connected to the host and performs data writing and data reading from the host,
A semiconductor nonvolatile memory unit;
A control unit for controlling access to the semiconductor nonvolatile memory unit;
An interface unit in which data writing and data reading from the host are performed in an HDD compatible specification;
A power detection circuit for detecting the presence or absence of power supply from the host;
A capacitor having a capacitance value of at least 0.1 F and arranged so that charge is stored by a power source supplied from the host when the host is operating;
Is mounted in one package,
When the power detection circuit detects the interruption of power supply from the host,
The power supply to the interface unit, the semiconductor nonvolatile memory unit, and the control unit is switched to an operating voltage formed by the accumulated charge of the capacitor, and the interface unit is controlled to connect the storage device and the host. Separation process,
In a state where the control unit is disconnected from the host, the control unit operates with an operating voltage formed by the accumulated charge of the capacitor, and finishes the operation commanded by the host before the power is shut off;
A storage device configured to execute

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