JP4745960B2 - マイクロプロセッサにおいてデータ推測オペレーションを識別する推測ポインタ - Google Patents

マイクロプロセッサにおいてデータ推測オペレーションを識別する推測ポインタ Download PDF

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Publication number
JP4745960B2
JP4745960B2 JP2006508587A JP2006508587A JP4745960B2 JP 4745960 B2 JP4745960 B2 JP 4745960B2 JP 2006508587 A JP2006508587 A JP 2006508587A JP 2006508587 A JP2006508587 A JP 2006508587A JP 4745960 B2 JP4745960 B2 JP 4745960B2
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Japan
Prior art keywords
data
speculative
speculation
unit
verification
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JP2006508587A
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Japanese (ja)
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JP2006525595A5 (enExample
JP2006525595A (ja
Inventor
エイ． フィリッポ マイケル
ケイ． ピケット ジェイムズ
ティー． サンダー ベンジャミン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Investigating Or Analysing Biological Materials (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP2006508587A 2003-05-02 2004-01-09 マイクロプロセッサにおいてデータ推測オペレーションを識別する推測ポインタ Expired - Fee Related JP4745960B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/429,159 US7266673B2 (en) 2003-05-02 2003-05-02 Speculation pointers to identify data-speculative operations in microprocessor
US10/429,159 2003-05-02
PCT/US2004/000483 WO2004099978A2 (en) 2003-05-02 2004-01-09 Apparatus and method to identify data-speculative operations in microprocessor

Publications (3)

Publication Number Publication Date
JP2006525595A JP2006525595A (ja) 2006-11-09
JP2006525595A5 JP2006525595A5 (enExample) 2011-04-28
JP4745960B2 true JP4745960B2 (ja) 2011-08-10

Family

ID=33310560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006508587A Expired - Fee Related JP4745960B2 (ja) 2003-05-02 2004-01-09 マイクロプロセッサにおいてデータ推測オペレーションを識別する推測ポインタ

Country Status (8)

Country Link
US (1) US7266673B2 (enExample)
JP (1) JP4745960B2 (enExample)
KR (1) KR101057163B1 (enExample)
CN (1) CN100373330C (enExample)
DE (1) DE112004000741B4 (enExample)
GB (1) GB2418045B (enExample)
TW (1) TWI318371B (enExample)
WO (1) WO2004099978A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7721054B2 (en) * 2005-01-18 2010-05-18 Texas Instruments Incorporated Speculative data loading using circular addressing or simulated circular addressing
US8595557B2 (en) * 2005-02-23 2013-11-26 International Business Machines Corporation Method and apparatus for verifying memory testing software
US7921280B2 (en) * 2008-06-27 2011-04-05 Intel Corporation Selectively powered retirement unit using a partitioned allocation array and a partitioned writeback array
US8880854B2 (en) * 2009-02-11 2014-11-04 Via Technologies, Inc. Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment register
US8707015B2 (en) 2010-07-01 2014-04-22 Advanced Micro Devices, Inc. Reclaiming physical registers renamed as microcode architectural registers to be available for renaming as instruction set architectural registers based on an active status indicator
US8589892B2 (en) 2010-11-21 2013-11-19 International Business Machines Corporation Verification of speculative execution
US8745599B2 (en) * 2012-01-19 2014-06-03 National Tsing Hua University Probabilistic pointer analysis method using SSA form
US10776123B2 (en) 2018-12-03 2020-09-15 Advanced Micro Devices, Inc. Faster sparse flush recovery by creating groups that are marked based on an instruction type
CN112559048B (zh) * 2019-09-25 2023-12-12 阿里巴巴集团控股有限公司 一种指令处理装置、处理器及其处理方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5740393A (en) * 1993-10-15 1998-04-14 Intel Corporation Instruction pointer limits in processor that performs speculative out-of-order instruction execution
US5903741A (en) * 1995-01-25 1999-05-11 Advanced Micro Devices, Inc. Method of allocating a fixed reorder buffer storage line for execution results regardless of a number of concurrently dispatched instructions
US6665792B1 (en) * 1996-11-13 2003-12-16 Intel Corporation Interface to a memory system for a processor having a replay system
US6212626B1 (en) 1996-11-13 2001-04-03 Intel Corporation Computer processor having a checker
US5966544A (en) 1996-11-13 1999-10-12 Intel Corporation Data speculatable processor having reply architecture
US6735688B1 (en) 1996-11-13 2004-05-11 Intel Corporation Processor having replay architecture with fast and slow replay paths
US5781752A (en) 1996-12-26 1998-07-14 Wisconsin Alumni Research Foundation Table based data speculation circuit for parallel processing computer
US6381691B1 (en) * 1999-08-13 2002-04-30 International Business Machines Corporation Method and apparatus for reordering memory operations along multiple execution paths in a processor
DE10085438B4 (de) 2000-02-14 2006-01-05 Intel Corporation, Santa Clara Prozessor mit Wiederholarchitektur mit schnellen und langsamen Wiederholpfaden
US6877086B1 (en) 2000-11-02 2005-04-05 Intel Corporation Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter
US6718839B2 (en) 2001-06-26 2004-04-13 Sun Microsystems, Inc. Method and apparatus for facilitating speculative loads in a multiprocessor system
EP1402349A2 (en) 2001-06-26 2004-03-31 Sun Microsystems, Inc. Method and apparatus for facilitating speculative stores in a multiprocessor system
US6952764B2 (en) 2001-12-31 2005-10-04 Intel Corporation Stopping replay tornadoes
US7363470B2 (en) 2003-05-02 2008-04-22 Advanced Micro Devices, Inc. System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor

Also Published As

Publication number Publication date
CN100373330C (zh) 2008-03-05
DE112004000741B4 (de) 2008-02-14
TW200502849A (en) 2005-01-16
TWI318371B (en) 2009-12-11
US20040221140A1 (en) 2004-11-04
CN1784654A (zh) 2006-06-07
KR20060004974A (ko) 2006-01-16
WO2004099978A3 (en) 2005-12-08
DE112004000741T5 (de) 2006-05-11
GB0521335D0 (en) 2005-11-30
GB2418045B (en) 2007-02-28
GB2418045A (en) 2006-03-15
KR101057163B1 (ko) 2011-08-17
JP2006525595A (ja) 2006-11-09
US7266673B2 (en) 2007-09-04
WO2004099978A2 (en) 2004-11-18

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