JP2006525595A5 - - Google Patents

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Publication number
JP2006525595A5
JP2006525595A5 JP2006508587A JP2006508587A JP2006525595A5 JP 2006525595 A5 JP2006525595 A5 JP 2006525595A5 JP 2006508587 A JP2006508587 A JP 2006508587A JP 2006508587 A JP2006508587 A JP 2006508587A JP 2006525595 A5 JP2006525595 A5 JP 2006525595A5
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JP
Japan
Prior art keywords
data
verification
speculation
data speculation
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006508587A
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English (en)
Japanese (ja)
Other versions
JP4745960B2 (ja
JP2006525595A (ja
Filing date
Publication date
Priority claimed from US10/429,159 external-priority patent/US7266673B2/en
Application filed filed Critical
Publication of JP2006525595A publication Critical patent/JP2006525595A/ja
Publication of JP2006525595A5 publication Critical patent/JP2006525595A5/ja
Application granted granted Critical
Publication of JP4745960B2 publication Critical patent/JP4745960B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2006508587A 2003-05-02 2004-01-09 マイクロプロセッサにおいてデータ推測オペレーションを識別する推測ポインタ Expired - Fee Related JP4745960B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/429,159 US7266673B2 (en) 2003-05-02 2003-05-02 Speculation pointers to identify data-speculative operations in microprocessor
US10/429,159 2003-05-02
PCT/US2004/000483 WO2004099978A2 (en) 2003-05-02 2004-01-09 Apparatus and method to identify data-speculative operations in microprocessor

Publications (3)

Publication Number Publication Date
JP2006525595A JP2006525595A (ja) 2006-11-09
JP2006525595A5 true JP2006525595A5 (enExample) 2011-04-28
JP4745960B2 JP4745960B2 (ja) 2011-08-10

Family

ID=33310560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006508587A Expired - Fee Related JP4745960B2 (ja) 2003-05-02 2004-01-09 マイクロプロセッサにおいてデータ推測オペレーションを識別する推測ポインタ

Country Status (8)

Country Link
US (1) US7266673B2 (enExample)
JP (1) JP4745960B2 (enExample)
KR (1) KR101057163B1 (enExample)
CN (1) CN100373330C (enExample)
DE (1) DE112004000741B4 (enExample)
GB (1) GB2418045B (enExample)
TW (1) TWI318371B (enExample)
WO (1) WO2004099978A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7721054B2 (en) * 2005-01-18 2010-05-18 Texas Instruments Incorporated Speculative data loading using circular addressing or simulated circular addressing
US8595557B2 (en) * 2005-02-23 2013-11-26 International Business Machines Corporation Method and apparatus for verifying memory testing software
US7921280B2 (en) * 2008-06-27 2011-04-05 Intel Corporation Selectively powered retirement unit using a partitioned allocation array and a partitioned writeback array
US8880854B2 (en) * 2009-02-11 2014-11-04 Via Technologies, Inc. Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment register
US8707015B2 (en) 2010-07-01 2014-04-22 Advanced Micro Devices, Inc. Reclaiming physical registers renamed as microcode architectural registers to be available for renaming as instruction set architectural registers based on an active status indicator
US8589892B2 (en) 2010-11-21 2013-11-19 International Business Machines Corporation Verification of speculative execution
US8745599B2 (en) * 2012-01-19 2014-06-03 National Tsing Hua University Probabilistic pointer analysis method using SSA form
US10776123B2 (en) 2018-12-03 2020-09-15 Advanced Micro Devices, Inc. Faster sparse flush recovery by creating groups that are marked based on an instruction type
CN112559048B (zh) * 2019-09-25 2023-12-12 阿里巴巴集团控股有限公司 一种指令处理装置、处理器及其处理方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5740393A (en) * 1993-10-15 1998-04-14 Intel Corporation Instruction pointer limits in processor that performs speculative out-of-order instruction execution
US5903741A (en) * 1995-01-25 1999-05-11 Advanced Micro Devices, Inc. Method of allocating a fixed reorder buffer storage line for execution results regardless of a number of concurrently dispatched instructions
US6665792B1 (en) * 1996-11-13 2003-12-16 Intel Corporation Interface to a memory system for a processor having a replay system
US6212626B1 (en) 1996-11-13 2001-04-03 Intel Corporation Computer processor having a checker
US5966544A (en) 1996-11-13 1999-10-12 Intel Corporation Data speculatable processor having reply architecture
US6735688B1 (en) 1996-11-13 2004-05-11 Intel Corporation Processor having replay architecture with fast and slow replay paths
US5781752A (en) 1996-12-26 1998-07-14 Wisconsin Alumni Research Foundation Table based data speculation circuit for parallel processing computer
US6381691B1 (en) * 1999-08-13 2002-04-30 International Business Machines Corporation Method and apparatus for reordering memory operations along multiple execution paths in a processor
DE10085438B4 (de) 2000-02-14 2006-01-05 Intel Corporation, Santa Clara Prozessor mit Wiederholarchitektur mit schnellen und langsamen Wiederholpfaden
US6877086B1 (en) 2000-11-02 2005-04-05 Intel Corporation Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter
US6718839B2 (en) 2001-06-26 2004-04-13 Sun Microsystems, Inc. Method and apparatus for facilitating speculative loads in a multiprocessor system
EP1402349A2 (en) 2001-06-26 2004-03-31 Sun Microsystems, Inc. Method and apparatus for facilitating speculative stores in a multiprocessor system
US6952764B2 (en) 2001-12-31 2005-10-04 Intel Corporation Stopping replay tornadoes
US7363470B2 (en) 2003-05-02 2008-04-22 Advanced Micro Devices, Inc. System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor

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