JP4744934B2 - Spin transistor - Google Patents

Description

  The present invention relates to a spin transistor having a MOS structure, a programmable logic circuit using the same, and a magnetic memory using a tunnel magnetoresistive effect, and in particular, controls a memory state by a spin transistor having an amplifying action and spin injection in a plane direction. It relates to a magnetic memory.

  In recent years, research and development of spin electronics devices using the spin degree of freedom of electrons has been actively conducted. Application research based on the tunnel magnetoresistive effect (TMR) such as magnetic random access memory (MRAM) and reproducing magnetic head is also gaining momentum. In particular, a spin transistor in which a semiconductor and a magnetic material are combined has attracted attention.

  Typical spin transistor structures include diffusion type spin transistors (Mark Johnson type) (see Non-Patent Document 1), Supriyo Datta type (Spin Orbit Control Type Spin Transistor) (see Non-Patent Document 2), spin valve transistors (Non-Patent Document 1). Patent Document 3 and Non-Patent Document 4), single-electron spin transistors (see Non-Patent Document 5), and resonant spin transistors (see Non-Patent Document 6) have been proposed.

  Also, a spin transistor having a MOS structure in which a source and a drain are formed of a magnetic material and a point contact is provided between the channel and the drain has been proposed (see Patent Document 1). This point contact is sized to produce a quantum effect on spin-polarized electrons, and its resistance is significantly larger than the channel resistance. Since the interface resistance between the channel and the drain is the main factor that determines the magnetization dependence of the drain current, this spin transistor results in a large magnetoresistance ratio (MR ratio). Obtainable.

  A programmable logic circuit that can control the validity and invalidity of the logic gates by changing the memory state of the MRAM by configuring basic logic gates such as AND gates and OR gates by combining the MRAM and MOSFET. Has been proposed.

JP 2003-92412 A M. Johnson et al., Phys. Rev. B37, 5326, (1988) D. Datta et al., Appl. Phys. Lett. 56, 665 (1990) D. J. Monsma et al., Phys. Rev. Lett. 74, 5260 (1995) K. Mizushima et al., Phys. Rev. B58, 4660 (1998) K. Ono et al., J. Phys. Soc. Jpn 66, 1261 (1997) N. Akiba et al., Physica B256-258, 561 (1998)

  However, none of the above-described spin transistors has an amplification function, and only the switching function is utilized among the functions of the transistor.

  Further, the spin transistor described in Patent Document 1 has a problem that the response speed of the element is lowered because the resistance value at the point contact increases. Furthermore, there are examples in which high MR ratios can and cannot be achieved in experimental reports of spin transistors having point contacts, and such spin transistors are applied to logic circuits that are a collection of many elements. Had the problem of being difficult.

  Even a spin transistor having a structure without a point contact can increase the MR ratio if an intrinsic semiconductor is used as a semiconductor substrate and a magnetic semiconductor is used as a magnetic material used for a source and a drain. Specifically, a Schottky barrier is formed at the interface between the source and drain and the channel, and spin injection is performed through this Schottky barrier. A magnetic semiconductor is obtained, for example, by substituting a part of semiconductor atoms with a magnetic material such as Mn. However, magnetic semiconductors have not been able to obtain a good squareness ratio at room temperature at present and have a problem that they are limited to operation at low temperatures.

  Further, when a programmable logic circuit is constructed by combining MRAM and MOSFET, there is a problem that wiring between MRAM made of a magnetic layer and MOSFET made of a semiconductor layer becomes complicated.

  The present invention has been made in view of the above, and an object thereof is to provide a spin transistor having an amplification function and a nonvolatile memory function and having high reliability.

  Another object of the present invention is to provide a programmable logic circuit that solves the problem of conventional wiring by using the spin transistor according to the present invention.

  It is another object of the present invention to provide a magnetic memory capable of controlling the storage state by spin injection in the plane direction.

In order to solve the above-described problems and achieve the object, a spin transistor according to the present invention is formed of a semiconductor substrate and a ferromagnetic material magnetized in a first direction on the semiconductor substrate, and has a source or a drain. A first conductive layer functioning as either one, and a ferromagnetic material magnetized on the semiconductor substrate in either the first direction or a second direction antiparallel to the first direction. A second conductive layer functioning as either the source or the drain; and a portion located between the first conductive layer and the second conductive layer in the semiconductor substrate ; the first conductive layer; A channel portion for guiding electron spin to and from the second conductive layer; an insulating film located above the channel portion; a gate electrode located above the insulating film ; the first conductive layer and the second conductive layer At least of the conductive layer , A tunnel barrier layer disposed between said channel portion and toward characterized by comprising a.

A spin transistor according to the present invention includes a semiconductor substrate, a first conductive layer formed of a ferromagnetic material magnetized in a first direction on the semiconductor substrate, and functioning as either a source or a drain; Formed on the semiconductor substrate with a ferromagnetic material magnetized in one of the first direction and a second direction antiparallel to the first direction, and functions as either the source or the drain An electron spin formed between the second conductive layer and a portion of the semiconductor substrate located between the first conductive layer and the second conductive layer, wherein electron spin is generated between the first conductive layer and the second conductive layer; A guiding channel portion, a floating gate located above the channel portion, a gate electrode located above the floating gate, at least one of the first conductive layer and the second conductive layer, and the Characterized by comprising a tunnel barrier layer disposed between Yaneru portion.

  According to the spin transistor of the present invention, the memory function can be provided by controlling the magnetization direction in the second conductive layer in addition to the switching function and amplification function of the known MOS transistor. .

  In addition, according to the spin transistor of the present invention, the magnetization direction of the second conductive layer can be controlled by spin injection in the plane direction, thereby providing an effect that a memory function can be provided.

  Further, according to the programmable logic circuit of the present invention, since it is constructed by a spin transistor having a memory function, there is an effect that the wiring between the switching unit and the memory function unit can be simplified.

  Further, the magnetic memory according to the present invention has an effect that the magnetization direction of the magnetic recording layer can be controlled by spin injection in the plane direction.

  Hereinafter, embodiments of a spin transistor, a magnetic memory, and a programmable logic circuit according to the present invention will be described in detail with reference to the drawings. However, the drawings are schematic, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are different from the actual ones. Moreover, even when referring to the same part between the drawings, there are parts where the dimensions and ratios are different from each other.

(Embodiment 1)
The spin transistor according to the first embodiment is a MOS structure transistor in which a source and a drain are formed of a magnetic material, and a tunnel barrier film is formed between a channel and the source and / or drain. And

  FIG. 1 is a schematic cross-sectional view of the spin transistor according to the first embodiment. In FIG. 1, a spin transistor 100 is formed between a semiconductor substrate 10, a first conductive layer 12 and a second conductive layer 14 formed on the semiconductor substrate 10, and between the first conductive layer 12 and the semiconductor substrate 10. The tunnel barrier film 11a, the tunnel barrier film 11b formed between the second conductive layer 14 and the semiconductor substrate 10, and the semiconductor substrate 10 positioned between the first conductive layer 12 and the second conductive layer 14. The formed gate insulating film 30, the gate electrode 40 formed on the gate insulating film 30, the antiferromagnetic layer 16 formed on the first conductive layer 12, and the antiferromagnetic layer 16 were formed. The electrode 20a and the electrode 20b formed on the second conductive layer 14 are provided. The first conductive layer 12 is a layer that functions as one of the source and the drain of the MOS transistor, and the second conductive layer 14 is a layer that functions as the other of the source and the drain of the MOS transistor. The spin transistor 100 has the same structure as a conventional MOS transistor except that a ferromagnetic material is used as a source and a drain and tunnel barrier films 11a and 11b are formed. Therefore, the region of the semiconductor substrate 10 located immediately below the gate insulating film 30 and between the first conductive layer 12 and the second conductive layer 14 functions as a channel.

The semiconductor substrate 10 is, for example, an intrinsic semiconductor such as Si or Ge, a compound semiconductor such as GaAs or ZnSe, or a highly conductive semiconductor obtained by doping these semiconductors. The first conductive layer 12 is a ferromagnetic material that functions as a magnetic pinned layer, and its magnetization is fixed in a predetermined direction. In other words, most of the electrons contained in the first conductive layer 12 are polarized in a predetermined spin direction. In FIG. 1, the direction of electron spin in the first conductive layer 12 is the front side of the drawing. The first conductive layer 12 is, for example,
i) NiFe alloy, CoFe alloy, CoFeNi alloy
ii) (Co, Fe, Ni)-(Si, B) alloys, (Co, Fe, Ni)
-(Si, B)-(P, Al, Mo, Nb, Mn) based alloys
iii) Amorphous materials such as Co- (Zr, Hf, Nb, Ta, Ti) films
iv) Co ₂ (CrxFe _1-x ) Al series, Co ₂ MnAl, Co ₂ MnSi
Heusler alloys (half metal)
v) It can be formed of at least one ferromagnetic thin film selected from the group consisting of dilute magnetic semiconductor materials such as SiMn and GeMn, or a multilayer film thereof.

  The first conductive layer 12 preferably has unidirectional anisotropy. The thickness of the first conductive layer 12 is preferably 0.1 nm to 100 nm, and more preferably 0.4 nm or more, which is a thickness that does not cause superparamagnetism.

The antiferromagnetic layer 16 is a thin film formed in order to fix the magnetization of the first conductive layer 12 more firmly and stably. As the antiferromagnetic layer 16, for example, FeMn, PtMn, PtCrMn, NiMn, IrMn, NiO, or Fe ₂ O ₃ can be used.

  The second conductive layer 14 is a ferromagnetic material that functions as a magnetic recording layer, and its magnetization direction is changed by an externally applied magnetic field or spin injection. That is, the magnetization direction of the second conductive layer 14 can be controlled to be “parallel” or “anti-parallel” with respect to the magnetization direction of the first conductive layer 12. Here, “parallel” with respect to a certain magnetization direction means that the directions of two magnetizations substantially coincide with each other, and “anti-parallel” with respect to a certain magnetization direction means that the directions of two magnetizations are approximately the same. Means the opposite. In the following description, the expressions “parallel” and “antiparallel” follow this definition. In FIG. 1, the magnetization direction of the second conductive layer 14 is controlled from the front side to the front side or back side. The second conductive layer 14 can also be formed of a ferromagnetic thin film similar to the first conductive layer 12. The second conductive layer 14 desirably has uniaxial anisotropy, and the thickness thereof is approximately the same as that of the first conductive layer 12. As the second conductive layer 14, a two-layer structure of soft magnetic layer / ferromagnetic layer or a three-layer structure of ferromagnetic layer / soft magnetic layer / ferromagnetic layer may be used.

  Further, Ag, Cu, Au, Al, Mg, Si, Bi, Ta, B, C, O, N, Pd, Pt, Zr, and the like are formed on the magnetic material forming the first conductive layer 12 and the second conductive layer 14. By adding nonmagnetic elements such as Ir, W, Mo, Ru, Re, Os, Nb, and B, various physical properties such as magnetic properties, crystallinity, mechanical properties, and chemical properties may be adjusted.

The tunnel barrier films 11a and 11b are made of, for example, an oxide or nitride of Si, Ge, Al, Ga, Mg, Ti, and Ta. The gate insulating film 30 is formed of the same material as the gate insulating film of the conventional MOS transistor, for example, SiO ₂ .

  Gate electrode 40, electrode 20a, and electrode 20b are also formed of an electrode material used in a conventional MOS transistor. The gate electrode 40 is made of, for example, polycrystalline silicon, and the electrodes 20a and 20b and the gate lead electrode (not shown) are made of, for example, aluminum or polycrystalline silicon.

  FIG. 2A is a diagram schematically illustrating the spin transistor 100 when the magnetization direction of the second conductive layer 14 is “parallel” to the magnetization direction of the first conductive layer 12. FIG. 2B is an energy band diagram of the first conductive layer 12, the second conductive layer 14, and the tunnel barrier films 11a and 11b in this case. FIG. 2B is an energy band diagram when the first conductive layer 12 and the second conductive layer 14 are formed of a half metal material such as a Heusler alloy.

  Between regions having the same magnetization direction, electron spin polarized in the same direction as the magnetization direction tends to flow. Therefore, when the magnetization directions are in a “parallel” relationship, the spin transistor 100 has a switching function similar to that of a conventional MOS transistor. That is, by controlling the voltage applied to the gate electrode 40, the conduction state between the electrode 20a and the electrode 20b can be controlled.

  More specifically, the voltage applied between the electrodes 20a and 20b causes the electrons of the first conductive layer 12 to be excited to the conduction band, passes through the energy barrier of the tunnel barrier film 11a, and decreases by the gate voltage. It moves to the conduction band of the second conductive layer 14 through the conduction band of the channel region and the energy barrier of the tunnel barrier film 11b. When the magnetization directions are in a “parallel” relationship, as shown in FIG. 2B, the energy band structure of the first conductive layer 12 and the second conductive layer 14 for the Up spin electrons and Down spin electrons, respectively. The energy band structure of is consistent. The Up spin electrons move to the Up spin band, and the Down spin electrons move to the Down spin band. Therefore, the excited electrons can easily move from the first conductive layer 12 to the second conductive layer 14. .

  FIG. 3A is a diagram schematically illustrating the spin transistor 100 when the magnetization direction of the second conductive layer 14 is “anti-parallel” to the magnetization direction of the first conductive layer 12. FIG. 3-2 is an energy band diagram of the first conductive layer 12, the second conductive layer 14, and the tunnel barrier films 11a and 11b in this case. FIG. 3-2 is also an energy band diagram in the case where the first conductive layer 12 and the second conductive layer 14 are formed of a half metal material.

  Between regions of different magnetization directions, electron spin polarized in one magnetization direction hardly flows into the region of the other magnetization direction. Therefore, when the magnetization direction is “antiparallel”, the spin transistor 100 is equivalent to a MOS transistor in an OFF state. That is, even when a voltage higher than the threshold value is applied to the gate electrode 40, a current hardly flows between the electrode 20a and the electrode 20b.

  When the magnetization directions are in an “antiparallel” relationship, as shown in FIG. 3-2, the energy band structure of the first conductive layer 12 and the second conductive layer for the Up spin electrons and the Down spin electrons, respectively. The 14 energy band structures do not match. Therefore, it becomes difficult for the excited electrons to move from the first conductive layer 12 to the second conductive layer 14.

  Therefore, when the current between the electrode 20 a and the electrode 20 b is measured in a state where a gate voltage equal to or higher than the threshold is applied, the magnetization direction of the second conductive layer 14 is “parallel to the magnetization direction of the first conductive layer 12. "Or" anti-parallel ". This means that the spin transistor 100 has a memory function. In particular, the second conductive layer 14 maintains its magnetization direction unless energy is applied from the outside by a current magnetic field, spin injection, or the like, so that a nonvolatile memory function is realized.

  The spin transistor 100 also has an amplification function similar to that of a conventional MOS transistor. When a gate voltage higher than the threshold is applied, the band edge of the valence band of the semiconductor located in the channel region increases (as a result, the band edge of the conduction band decreases), so that the first conductive layer 12 injects into the channel. The emitted electrons can easily move to the second conductive layer 14 side through the channel. In other words, the ease with which electrons pass through the channel region, that is, the amount of electrons depends on the magnitude of the gate voltage. This means that the current between the first conductive layer 12 and the second conductive layer 14 can be amplified by controlling the gate voltage.

  Further, in the known MOS type spin transistor, an intrinsic semiconductor is used as a semiconductor substrate to form a Schottky barrier. However, in the spin transistor 100, a tunnel barrier is formed instead of the Schottky barrier. A compound semiconductor or a doped semiconductor can be used as the substrate. That is, the selectivity of the material constituting the spin transistor 100 can be increased.

  As described above, according to the spin transistor 100 according to the first embodiment, the first conductive layer 12 and the second conductive layer 14 are provided as MOS transistors formed of a magnetic material or a magnetic semiconductor, and the first conductive layer 12 is provided. Tunnel barrier films 11a and 11b are formed between the layer 12 and the channel and between the second conductive layer 14 and the channel, respectively. Thereby, in addition to the known switching function and amplification function of the MOS transistor, a memory function can also be provided by controlling the magnetization direction in the second conductive layer 14.

  Even when the tunnel barrier film is formed only between one of the first conductive layer 12 and the channel and between the second conductive layer 14 and the channel, the above effect can be obtained. it can.

  Further, in FIG. 1, nothing is formed on the side surfaces of the gate insulating film 30 and the gate electrode 40, but insulating films 42a and 42b are formed on these side surfaces as in the spin transistor 100 ′ shown in FIG. Also good. The insulating films 42a and 42b can be formed by, for example, CVD (Chemical Vapor Deposition) or sputtering, and then selective etching by RIE (Reactive Ion Etching) or the like.

  Further, in FIG. 1, the first conductive layer 12 and the second conductive layer 14 are embedded in the semiconductor substrate 10, but these conductive layers are formed on the main surface of the semiconductor substrate as shown in FIG. (This type is hereinafter referred to as a surface stacked MOS structure). In the spin transistor 1100 shown in FIG. 5, the tunnel barrier films 11a and 11b are formed on the surface of the semiconductor substrate 1110, respectively. The first conductive layer 12 is formed on the tunnel barrier film 11a, and the second conductive layer 14 is formed on the tunnel barrier film 11b. In FIG. 5, the same reference numerals are given to the portions common to FIG. 1. The channel is formed immediately below the gate insulating film 30. As described above, even if the first conductive layer 12 and the second conductive layer 14 are spin transistors having a surface stacked MOS structure in which the main surface of the semiconductor substrate 1110 is formed, the above-described effect of FIG. 1 can be enjoyed. Can do. Further, as in the spin transistor 1100 ′ shown in FIG. 6, between the gate insulating film 30 and the gate electrode 40 and the first conductive layer 12, and between the gate insulating film 30 and the gate electrode 40 and the second conductive layer 14. Insulating films 42a and 42b may be formed respectively.

(Embodiment 2)
The spin transistor according to the second embodiment is characterized by having a structure in which the magnetization direction of the second conductive layer 14 shown in FIG. 1 is controlled by a current magnetic field. FIG. 7 is a schematic cross-sectional view of the spin transistor according to the second embodiment. In the spin transistor 110, the surface of the antiferromagnetic layer 16, the gate electrode 40, and the semiconductor substrate layer 10 and the side surface of the gate insulating film 30 are covered with the insulating layer 60. 1 differs from FIG. 1 in that the first word line 111a is formed on the insulating layer 60, and the semiconductor layer 10 and the silicon oxide layer 50 are part of an SOI (Silicon On Insulator) substrate. The second word line 111 b is formed in the silicon oxide layer 50. A support substrate (not shown) such as Si is provided under the silicon oxide layer 50.

  The first word line 111a and the second word line 111b are arranged substantially orthogonally so as to sandwich the second conductive layer 14, and are made of, for example, Al or Cu. In FIG. 7, the first word line 111 a extends in a direction across the first conductive layer 12 and the second conductive layer 14, and the second word line 111 b extends in a direction along the second conductive layer 14.

  By applying a current pulse to each of the first word line 111a and the second word line 111b, a synthetic magnetic field is generated in a region sandwiched between these word lines, that is, a region where the second conductive layer 14 is located. The direction of the synthetic magnetic field can be controlled by the direction of the current pulse. The magnetization direction of the second conductive layer 14 can be controlled by the direction of the synthetic magnetic field.

  Therefore, according to the spin transistor 110 according to the second embodiment, the magnetization direction of the second conductive layer 14 of the spin transistor 100 according to the first embodiment can be controlled by the current magnetic field.

  This current magnetic field control structure can also be applied to the spin transistor having the surface stacked MOS structure shown in FIG.

(Embodiment 3)
In the spin transistor according to the third embodiment, a magnetic coating layer made of a magnetic material is formed on a part of the surface of the first word line and / or the second word line of the spin transistor according to the second embodiment. It is characterized by. FIG. 8A is a schematic cross-sectional view of the spin transistor according to the third embodiment. This spin transistor 120 is different from FIG. 7 in that a magnetic covering layer (Yoke) 122 a is formed on the upper surface and side surfaces of the first word line 121 a on the insulating layer 60, and that A magnetic coating layer (Yoke) 122b is formed on the lower and side surfaces of the two word lines 121b. The magnetic coating layers 122a and 122b are made of permalloy, for example. FIG. 8-2 is a sectional view taken along line XX of FIG. As shown in FIGS. 8A and 8B, the magnetic coating layers 122a and 122b have a U-shaped cross section. Of the surfaces of the first word line 121a and the second word line 121b, the second conductive layer 14 is used. The magnetic coating layer is not formed on the surface facing the direction.

  According to the spin transistor 120 according to the third embodiment, a current magnetic field is locally applied to the second conductive layer 14 by the magnetic coating layers 122a and 122b formed on the first word line 121a and the second word line 121b. It becomes possible to give. In other words, the current pulse required to control the magnetization direction of the second conductive layer 14 can be further reduced, and thereby various problems associated with an increase in the current pulse, that is, EM (Electro Migration) and current pulse An increase in the area of the generation circuit can be avoided.

FIG. 9 is a graph showing drain current characteristics of the spin transistor according to the third exemplary embodiment. The first conductive layer 12 of the spin transistor used to obtain this graph is a ferromagnetic multilayer film of (Co ₉₀ Fe ₁₀ ) ₈₅ B ₁₅ / PtMn / Ta / Poly-Si, and the second conductive layer 14 Is a ferromagnetic multilayer film of (Co ₉₀ Fe ₁₀ ) ₈₅ B ₁₅ / Ta / Poly-Si. In FIG. 9, the solid line represents a graph in which the magnetization direction of the second conductive layer 14 is “parallel” to the magnetization direction of the first conductive layer 12, and the broken line represents a state in which the magnetization direction is “anti-parallel”. ing. Further, in each of the “parallel” state and the “antiparallel” state, respective graphs when the gate voltage V _g is 0.2V, 0.6V, 0.9V, and 1.4V are shown. As shown in FIG. 9, in the “parallel” state, a sufficiently large drain current flows even when a smaller source-drain voltage is applied than in the “antiparallel” state. That is, different current characteristics are shown between the “parallel” state and the “anti-parallel” state, which means the development of the memory function. Further, the drain current increases with the increase of the gate voltage. This means that the spin transistor 120 has an amplification function.

FIG. 10 is a graph showing drain current characteristics of another example of the spin transistor according to the third exemplary embodiment. Note that the first conductive layer 12 and the second conductive layer 14 of the spin transistor used to obtain this graph are multilayer films using a half-metal material Co ₂ MnAl. Specifically, the first conductive layer 12, as _{Co 2 MnAl / (Co 90 Fe} 10) 85 B 15 / PtMn / Ta / Poly-Si ferromagnetic multi-layer film using the second conductive layer 14, Co ₂ A ferromagnetic multilayer film of MnAl / (Co ₉₀ Fe ₁₀ ) ₈₅ B ₁₅ / Cu / (Co ₉₀ Fe ₁₀ ) ₈₅ B ₁₅ / PtMn / Ta / Poly-Si was used. Further, in each of the “parallel” state and the “anti-parallel” state, respective graphs when the gate voltage V _g is 0.4 V, 0.8 V, 1.2 V, and 1.5 V are shown. Also in FIG. 10, the drain current characteristic similar to that of FIG. 9 is shown. However, since the sufficiently large drain current flows in the “antiparallel” state in the graph shown in FIG. 10 in comparison with the graph in FIG. 9, it is necessary to apply a larger source-drain voltage. This means that a larger MR ratio can be obtained by using a half metal material as the first conductive layer 12 and the second conductive layer 14.

(Embodiment 4)
The spin transistor according to the fourth embodiment is characterized by having a structure in which the magnetization direction of the second conductive layer 14 of the spin transistor according to the first embodiment is controlled by spin injection. FIG. 11A is a schematic cross-sectional view of the spin transistor according to the fourth embodiment. FIG. 11B is a plan view of the spin transistor shown in FIG. This spin transistor 130 is different from FIG. 1 in that a first multilayer film and a second multilayer film that are separated from each other by a predetermined distance are formed on the second conductive layer 14.

  As shown in FIG. 11A, in the spin transistor 130, a nonmagnetic layer 131a and a magnetic pinned layer 132a are stacked in this order as a first multilayer film on the surface of the second conductive layer 14, and the second multilayer film is formed. As shown, a nonmagnetic layer 131b and a magnetic pinned layer 132b are stacked in that order. In particular, the first multilayer film and the second multilayer film are long along the longitudinal direction of the second conductive layer 14 and are parallel to each other. That is, the gap between the first multilayer film and the second multilayer film is also long along the longitudinal direction of the second conductive layer 14. The magnetic pinned layers 132 a and 132 b have a magnetization direction “anti-parallel” to each other, and are formed of the same magnetic material as that of the first conductive layer 12. The nonmagnetic layers 131a and 131b are made of, for example, Ag, Cu, Au, Al, Ru, Os, Re, Si, Bi, Ta, B, C, Pd, Pt, Zr, Ir, W, Mo, Nb, or the like. Made of alloy.

  An electrode 133a is formed on the magnetic pinned layer 132a, and an electrode 133b is formed on the magnetic pinned layer 132b. The electrodes 133a and 133b are made of, for example, aluminum or polycrystalline silicon.

  Spin injection into the second conductive layer 14 is performed by passing a current between the electrode 133a and the electrode 133b. Hereinafter, the control of the magnetization direction by the spin injection will be described. Here, as shown in FIG. 11A, the magnetization direction of the magnetic pinned layer 132a is “antiparallel” to the magnetization direction of the first conductive layer 12, and the magnetization direction of the magnetic pinned layer 132b is the first magnetization direction. It is assumed that it is “parallel” to the magnetization direction of the conductive layer 12.

  First, it is assumed that the magnetization direction of the second conductive layer 14 is recorded “parallel” to the magnetization direction of the first conductive layer 12. From this state, the magnetization direction of the second conductive layer 14 is reversed from “parallel” to “antiparallel” by spin injection. This magnetization reversal is performed by passing a current from the electrode 133b to the electrode 133a. In terms of electron movement, “anti-parallel” polarized electron spin (hereinafter referred to as anti-parallel spin) in the magnetic pinned layer 132a is injected into the second conductive layer 14 via the non-magnetic layer 131a. The Electron spins polarized in “parallel” in the second conductive layer 14 (hereinafter referred to as “parallel spins”) receive the torque of the injected antiparallel spins, and reverse the spin directions antiparallel. Further, the antiparallel spin that has reached the magnetic pinned layer 132b by the injection is reflected there because the magnetization direction of the magnetic pinned layer 132b is “parallel”. The reflected antiparallel spin further gives torque to the parallel spin in the second conductive layer 14 and reverses the spin direction of the parallel spin antiparallel. Thereby, the magnetization direction of the second conductive layer 14 can be reversed from “parallel” to “antiparallel”.

The current I _C ^AP required for this “parallel” → “anti-parallel” operation is
I _C ^AP = e · α · M · A _t [H + H _k + 2πM] / (h · g (0))
It is expressed as Here, alpha is Gilbert damping parameter, M is the magnetization, A _t is the volume of the second conductive layer 14, H is the magnetic field, H _k is the anisotropy constant, h is Planck's constant. The general formula g (π) of g (0) indicates the spin dependence at the interface between the magnetic pinned layer 132a and the nonmagnetic layer 131a and at the interface between the magnetic pinned layer 132b and the nonmagnetic layer 131b.
g (θ) = 1 / [− 4+ (1 + p) ³ · (3 + cos θ) / 4p ^3/2 ]
It is expressed as Here, p is the spin polarization rate.

  Next, it is assumed that the magnetization direction of the second conductive layer 14 is recorded “antiparallel” to the magnetization direction of the first conductive layer 12. From this state, the magnetization direction of the second conductive layer 14 is reversed from “antiparallel” to “parallel” by spin injection. This magnetization reversal is performed by flowing a current from the electrode 133a to the electrode 133b, contrary to the above-described "parallel" → "antiparallel" operation. In terms of electron movement, parallel spins in the magnetic pinned layer 132b are injected into the second conductive layer 14 through the nonmagnetic layer 131b. This inversion operation is the same as the above-described “parallel” → “antiparallel” operation except that the spin directions are different.

The current I _C ^P required for this “antiparallel” → “parallel” operation is
I _c ^P = e · α · M · A _t [H−H _k −2πM] / (h · g (π))
It is expressed as Since g (π)> g (0), the current I _c ^P is generally smaller than the current I _c ^AP .

  The magnetization direction control structure shown in FIGS. 11A and 11B can also be applied to the surface stacked MOS structure described above, as shown in FIG. In the spin transistor 1130 shown in FIG. 12, the first conductive layer 12 and the second conductive layer 14 are formed on the tunnel barrier films 11 a and 11 b formed on the surface of the semiconductor substrate 1110, respectively. The first multilayer film (nonmagnetic layer 131a, magnetic pinned layer 132a) and the second multilayer film (nonmagnetic layer 131b, magnetic pinned layer 132b) shown in FIGS. 11-1 and 11-2 are formed.

  In FIGS. 11A and 11B, the first multilayer film and the second multilayer film are long in the direction parallel to each other along the longitudinal direction of the second conductive layer 14, but the juxtaposed direction is 90 °. It may be rotated so that a gap is formed between the tip of the first magnetic multilayer film and the tip of the second multilayer film. FIG. 13A is a schematic cross-sectional view of the spin transistor according to the fourth embodiment in this case. FIG. 13B is a plan view of the spin transistor shown in FIG. In the spin transistor 140 shown in FIG. 13A, a nonmagnetic layer 141a and a magnetic pinned layer 142a are stacked in that order as a first multilayer film on the surface of the second conductive layer 14, and a nonmagnetic layer is formed as the second multilayer film. A layer (not shown) and a magnetic pinned layer 142b are stacked in that order. In particular, the first multilayer film and the second multilayer film are arranged so that the tips thereof face each other and a gap is formed between the tips. The magnetic pinned layers 142a and 142b are formed of the same material as the magnetic pinned layers 132a and 132b shown in FIG. 11A. The nonmagnetic layers 141a and 141b are also formed of the nonmagnetic layers 131a and 141b shown in FIG. It is made of the same material as 131b. An electrode 143a is formed on the magnetic pinned layer 142a, and an electrode 143b is formed on the magnetic pinned layer 142b. These electrodes are also formed of the same material as the electrodes 133a and 133b shown in FIG.

  The magnetization direction control structure shown in FIGS. 13A and 13B can also be applied to the surface stacked MOS structure described above, as shown in FIG. In the spin transistor 1140 shown in FIG. 14, the first conductive layer 12 and the second conductive layer 14 are formed on the tunnel barrier films 11 a and 11 b formed on the surface of the semiconductor substrate 1110, respectively. The first multilayer film (nonmagnetic layer 141a, magnetic pinned layer 142a) and the second multilayer film (nonmagnetic layer, magnetic pinned layer 142b) shown in FIGS. 13-1 and 13-2 are formed.

  As described above, according to the spin transistors 130, 1130, 140, and 1140 according to the fourth embodiment, the magnetization direction of the second conductive layer 14 can be controlled by spin injection. Since the synthesized magnetic field generated by the current magnetic field shown in the second and third embodiments has a spatial spread regardless of the layer structure of the spin transistor, it adversely affects the components other than the second conductive layer 14. There is a possibility of effect. In addition to the space occupied by the MOS structure, a space for arranging word lines is required. In the spin transistor according to the fourth embodiment, these structural defects that generate the current magnetic field are improved. Furthermore, since spin injection is performed with respect to the surface direction of the second conductive layer 14, the electron spin injected to control the magnetization direction does not flow through the tunnel barrier films 11a and 11b. Thereby, destruction of the tunnel barrier films 11a and 11b can be avoided.

  In FIG. 11A, an antiferromagnetic layer formed of the same material as the antiferromagnetic layer 16 between the magnetic pinned layer 132a and the electrode 133a and between the magnetic pinned layer 132b and the electrode 133b. May be provided. Thereby, the magnetization of the magnetic pinned layer 132a and the magnetic pinned layer 132b can be held more firmly and stably. The same applies to the spin transistors shown in FIGS. 12, 13-1, and 14.

  Furthermore, the spin injection structure that is a feature of the fourth embodiment can be applied to a spin transistor that does not include the tunnel barrier films 11a and 11b. That is, the magnetization direction of the second conductive layer can be controlled by spin injection even for a MOS type spin transistor in which a Schottky barrier is generated between the first conductive layer 12 and the second conductive layer 14 and the channel. is there.

(Embodiment 5)
The spin transistor according to the fifth embodiment is different from the spin transistor according to the fourth embodiment in that the magnetic pinned layer of at least one magnetic multilayer film is formed by a three-layer structure of magnetic layer / nonmagnetic layer / magnetic layer. It is a feature.

  FIG. 15A is a schematic cross-sectional view of the spin transistor according to the fifth embodiment. 15-2 is a plan view of the spin transistor shown in FIG. 15-1, and FIG. 15-3 is a cross-sectional view taken along line XI-XI of the spin transistor shown in FIG. 15-2. The spin transistor 150 shown in FIG. 15A differs from FIG. 13A in that a nonmagnetic layer 151a, a magnetic layer 152a, and a nonmagnetic layer 153a are formed on the surface of the second conductive layer 14 as a first multilayer film. And a magnetic layer 154a are stacked in that order, and as the second multilayer film, a nonmagnetic layer 152b and a magnetic layer 153b are stacked in that order. In addition, the magnetization directions of the magnetic layer 152a and the magnetic layer 153b have an “antiparallel” relationship, and the magnetization directions of the magnetic layer 154a and the magnetic layer 153b have a “parallel” relationship. That is, the two magnetic layers 152a and 154a constituting the first multilayer film have different magnetization directions.

  The magnetic layers 152a, 154a, and 153b are formed of the same material as the magnetic pinned layer described in the fourth embodiment, and the nonmagnetic layers 151a, 153a, and 152b are also the same as the nonmagnetic layer described in the fourth embodiment. It is made of a new material. An electrode 155a is formed on the magnetic layer 154a, and an electrode 154b is formed on the magnetic layer 153b. These electrodes are also formed of the same material as the electrodes described above.

  By adopting a structure in which two magnetic layers having different magnetization directions are sandwiched via nonmagnetic layers, such as magnetic layer 152a / nonmagnetic layer 153a / magnetic layer 154a, antiferromagnetic interaction is achieved between the two magnetic layers. And the magnetization direction of the magnetic layer is more firmly and stably maintained. That is, this three-layer structure can provide the same action as the antiferromagnetic layer 16 formed on the first conductive layer 12. It is more effective to further provide an antiferromagnetic layer adjacent to this three-layer structure. By adjusting the film thickness of the two magnetic layers of the magnetic layer / nonmagnetic layer / magnetic layer constituting the magnetic pinned layer, the magnetization shift of the second conductive layer 14 that is a magnetic recording layer can be arbitrarily set. . Further, the magnetization fixation by this three-layer structure can reduce the stray field from the magnetic layer.

  The magnetic layer of the second multilayer film may be realized by a three-layer structure of magnetic layer / nonmagnetic layer / magnetic layer. In this case, one of the first multilayer film and the second multilayer film is formed by a multilayer structure in which a nonmagnetic layer / magnetic layer is stacked an odd number of times, and the other is a multilayer in which a nonmagnetic layer / magnetic layer is stacked an even number of times. It needs to be formed by the structure.

  This magnetization pinning by the three-layer structure can also be applied to the first conductive layer 12 that is a magnetic pinned layer. That is, the structure composed of the first conductive layer 12 and the antiferromagnetic layer 16 may be a three-layer structure of magnetic layer / nonmagnetic layer / magnetic layer. In this case, the antiferromagnetic layer 16 may be arranged adjacent to the three-layer structure.

  Further, the magnetization direction control structure shown in FIGS. 15A to 15C can be applied to the above-described surface stacked MOS structure as shown in FIG. In the spin transistor 1150 illustrated in FIG. 16, the first conductive layer 12 and the second conductive layer 14 are formed on the tunnel barrier films 11 a and 11 b formed on the surface of the semiconductor substrate 1110, respectively. The first multilayer film (nonmagnetic layer 151a, magnetic layer 152a, nonmagnetic layer 153a, magnetic layer 154a) and second multilayer film (nonmagnetic layer 152b, magnetic pinned) as shown in FIGS. 13-1 and 13-2 Layer 153b) is formed.

  As described above, according to the spin transistors 150 and 1150 according to the fifth embodiment, the magnetic pinned layers for performing spin injection into the second conductive layer 14 are magnetic layers / nonmagnetic layers / magnetic layers 3. Formed by layer structure. With this three-layer structure, the magnetization of the magnetic pinned layer can be held more firmly and stably.

(Embodiment 6)
In the spin transistor according to the sixth embodiment, the magnetization direction of the magnetic pinned layer constituting the first multilayer film is the same as the magnetization direction of the magnetic pinned layer constituting the second multilayer film in the spin transistor according to the fourth embodiment. It is characterized by being. In particular, a reflux magnetic domain is generated in the second conductive layer 14 by spin injection. FIG. 17A is a schematic cross-sectional view of the spin transistor according to the sixth embodiment. FIG. 17-2 is a plan view of the spin transistor shown in FIG. 17-1.

  In the spin transistor 160, a nonmagnetic layer 161a and a magnetic pinned layer 162a are stacked in that order as a first multilayer film on the surface of the second conductive layer 14, and a magnetic pinned magnetic layer and the nonmagnetic layer 161b are stacked as a second multilayer film. The layer 162b is stacked in that order. An electrode 163a is formed on the magnetic pinned layer 162a, and an electrode 163b is formed on the magnetic pinned layer 162b. The spin transistor 160 has the same structure as the spin transistor 130 shown in FIG. 11A and is formed of the same material except that the magnetization directions of the magnetic pinned layers 162a and 162b are the same.

  In the following, the control of the magnetization direction by spin injection in the spin transistor 160, particularly the generation of the reflux magnetic domain will be described. Here, as shown in FIG. 11A, the magnetization directions of the magnetic pinned layers 162 a and 162 b are assumed to be “parallel” to the magnetization direction of the first conductive layer 12.

  First, it is assumed that the magnetization direction of the second conductive layer 14 is recorded “antiparallel” with respect to the magnetization direction of the first conductive layer 12. Precisely, a return magnetic domain is generated in the second conductive layer 14, and a magnetic domain located on the channel side of the return magnetic domain, in other words, a magnetic domain located immediately below the nonmagnetic layer 161a (hereinafter referred to as a proximal magnetic domain). )) Is “antiparallel”, and the magnetization direction of a magnetic domain (hereinafter referred to as a distal magnetic domain) located immediately below the nonmagnetic layer 161b is assumed to be “parallel”. FIG. 18A is a diagram illustrating the reflux magnetic domain in this state. As described above, when the reflux magnetic domain is generated in the second conductive layer 14, the second conductive layer 14 has two recording states of “anti-parallel” and “parallel” with respect to the first conductive layer 12. become. However, the ease of flow of the drain current is substantially determined by the magnetization direction of the first conductive layer 12 and the magnetization direction of the proximal magnetic domain of the second conductive layer 14. For this reason, the recording state of the second conductive layer 14 can be expressed by the magnetization direction of the proximal magnetic domain.

  From the state shown in FIG. 18A, the magnetization direction of the proximal magnetic domain is reversed to “parallel” by spin injection, and the magnetization direction of the distal magnetic domain is reversed to “antiparallel”. This magnetization reversal is performed by passing a current in a direction from the electrode 163b toward the electrode 163a. In terms of electron movement, parallel spins in the magnetic pinned layer 162a are injected into the second conductive layer 14 through the nonmagnetic layer 161a. The antiparallel spin in the proximal magnetic domain receives the torque of the injected parallel spin, reverses its direction, and becomes a parallel spin. The injected parallel spin passes through the proximal magnetic domain and the distal magnetic domain and reaches the magnetic pinned layer 162b. Since the magnetization direction of the magnetic pinned layer 162b is “parallel”, the parallel spin is not reflected and easily flows to the electrode 163b. On the other hand, application of a voltage between the electrodes 163a and 163b moves not only parallel spins but also antiparallel spins in the second conductive layer 14 to the magnetic pinned layer 162b. The antiparallel spin that has reached the magnetic pinned layer 162b is reflected there because the magnetization direction of the magnetic pinned layer 162b is "parallel". The reflected antiparallel spins further torque the parallel spins in the distal domain and reverse their orientation to “antiparallel”. Thereby, the magnetization direction of the proximal magnetic domain can be reversed to “parallel”, and the magnetization direction of the distal magnetic domain can be reversed to “antiparallel”. FIG. 18-2 is a diagram illustrating the reflux magnetic domain after the magnetization reversal. As can be seen by comparing FIG. 18-1 and FIG. 18-2, the magnetization direction of the return magnetic domain is reversed from clockwise to counterclockwise by spin injection from the magnetic pinned layer 162a to the second conductive layer. be able to.

  Next, it is assumed that the magnetization direction of the second conductive layer 14 is recorded “parallel” to the magnetization direction of the first conductive layer 12. To be exact, this is the state shown in FIG. This magnetization reversal is performed by passing a current in a direction from the electrode 163a toward the electrode 163b. In terms of electron movement, parallel spins in the magnetic pinned layer 162b are injected into the second conductive layer 14 through the nonmagnetic layer 161b. This magnetization reversal is the same as the above-mentioned “antiparallel” → “parallel” operation except that the spin direction is different.

  Further, the magnetization direction control structure shown in FIGS. 18A and 18B can also be applied to the surface stacked MOS structure described above, as shown in FIG. In the spin transistor 1160 shown in FIG. 19, the first conductive layer 12 and the second conductive layer 14 are formed on the tunnel barrier films 11 a and 11 b formed on the surface of the semiconductor substrate 1110, respectively. The first multilayer film (nonmagnetic layer 161a and magnetic layer 162a) and the second multilayer film (nonmagnetic layer 161b and magnetic pinned layer 162b) shown in FIGS. 17-1 and 17-2 are formed.

  As described above, according to the spin transistors 160 and 1160 according to the sixth embodiment, by generating a return magnetic domain by spin injection in the second conductive layer 14 and controlling the magnetization direction of the return magnetic domain, The recording state of the second conductive layer 14 can be controlled. In particular, the reflux magnetic domain has an advantage that it is thermally stable and can solve the problem of spin inversion due to thermal fluctuation when the size of the second conductive layer 14 formed of a magnetic material is reduced.

  In the spin transistors according to FIGS. 13-1, 14 and the fifth embodiment as well, the above-described reflux magnetic domains can be obtained by fixing the magnetization directions of the magnetic layers juxtaposed on the second conductive layer 14 in parallel to each other. Generation and magnetization reversal can also be realized.

(Embodiment 7)
A programmable logic circuit can be configured using the spin transistors according to the first to sixth embodiments described above. FIG. 20 is a schematic cross-sectional view of a spin transistor included in the programmable logic circuit according to the seventh embodiment. The spin transistor 170 shown in FIG. 20 is different from FIG. 1 in that a gate electrode 41 and a floating gate 31 are provided in place of the gate electrode 40 and the gate insulating film 30. Note that the magnetization direction of the second conductive layer 14 can be controlled by the current magnetic field shown in the second and third embodiments and the spin injection shown in the fourth to sixth embodiments. The illustration of the structure is omitted.

  FIG. 21 is an example of a programmable logic circuit configured using the spin transistor of FIG. The programmable logic circuit shown in FIG. 21 includes an N-type spin transistor MT1 and a P-type spin transistor MT2 each having the structure shown in FIG. 20, and these spin transistors share a floating gate FG. That is, the floating gate 31 shown in FIG. 20 is electrically connected to the floating gates of other adjacent spin transistors. Further, the drain (or source) of the spin transistor MT1 and the source (or drain) of the spin transistor MT2 are connected, the source (or drain) of the spin transistor MT1 is connected to the power supply voltage, and the drain (or source) of the spin transistor MT2 is connected. ) Is grounded. In this programmable logic circuit, the gates of the spin transistors MT1 and MT2 are connected to the input terminal, and the drain of the spin transistor MT1 (that is, the source of the spin transistor MT2) is connected to the output terminal.

FIG. 22 is a layout example of the programmable logic circuit shown in FIG. In FIG. 22, an N-type diffusion region 1012a corresponds to the first conductive layer 12, and is made of a diluted magnetic semiconductor material such as SiMn or GeMn in which an N-type impurity is diffused. N-type diffusion region 1012a is connected to power supply line V _DD via a via hole and a metal wiring layer. The N-type diffusion region 1014a corresponds to the second conductive layer 14, and is made of a semiconductor ferromagnetic material in which N-type impurities are diffused. N-type diffusion region 1014a is connected to output terminal Y through a via hole and a metal wiring layer. The P-type diffusion region 1012b corresponds to the first conductive layer 12, and is made of a diluted magnetic semiconductor material such as SiMn or GeMn in which P-type impurities are diffused. P type diffusion region 1012b is connected to ground line GND through a via hole and a metal wiring layer. The P-type diffusion region 1014b corresponds to the second conductive layer 14, and is made of a semiconductor ferromagnetic material in which P-type impurities are diffused. P-type diffusion region 1014b is connected to output terminal Y through a via hole and a metal wiring layer. The gate electrodes 1041a and 1041b correspond to the gate electrode 41, are made of polysilicon, for example, and are connected to the input terminals A and B through via holes and metal wiring layers, respectively.

FIG. 23 is a graph showing the output characteristics of the programmable logic circuit shown in FIG. 21, and shows the relationship between the logic level V _fg given to the floating gate FG and the logic output Y. If the logic input of the spin transistor MT1 is A and the logic input of the spin transistor MT2 is B, the relationship V _fg = (A + B) / 2 is satisfied. In FIG. 23, the solid line indicates output characteristics when the magnetization directions of the second conductive layers 14 of the spin transistors MT1 and MT2 are both “parallel”, and the broken line indicates the magnetization of the second conductive layer 14 of the spin transistor MT1. The output characteristics when the direction is “parallel” and the magnetization direction of the second conductive layer 14 of the spin transistor MT2 is “anti-parallel” are shown. As shown in FIG. 23, the logic output Y of this programmable logic circuit exhibits different characteristics depending on the magnetization direction of each second conductive layer 14 of the spin transistors MT1 and MT2. Specifically, when the logic level V _fg of the floating gate FG is ½, in other words, when only one of the logic inputs A and B indicates the logic level “1”, The logic output Y indicates “0”, but in the “anti-parallel” state, the logic output Y indicates “1”. Using this characteristic, the programmable logic circuit shown in FIG. 21 can realize an AND circuit and an OR circuit according to the recording state of the spin transistors MT1 and MT2.

  FIG. 24-1 shows that the magnetization direction of each of the second conductive layers 14 of the spin transistors MT1 and MT2, that is, the direction of spin is “parallel to the magnetization direction of the first conductive layer 12 in the programmable logic circuit shown in FIG. Is an input / output relationship table. As can be seen from this input / output relationship table, the relationship of the output Y to the inputs A and B matches the truth table of the AND logic operation. This is because the programmable logic circuit shown in FIG. 21 functions as an AND circuit. Means that

  FIG. 24-2 shows the programmable logic circuit shown in FIG. 21 in which the magnetization direction of the second conductive layer 14 of the spin transistor MT1, that is, the direction of spin is “parallel” to the magnetization direction of the first conductive layer 12, In addition, this is an input / output relationship table when the magnetization direction of the second conductive layer 14 of the spin transistor MT2 is “antiparallel” to the magnetization direction of the first conductive layer 12. Particularly in this case, the spin transistor MT2 is in a high impedance state. As can be seen from this input / output relationship table, the relationship of the output Y to the inputs A and B matches the truth table of the OR logic operation. This is because the programmable logic circuit shown in FIG. 21 functions as an OR circuit. Means that

  In the programmable logic circuit shown in FIG. 21, the source (or drain) of the spin transistor MT1 is grounded, the drain (or source) of the spin transistor MT2 is connected to the power supply voltage, and the spin transistors MT1 and MT2 Even in the case of a circuit configuration in which an inverter is connected to the connection point, as described above, it can function as an AND circuit or an OR circuit. FIG. 25 shows a programmable logic circuit in this case. As shown in FIG. 25, the drain (or source) of the P-type spin transistor MT2 that inputs the input B to the gate is connected to the power supply voltage, and the source (or the N-type spin transistor MT1 that inputs the input A to the gate). The drain) is grounded. Both the source (or drain) of the spin transistor MT2 and the drain (or source) of the spin transistor MT1 are connected to the input terminal of the inverter INV. A logic output Y ′ is obtained from the output terminal of the inverter INV.

  FIG. 26A shows the magnetization direction of the second conductive layer 14 of the spin transistor MT1, that is, the direction of spin is “anti-parallel” to the magnetization direction of the first conductive layer 12 in the programmable logic circuit shown in FIG. And an input / output relationship table when the magnetization direction of the second conductive layer 14 of the spin transistor MT2 is “parallel” to the magnetization direction of the first conductive layer 12. FIG. Particularly in this case, the spin transistor MT1 is in a high impedance state. As can be seen from this input / output relationship table, the relationship of the output Y ′ with respect to the inputs B and A matches the truth table of the AND logic operation. This is because the programmable logic circuit shown in FIG. Means that it is functioning.

  FIG. 26B shows the magnetization direction of each of the second conductive layers 14 of the spin transistors MT1 and MT2, that is, the spin direction is “parallel to the magnetization direction of the first conductive layer 12 in the programmable logic circuit shown in FIG. Is an input / output relationship table. As can be seen from this input / output relationship table, the relationship of the output Y ′ with respect to the inputs B and A coincides with the truth table of the OR logic operation. This is because the programmable logic circuit shown in FIG. Means that it is functioning.

  From the above, the programmable logic circuit shown in FIG. 21 or FIG. 25 can realize either the AND circuit or the OR circuit by controlling the magnetization direction of the second conductive layer 14. Since the AND circuit and the OR circuit are basic circuits, any logic circuit including a NAND circuit, a NOR circuit, and an EX-OR circuit can be constructed by combining these circuits.

  In the programmable logic circuit in the above-described embodiment, the connection relationship between the two spin transistors has been described using the terms “source” and “drain”. However, as described in the first embodiment, the first conductive layer 12 (that is, magnetic The pinned layer) and the second conductive layer 14 (that is, the magnetic recording layer) can function as both a source and a drain. Therefore, the magnetic pinned layers may be connected between the two spin transistors, or the magnetic recording layers may be connected to each other. May be connected, and the magnetic pinned layer and the magnetic recording layer may be connected. It is possible to provide a programmable logic circuit having excellent characteristics with such a simple connection configuration.

  Note that one of the spin transistors MT1 and MT2 shown in FIG. 21 or FIG. 25 may be replaced with a normal MOS transistor. For example, even if the spin transistor MT1 of FIG. 21 is constructed of a normal NMOS transistor having a floating gate, the same result as the truth table shown in FIGS. 24-1 and 24-2 can be obtained.

  As described above, according to the programmable logic circuit of the seventh embodiment, it is possible to construct a logic circuit that switches to either the AND circuit or the OR circuit depending on the magnetization direction of the second conductive layer 14. it can. In particular, since the spin transistor constituting this programmable logic circuit has a switching function and a nonvolatile memory function, a conventional programmable logic circuit (that is, a logic in which the switching unit and the memory function unit are configured as separate elements). The problem of complicated wiring between elements in the circuit) is also solved.

(Embodiment 8)
The manufacturing process of the spin transistor according to the first embodiment (equivalent to the spin transistor shown in FIG. 1) will be described below as the eighth embodiment. FIGS. 27-1 to 27-3 are cross-sectional views showing the manufacturing process of the spin transistor. First, field oxide films 183a and 183b for defining an element region are formed on a silicon substrate 181, and the first conductive layer embedded region 191a and the second conductive layer are formed by a known lithography process, etching process, and film forming process. A layer buried region 191b, a gate insulating film 186, and a gate electrode 187 are formed (FIG. 27-1). The gate insulating film 186 and the gate electrode 187 are formed using the materials described in Embodiment 1.

  Next, field oxide films 183a and 183b, first conductive layer buried region 191a, second conductive layer buried region 191b, gate insulating film 186, and tunnel barrier film 185a are exposed on the exposed surfaces of gate electrode 187 by sputtering and plasma oxidation processes. , 185b (FIG. 27-2). Note that part of the surface of the gate electrode 187 is exposed for connection to the wiring. These tunnel barrier films 185a and 185b are also formed using the materials described in the first embodiment. Then, the first conductive layer 182 and the second conductive layer 184 were stacked in the first conductive layer embedded region 191a and the second conductive layer embedded region 191b, respectively, by sputtering (FIG. 27-3). For this sputtering, for example, a strongly directional sputtering apparatus is used. The first conductive layer 182 and the second conductive layer 184 can be formed using different materials by using different resist masks. Thus, the spin transistor 180 in which the tunnel barrier films 185a and 185b are formed between the first conductive layer 182 and the second conductive layer 184 and the channel region of the silicon substrate 181 can be obtained.

  As described above, according to the manufacturing method according to the eighth embodiment, the spin transistor according to the first embodiment can be easily formed using a known semiconductor manufacturing technique.

(Embodiment 9)
The spin injection structure of the spin transistor according to the fourth to sixth embodiments is useful as a structure that bears the memory function of a magnetic memory such as an MRAM. Here, a magnetic memory using a spin injection structure of a spin transistor according to the sixth embodiment, that is, a structure that enables storage retention and switching of a storage state by generating a reflux magnetic domain will be described. FIG. 28 is a schematic sectional view of the magnetic memory according to the ninth embodiment.

  In the magnetic memory 200 shown in FIG. 28, the antiferromagnetic layer 285, the magnetic pinned layer 286, the tunnel barrier layer 287, the magnetic recording layer 214, the nonmagnetic layer 261a, the nonmagnetic layer 261b, the magnetic pinned layer 262a, the magnetic pinned layer 262b, The electrode 263a and the electrode 263b are, in order of materials and functions, in order from the antiferromagnetic layer 16, the first conductive layer 12, the tunnel barrier film 11a (and 11b), and the second conductive layer 14 shown in FIG. These correspond to the nonmagnetic layer 161a, the nonmagnetic layer 161b, the magnetic pinned layer 162a, the magnetic pinned layer 162b, the electrode 163a, and the electrode 163b. In particular, on the surface of the magnetic recording layer 214, a nonmagnetic layer 261a and a magnetic pinned layer 262a are stacked in this order as a first multilayer film, and a nonmagnetic layer 261b and a magnetic pinned layer 262b are formed as a second multilayer film. It is the same as FIG. In FIG. 28, the portion corresponding to the channel region of FIG. 17A is the lower magnetic recording layer 288, which is formed of the same material as the magnetic recording layer 214. In the magnetic memory 200, since it is not necessary to form a channel, the lower magnetic recording layer 288 simply functions as an electron spin injection window. However, this injection window needs to be arranged only directly under the magnetic domain corresponding to the proximal magnetic domain described in the sixth embodiment among the return magnetic domains formed in the magnetic recording layer 214. This is because the recording state of the magnetic memory depends on the magnetization direction of the proximal magnetic domain among the generated return magnetic domains. The lower magnetic recording layer 288 may be omitted.

  The stacked structure described above is formed on the base electrode layer 296. Specifically, as shown in FIG. 28, a conductive layer 284 is further formed on the surface of the base electrode layer 296, and an antiferromagnetic layer 285, a magnetic pinned layer 286, and a tunnel barrier layer 287 are formed on the conductive layer 284. The lower magnetic recording layer 288 is laminated in that order, and a spin injection structure having the magnetic recording layer 214 as a main part is formed on the lower magnetic recording layer 288. An electrode lead layer 264a is formed on the electrode 263a, and a bit line 270 is further formed on the electrode lead layer 264a. The memory function unit of the magnetic memory 200 is realized by a configuration sandwiched between the bit line 270 and the base electrode layer 296.

  A selection transistor for reading the memory state of the memory function portion is formed below the base electrode layer 296, and the source electrode extraction layer 294 and the base electrode layer 296 of the selection transistor are electrically connected. The selection transistor includes a semiconductor substrate 290, a source region 292 and a drain region 293 formed in the semiconductor substrate 290, and a gate electrode 291. A source electrode extraction layer 294 is formed on the source region 292, and a drain electrode extraction layer 295 is formed on the drain region 293. Note that a region other than the stacked structure described above between the bit line 270 and the semiconductor substrate 290 is filled with an insulating material.

  In other words, the magnetic memory 200 has a structure in which a portion corresponding to a TMR element in a known MRAM cell is replaced with the memory function unit described above. That is, a memory cell array can be constructed by forming a plurality of magnetic memories 200 in an array.

Note that a TMR element constituting an MRAM may be used in place of the magnetic recording layer 214, the lower magnetic recording layer 288, the tunnel barrier layer 287, and the magnetic pinned layer 286. In other words, a circulating magnetic domain is generated in the TMR element. Specifically, an insulating layer (or dielectric layer) is used instead of the tunnel barrier layer 287. This as an insulating layer, for example, can be used _{Al 2 O 3, SiO 2,} MgO, AlN, Bi 2 O 3, MgF 2, CaF 2, SrTiO 2, AlLaO 3, the AlNO. These compounds do not need to have a completely accurate composition in terms of stoichiometry, and may be deficient or excessive or deficient in oxygen, nitrogen, fluorine, or the like. The thickness of the insulating layer (or dielectric layer) is desirably thin enough to allow a tunnel current to flow, and is preferably 10 nm or less.

  FIG. 29A and FIG. 29B are diagrams illustrating the reflux magnetic domain formed on the magnetic recording layer 214. Similar to the magnetization control by spin injection described in the sixth embodiment, also on the magnetic recording layer 214 constituting the magnetic memory 200, the magnetization direction of the reflux magnetic domain can be controlled by spin injection (dotted line shown in FIG. 28). . This spin injection is performed by passing a current between the electrodes 263a and 263b. Further, the recording state of the magnetic memory 200 can be detected by the amount of current (a chain line shown in FIG. 28) flowing between the bit line 270 and the drain electrode extraction layer 295, as in the MRAM.

  In FIG. 28, the width of the layer structure between the base electrode layer 296 and the magnetic recording layer 214, that is, the conductive layer 284, the antiferromagnetic layer 285, the magnetic pinned layer 286, the tunnel barrier layer 287, and the lower magnetic recording layer 288. Each width is smaller than the width of the magnetic recording layer 214, but may be the same as the width of the magnetic recording layer 214 as shown in FIG. In the magnetic memory 300 shown in FIG. 30, a conductive layer 384, an antiferromagnetic layer 385, a magnetic pinned layer 386, and a tunnel barrier layer 387 are formed in this order on the base electrode layer 396, and their width is the width of the magnetic recording layer 214. Matches.

  Further, in the structure shown in FIG. 30, a spin reflection layer may be provided between the magnetic recording layer 214 and the tunnel barrier layer 387. In the magnetic memory 400 shown in FIG. 31, the base electrode layer 496, the conductive layer 484, the antiferromagnetic layer 485, the magnetic pinned layer 486, and the tunnel barrier layer 487 are the base electrode layer 396, the conductive layer 384, and the anti-layer shown in FIG. This corresponds to the ferromagnetic layer 385, the magnetic pinned layer 386, and the tunnel barrier layer 387. In the magnetic memory 400, a spin reflection layer 490 is further formed between the magnetic recording layer 214 and the tunnel barrier layer 487. The spin reflection layer 490 is a multilayer film in which a magnetic layer 491 and a nonmagnetic layer 492 are stacked in that order.

  As the spin reflection layer 490, the following combinations of materials can be used. That is, when the material of the magnetoresistive effect element or the magnetic recording layer (free layer) 214 of the magnetic memory is a ferromagnetic material (metal, alloy, compound, etc.) containing Co, the nonmagnetic layer 492 in contact with the magnetic recording layer 214. As the material, it is preferable to use a metal or alloy containing at least one element selected from Cr, Ru, Ir, Os, and Re. When the magnetic recording layer 214 is made of a ferromagnetic material containing Fe (metal, alloy, compound, etc.), the material of the nonmagnetic layer 492 in contact with the magnetic recording layer 214 is Cr, Ru, Os, Re, It is preferable to use a metal or alloy containing at least one element selected from W, Mn, V, Ti, and Mo. Further, when the material of the magnetic recording layer 214 is a ferromagnetic material containing Ni (metal, alloy, compound, etc.), as the material of the nonmagnetic layer 492 in contact with the magnetic recording layer 214, Cr, Ru, Os, Re, It is preferable to use a metal or alloy containing at least one element selected from Rh, Ir, W, Nb, V, Ta, and Mo. Here, when the material of the magnetic recording layer 214 is an alloy such as Ni—Co, Ni—Fe, Co—Fe, and Co—Fe—Ni, it is common among nonmagnetic materials suitable for Co, Fe, and Ni. It is preferable to use a nonmagnetic material. In each case, the material of the magnetic layer 491 can be the same material as the magnetic recording layer 214, but is not limited thereto. The spin reflection layer 490 can further reduce the spin injection current, and at the time of spin injection, on the current path composed of the magnetic pinned layer 262a, the nonmagnetic layer 261a, the magnetic recording layer 214, the nonmagnetic layer 261b, and the magnetic pinned layer 262b. The flowing current can be increased, and further, damage to the tunnel barrier layer 487 can be reduced.

  FIG. 32 is a further modification of the magnetic memory shown in FIG. In the magnetic memory 500 shown in FIG. 32, the conductive layer 584, the antiferromagnetic layer 585, the magnetic pinned layer 586, the tunnel barrier layer 588, the magnetic recording layer 514, the nonmagnetic layer 561a, the nonmagnetic layer 561b, the magnetic pinned layer 562a, the magnetic layer The pinned layer 562b, the electrode 563a, the electrode 563b, and the electrode lead layer 564a are sequentially formed of the conductive layer 284, the antiferromagnetic layer 285, the magnetic pinned layer 286, the tunnel barrier layer 287, the magnetic recording layer 214, This corresponds to the magnetic layer 261a, the nonmagnetic layer 261b, the magnetic pinned layer 262a, the magnetic pinned layer 262b, the electrode 263a, the electrode 263b, and the electrode lead layer 264a.

  32 differs from FIG. 28 in that an insulating layer 587 is formed between the tunnel barrier layer 588 and the magnetic pinned layer 586, and that the bottom surface of the conductive layer 584 and a part of the bottom surface of the tunnel barrier layer 588 are formed. Is that several layers constituting the memory function part have an inclination so that they are located on the same plane. Specifically, a part of the conductive layer 584 is tapered, and an antiferromagnetic layer 585, a magnetic pinned layer 586, an insulating layer 587, a tunnel barrier layer 588, and a magnetic recording layer 514 are stacked over the conductive layer 584. As a result, these layers also have a slope. As shown in FIG. 32, the nonmagnetic layer 561a and the magnetic pinned layer 562a are formed on a flat surface and an inclined surface on the magnetic recording layer 514. Thus, by creating a tunnel barrier at the edge portion, the effective junction area can be controlled by the film thickness of the antiferromagnetic layer 585 and the magnetic pinned layer 586, and variations in the junction area can be suppressed. 31 can also be provided between the magnetic recording layer 514 and the tunnel barrier layer 588 in FIG. 32, so that current during spin injection writing can be reduced.

  The structure of the magnetic memory shown in FIGS. 28 and 30 to 32 can be easily formed by using a well-known semiconductor manufacturing process, similarly to the process of forming the conventional MRAM.

  28 and 30 to 32 exemplify the spin injection control structure in which the magnetic layers are in a “parallel” relationship like the spin transistor shown in FIG. 17A. As shown in FIGS. 12, 13-1, 14, 15-1, and 16, the spin injection control structure in which the magnetic layers are in an “anti-parallel” relationship may be used.

  As described above, the magnetic memory according to the ninth embodiment has a structure in which the portion corresponding to the TMR element of the MRAM is replaced with the spin injection structure of the spin transistor according to the fourth to sixth embodiments. Therefore, a magnetic memory in which the magnetization direction is controlled by spin injection can be provided. Moreover, this magnetic memory can enjoy the effect demonstrated in Embodiment 4-6.

  The present invention is not limited to the specific embodiments as described above, and further effects and modifications can be easily derived by those skilled in the art. That is, the embodiment according to the present invention can be variously modified without departing from the gist of the invention according to the appended claims and equivalents thereof.

  As described above, the spin transistor according to the present invention is useful as a switching element having an amplification function and a memory function, and is particularly suitable for use as a unit element of a programmable logic circuit. The magnetic memory according to the present invention is suitable for use as a nonvolatile memory.

1 is a schematic cross-sectional view of a spin transistor according to a first exemplary embodiment. FIG. 6 is a schematic cross-sectional view of a spin transistor when the magnetization direction of a second conductive layer is in a “parallel” state. It is an energy band figure of a spin transistor in case the magnetization direction of a 2nd conductive layer is a "parallel" state. FIG. 6 is a schematic cross-sectional view of a spin transistor when the magnetization direction of a second conductive layer is in an “antiparallel” state. It is an energy band figure of a spin transistor in case the magnetization direction of a 2nd conductive layer is an "anti-parallel" state. FIG. 6 is a schematic cross-sectional view of another example of the spin transistor according to the first exemplary embodiment. FIG. 6 is a schematic cross-sectional view of still another example of the spin transistor according to the first exemplary embodiment. FIG. 6 is a schematic cross-sectional view of still another example of the spin transistor according to the first exemplary embodiment. FIG. 6 is a schematic cross-sectional view of a spin transistor according to a second exemplary embodiment. FIG. 6 is a schematic cross-sectional view of a spin transistor according to a third exemplary embodiment. It is the XX sectional view taken on the line of FIG. 14 is a graph showing drain current characteristics of the spin transistor according to the third exemplary embodiment. 12 is a graph showing drain current characteristics of another example of the spin transistor according to the third exemplary embodiment; FIG. 5 is a schematic cross-sectional view of a spin transistor according to a fourth exemplary embodiment. It is a top view of a spin transistor shown in Drawing 11-1. FIG. 10 is a schematic cross-sectional view of another example of the spin transistor according to the fourth exemplary embodiment. FIG. 5 is a schematic cross-sectional view of a spin transistor according to a fourth exemplary embodiment. It is a top view of a spin transistor shown in Drawing 11-1. FIG. 10 is a schematic cross-sectional view of another example of the spin transistor according to the fourth exemplary embodiment. FIG. 10 is a schematic cross-sectional view of a spin transistor according to a fifth embodiment. FIG. 15B is a plan view of the spin transistor shown in FIG. 15-1. It is XI-XI sectional view taken on the line of the spin transistor shown to FIGS. 15-2. FIG. 10 is a schematic cross-sectional view of another example of the spin transistor according to the fifth exemplary embodiment. FIG. 10 is a schematic cross-sectional view of a spin transistor according to a sixth embodiment. It is a top view of the spin transistor shown in FIG. It is a figure which shows the return magnetic domain of the 2nd conductive layer whose magnetization direction is an "antiparallel" state. It is a figure which shows the return magnetic domain of the 2nd conductive layer whose magnetization direction is a "parallel" state. FIG. 20 is a schematic cross-sectional view of another example of the spin transistor according to the sixth exemplary embodiment. FIG. 10 is a schematic cross-sectional view of a spin transistor constituting a programmable logic circuit according to a seventh embodiment. It is a figure which shows an example of the programmable logic circuit comprised using the spin transistor shown in FIG. FIG. 22 is a diagram showing a layout example of the programmable logic circuit shown in FIG. 21. It is a graph which shows the output characteristic of the programmable logic circuit shown in FIG. FIG. 22 is a truth table in the “parallel” state of the programmable logic circuit shown in FIG. 21. FIG. 22 is a truth table in the “antiparallel” state of the programmable logic circuit shown in FIG. 21. It is a figure which shows the other example of the programmable logic circuit comprised using the spin transistor shown in FIG. 26 is a truth table in the “antiparallel” state of the programmable logic circuit shown in FIG. 25. 26 is a truth table in the “parallel” state of the programmable logic circuit shown in FIG. 25. FIG. 16 is a cross-sectional view showing a step of forming a first conductive layer buried region and a second conductive layer buried region in a manufacturing process of a spin transistor according to an eighth embodiment. FIG. 10 is a cross-sectional view showing a step of forming a tunnel barrier film among the steps of manufacturing a spin transistor according to the eighth embodiment. FIG. 16 is a cross-sectional view showing a step of forming a first conductive layer and a second conductive layer in a manufacturing process of a spin transistor according to an eighth embodiment. FIG. 10 is a schematic cross-sectional view of a magnetic memory according to a ninth embodiment. It is a figure which shows the return magnetic domain formed on a magnetic-recording layer. It is a figure which shows the reflux magnetic domain of the other state formed on a magnetic recording layer. It is a figure which shows the modification of the magnetic memory shown in FIG. FIG. 31 is a diagram showing a modification of the magnetic memory shown in FIG. 30. It is a figure which shows the other modification of the magnetic memory shown in FIG.

Explanation of symbols

10, 290, 1110 Semiconductor substrate 11a, 11b, 185a, 185b Tunnel barrier film 12, 182 First conductive layer 14, 184 Second conductive layer 16, 285, 385, 485, 585 Antiferromagnetic layer 30, 186 Gate insulating film 31 Floating gate 40, 41, 187, 291 Gate electrode 42a, 42b Insulating film 50 Silicon oxide layer 60 Insulating layer 100, 110, 120, 130, 140, 150, 160, 170, 180, 1100, 1130, 1140, 1150, 1160 Spin transistors 111a, 121a First word lines 111b, 121b Second word lines 122a, 122b Magnetic coating layers 131a, 131b, 141a, 151a, 152b, 153a, 161a, 161b, 261a, 261b, 492, 561a 561b Nonmagnetic layer 132a, 132b, 142a, 142b, 162a, 162b, 286, 262a, 262b, 386, 486, 562a, 562b, 586 Magnetic pinned layers 20a, 20b, 133a, 133b, 143a, 143b, 154b, 155a, 163a, 163b, 263a, 263b, 563a, 563b Electrode 152a, 153b, 154a, 491 Magnetic layer 183a, 183b Field oxide film 181 Silicon substrate 191a First conductive layer embedded region 191b Second conductive layer embedded region 200, 300 Magnetic memory 214 , 514 Magnetic recording layer 264a, 564a Electrode extraction layer 270 Bit line 284, 384, 484, 584 Conductive layer 287, 387, 487, 588 Tunnel barrier layer 288 Lower magnetic recording layer 29 Source region 293 drain region 294 source electrode lead layer 295 drain electrode lead layer 296,396,496 underlying electrode layer 490 spin reflection layer 1012a, 1014a N-type diffusion region 1012b, 1014b P-type diffusion region

Claims (11)

A semiconductor substrate;
A first conductive layer formed of a ferromagnetic material magnetized in a first direction on the semiconductor substrate and functioning as either a source or a drain;
Formed on the semiconductor substrate with a ferromagnetic material magnetized in one of the first direction and a second direction antiparallel to the first direction, and functions as either the source or the drain A second conductive layer;
A channel portion formed in a portion located between the first conductive layer and the second conductive layer in the semiconductor substrate and guiding electron spin between the first conductive layer and the second conductive layer;
An insulating film located above the channel portion ;
A gate electrode located above the insulating film ;
A tunnel barrier film located between at least one of the first conductive layer and the second conductive layer and the channel portion;
A spin transistor comprising:   The spin transistor according to claim 1, wherein a voltage for controlling an energy level of the channel portion is applied to the gate electrode.   The spin transistor according to claim 1, further comprising an antiferromagnetic layer in contact with the first conductive layer. A first word line and a second word line sandwiching the second conductive layer and substantially orthogonal to each other;
The magnetization direction of the second conductive layer is controlled according to a direction of a synthetic magnetic field generated by a current flowing through the first word line and the second word line. The spin transistor according to one.   5. The spin transistor according to claim 4, wherein the first word line is formed in an SOI (Silicon On Insulator) substrate.   6. The spin transistor according to claim 4, wherein at least one of the first word line and the second word line is covered with a magnetic coating layer.   The semiconductor substrate has a first recess, a second recess, and the channel portion positioned between the first recess and the second recess,
  The first conductive layer is formed in the first recess;
  The spin transistor according to claim 1, wherein the second conductive layer is formed in the second recess.   The semiconductor substrate has a first region, a second region, and the channel portion located between the first region and the second region,
  The first conductive layer is formed above the first region;
  The spin transistor according to claim 1, wherein the second conductive layer is formed above the second region.   The spin transistor according to claim 1, wherein the semiconductor substrate is a compound semiconductor.   The spin transistor according to claim 1, wherein the semiconductor substrate is a doped semiconductor. A semiconductor substrate;
  A first conductive layer formed of a ferromagnetic material magnetized in a first direction on the semiconductor substrate and functioning as either a source or a drain;
  Formed on the semiconductor substrate with a ferromagnetic material magnetized in one of the first direction and a second direction antiparallel to the first direction, and functions as either the source or the drain A second conductive layer;
  A channel portion formed in a portion located between the first conductive layer and the second conductive layer in the semiconductor substrate and guiding electron spin between the first conductive layer and the second conductive layer;
  A floating gate located above the channel portion;
  A gate electrode located above the floating gate;
  A tunnel barrier film located between at least one of the first conductive layer and the second conductive layer and the channel portion;
  A spin transistor comprising:

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