JP4744413B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device using silicide and a manufacturing method thereof.

  As semiconductor integrated circuit devices become highly integrated, miniaturization of transistors as constituent elements proceeds. With miniaturization, the gate length is shortened and the depth of the source / drain region is reduced. In order to reduce the resistance of the source / drain regions, self-aligned silicidation (salicide process) is performed. The silicide layer formed in the source / drain region must be formed shallower than the junction depth to prevent leakage current.

  As the gate length decreases, the height of the gate electrode also decreases. In order to reduce the gate resistance, full silicidation for siliciding the entire thickness of the gate electrode has been studied (Non-patent Document 1). Full silicidation is effective not only in reducing gate resistance but also in improving transistor characteristics because it can prevent the occurrence of a depletion layer. In order to perform full silicidation, the silicidation reaction needs to reach the entire thickness of the gate electrode.

  When the silicidation reaction proceeds sufficiently deep at the gate electrode, the silicide layer in the source / drain region also becomes deep. If the silicide layer in the source / drain region is close to or penetrates the junction, the leakage current increases. It is desirable to limit the depth of the silicide layer in the source / drain region.

In order to separate the bottom surface of the silicide layer from the junction, it has also been proposed to epitaxially grow a silicon layer on the source / drain region and raise the source / drain region surface before silicidation (Non-patent Document 2).
In order to further reduce the resistance of the gate electrode, there is a proposal to make the gate with a metal having a resistance lower than that of silicide. There is also a proposal of forming a replacement aluminum gate electrode by initially forming a disposable gate with a silicon layer and then replacing silicon with aluminum (Patent Document 3).

J. kedzierski et al., IEDM 2002 TechnicalDigest, p247 K. Rim et al., 2002 Symposium on VLSI Technology Digest of Technical Papers, in particular Fig. 3 JP-A-11-214327 JP 2001-352058 A JP 11-251595 A

  An object of the present invention is to provide a semiconductor device in which a gate of an nMOSFET and a gate of a pMOSFET are formed of different low resistance materials and a method for manufacturing the same.

  Another object of the present invention is to provide a semiconductor device capable of fully siliciding the gate of the pMOSFET and forming the gate of the nMOSFET with aluminum, and a method for manufacturing the same.

According to one aspect of the present invention,
forming a stack of a gate insulating layer, a polysilicon layer, and an insulating cap layer on a silicon substrate including a p-channel MOSFET region and an n-channel MOSFET region;
Patterning the insulating cap layer and leaving the patterned insulating cap layer in a gate electrode shape on the polysilicon layer in the n-channel MOSFET region;
A gate electrode-shaped resist pattern is formed on the polysilicon layer in the p-channel MOSFET region from which the insulating cap layer has been removed, and the polysilicon layer and gate are formed using the resist pattern and the patterned insulating cap layer as a mask. patterning the insulating layer, thereby forming a gate electrode on the p-channel and n-channel MOSFET region, a step of exposing the silicon substrate table surface on both sides,
Perform silicidation reaction from the exposed silicon substrate table surface and the polysilicon gate electrode surface of the p-channel MOSFET, to form a metal rich silicide regions in said silicon substrate surface, a polysilicon gate electrode of the p-channel MOSFET Forming a metal-rich silicide region by full silicidation; and
Forming an insulating layer covering the silicide region;
The insulating layer, a step of penetrating the insulating cap layer is formed the p-channel MOSFET of the gate electrode and the n-channel MOSFET comprising a silicide region the polysilicon gate electrode contact hole reaching the respective,
Filling each contact hole to form an aluminum layer;
Performing annealing and replacing the polysilicon gate electrode of the n-channel MOSFET with aluminum without replacing the gate electrode made of the metal-rich silicide region of the p-channel MOSFET with aluminum ; and
A method for manufacturing a semiconductor device is provided.

  The source / drain regions may be formed on the silicon substrate or may be formed by depositing a silicon layer on the silicon substrate.

According to another aspect of the invention,
forming a stack of a gate insulating layer, a polysilicon layer, and an insulating cap layer on a silicon substrate including a p-channel MOSFET region and an n-channel MOSFET region;
Patterning the insulating cap layer and leaving the patterned insulating cap layer in a gate electrode shape on the polysilicon layer in the n-channel MOSFET region;
A gate electrode-shaped resist pattern is formed on the polysilicon layer in the p-channel MOSFET region from which the cap layer has been removed, and the polysilicon layer and the gate insulation are formed using the resist pattern and the patterned insulating cap layer as a mask. a step of patterning the layer, to form a gate electrode on the p-channel and n-channel MOSFET region, exposing the silicon substrate table surface on both sides,
Growing a silicon layer embedding the gate electrode on the silicon substrate;
Chemically mechanical polishing the silicon layer, leaving a patterned insulating cap layer of the n-channel MOSFET, exposing a polysilicon gate electrode of the p-channel MOSFET;
A silicidation reaction is performed from the surface of the silicon layer and the exposed polysilicon gate electrode surface of the p-channel MOSFET to form a metal-rich silicide region on the silicon layer surface, and a polysilicon gate electrode of the p-channel MOSFET is formed. Forming a metal-rich silicide region by full silicidation; and
Forming an insulating layer covering the silicide region;
The insulating layer, a step of penetrating the insulating cap layer is formed the p-channel MOSFET of the gate electrode and the n-channel MOSFET comprising a silicide region the polysilicon gate electrode contact hole reaching the respective,
Filling each contact hole to form an aluminum layer;
Performing annealing and replacing the polysilicon gate electrode of the n-channel MOSFET with aluminum without replacing the gate electrode made of the metal-rich silicide region of the p-channel MOSFET with aluminum ; and
A method for manufacturing a semiconductor device is provided.

  The exposed silicon may be a silicon substrate or a silicon layer selectively formed thereon.

  The gate electrode of pMOSFET can be formed by silicidation reaction, and the gate electrode of nMOSFET can be formed by Al substitution reaction.

  First, preliminary experiments and results will be described.

  As shown in FIG. 1A, a nickel layer 22 having a thickness of 10 nm was formed on the surface of the silicon substrate 1 by sputtering.

As shown in FIG. 1B, using a rapid thermal annealing (RTA) apparatus, the sample shown in FIG. 1A was annealed at 750 ° C. for 1 minute to cause a silicidation reaction. A NiSi ₂ layer 23 was formed. The thickness of the NiSi ₂ layer 23 was 17 nm.

As shown in FIG. 1C, a nickel layer 24 having a thickness of 50 nm was formed on the NiS ₂ layer 23 by sputtering. This sample is called ds.

As shown in FIG. 1D, a sample in which a nickel layer 24 having a thickness of 50 nm was formed on a silicon substrate 1 on which no NiSi ₂ layer was formed was also prepared. This sample is called ss.

  The sample ds and the sample ss were carried into an RTA apparatus, heated at 400 ° C., and how silicidation progressed with respect to the heating time was measured. NiSi is formed in the silicidation reaction between Ni and Si at 400 ° C.

  FIG. 1E is a graph showing the results of heat treatment at 400 ° C. The horizontal axis indicates the heating time in units of seconds, and the vertical axis indicates the depth of the nickel silicide layer in units of nm. In the sample ss in which the nickel layer 24 is formed directly on the silicon substrate 1, the nickel silicide layer becomes deeper with heating time and reaches 75 nm or more. This maximum depth is considered to be the thickness of the NiSi layer that consumed almost all of the deposited nickel.

On the other hand, in the sample ds in which the NiSi ₂ layer 23 is formed on the silicon substrate 1 and the nickel layer 24 is formed thereon, the nickel silicide layer has a depth of about 17 nm at first, and is heated at 400 ° C. In addition, the depth of the nickel silicide layer does not change at all within the measurement error. Even if the silicide layer formed at 750 ° C. is annealed at 400 ° C. with the nickel layer 24 separated from the silicon surface, a new silicide reaction is suppressed. In NiSi ₂ which is stable at 750 ° C., it is considered that Ni is not substantially diffused at a lower temperature of 400 ° C.

  That is, if a silicide layer that is thermodynamically stable at high temperature is formed, a metal capable of silicidation reaction is formed on the silicide layer, and the silicidation reaction is greatly suppressed even if heat treatment is performed at a lower temperature. Conceivable. In addition to Ni, W, Co, or the like may be used as a metal that can be silicided.

2A-2H show examples based on the experimental results shown in FIGS. 1A-1E .

  As shown in FIG. 2A, a silicon oxide layer having a thickness of 2 nm is formed on the surface of the silicon substrate 1 by thermal oxidation, and a gate insulating film 2 is formed. A polysilicon layer 25 having a thickness of 50 nm is formed on the gate insulating film 2 by thermal CVD. A 20 nm thick silicon oxide layer is formed on the polysilicon layer 25 to form an insulating cap layer 26. A resist pattern RP is formed on the insulating cap layer 26 by lithography. Using the resist pattern RP as a mask, the insulating cap layer 26 and the polysilicon layer 25 are subjected to plasma etching and patterned into a gate electrode shape. Thereafter, the resist pattern RP is removed, and the gate insulating film 2 around the gate electrode is removed with diluted HF.

  As shown in FIG. 2B, a p-type impurity, for example, B is ion-implanted using the patterned gate electrode as a mask to form an extension 27.

As shown in FIG. 2C, a silicon nitride film is formed by thermal CVD, and the entire surface is etched by plasma to leave the sidewalls 28 only on the side surfaces of the insulated gate structure. Source / drain regions 29 are formed by ion implantation of B using the insulated gate structure and sidewalls 28 as a mask. The ion implantation conditions are, for example, an acceleration energy of 6 keV and a dose amount of 6E15 (6 × 10 ¹⁵ ) cm ⁻² . Using an RTA apparatus, for example, annealing at 1000 ° C. for 1 second is performed to activate the implanted impurities.

  As shown in FIG. 2D, a nickel layer 30 having a thickness of 10 nm is formed by sputtering. The exposed surface of the source / drain region 29 is in contact with the nickel layer 30. Since the polysilicon layer 25 having the insulated gate structure is covered with the insulating cap layer 26, it does not come into contact with the nickel layer 30.

Using RTA, the structure shown in FIG. 2D is annealed at 750 ° C. for 1 minute to cause a silicidation reaction. A NiSi ₂ layer having a thickness of about 17 nm is formed in the source / drain region 29 in contact with the nickel layer 30. Since the polysilicon layer 25 having the insulated gate structure is not in contact with the nickel layer 30, the silicidation reaction does not occur. Thereafter, the unreacted nickel layer 30 is removed by wet etching.

FIG. 2E shows a state in which the unreacted nickel layer 30 has been removed. In the source / drain region 29, a NiSi ₂ layer 31 having a depth of about 17 nm is formed.

  As shown in FIG. 2F, the insulating cap layer 26 having an insulated gate structure is removed by wet etching using diluted HF. Note that the insulating cap layer 26 may be removed by plasma etching instead of wet etching.

  As shown in FIG. 2G, a nickel layer 32 having a thickness of 50 nm is formed on the substrate surface by sputtering with the surface of the polysilicon layer 25 having an insulated gate structure exposed.

An annealing is performed at 400 ° C. for 1 minute using an RTA apparatus to cause a silicidation reaction. The polysilicon layer 25 having the insulated gate structure is converted into NiSi by a silicidation reaction. The NiSi ₂ layer 31 is a thermodynamically stable layer, and no further silicidation reaction occurs at a temperature of 400 ° C. Full silicidation of the polysilicon layer 25 of the gate electrode is facilitated.

FIG. 2H shows a state in which the unreacted nickel layer 32 is removed by wet etching after the silicidation reaction. The gate electrode is formed by the NiSi layer 33. A NiSi ₂ layer 31 is formed in the source / drain region 29, and its depth is determined by a silicidation reaction at 750 ° C. and does not increase any further. By limiting the depth of the silicide region 31 and sufficiently separating it from the junction surface of the source / drain region 29, the leakage current of the junction can be reduced.

In this embodiment , Ni is used as the silicidation metal, but the same configuration can be realized even if another metal having a plurality of silicide states, such as Co or W, is used.

In the above-described embodiment , a metal layer capable of silicidation is formed on the surface with the first silicon surface exposed and the second silicon surface covered with an insulating layer, and the first silicide is formed at the first temperature. After forming the layer, the insulating cap layer covering the second silicon surface is removed, a metal layer capable of silicidation is formed on the substrate, and does not affect the first silicide layer, which is lower than the first temperature. A silicidation reaction was caused at the second temperature to form a deep silicide region only in the second silicon region. Although the first silicide region and the second silicide region are formed using the same metal, different metals can also be used. When different metals are used, the degree of freedom such as temperature selection is improved.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment .

  As shown in FIG. 3A, a gate insulating film 2 of silicon oxide is formed on the surface of the silicon substrate 1 by thermal oxidation. A polysilicon layer 3 is formed on the gate insulating film 2 and patterned using a resist pattern. In this state, n-type impurities are ion-implanted to form extensions 4. Impurities are also implanted into the polysilicon layer 3 of the gate electrode.

  As shown in FIG. 3B, a silicon oxide insulating cap layer 5 is formed so as to cover the gate electrode 3. Subsequently, a silicon nitride layer 6 is formed, and sidewalls 6 are formed by anisotropic etching. The surface of the gate electrode 3 is covered with the insulating cap layer 5. Sidewall 6 is also used as a mask, and impurities are ion-implanted to form source / drain regions 8.

As shown in FIG. 3C, a cobalt layer 10 is formed on the substrate by sputtering in a state where the polysilicon layer 3 of the gate electrode is covered with the insulating cap layer 5. An RTA layer is used for annealing at 550 ° C. for 30 seconds to cause a silicidation reaction. A silicidation reaction occurs on the surface of the source / drain region 8, and a cobalt silicide region 11 having a depth of about 50 nm is formed. Thereafter, the unreacted cobalt layer 10 is removed by wet etching using H ₂ SO ₄ .

  FIG. 3D shows a state where the unreacted cobalt layer 10 has been removed. The insulating cap layer 5 covering the polysilicon layer 3 of the gate electrode is removed by wet etching using dilute HF.

  As shown in FIG. 3E, a nickel layer 13 is formed on the substrate by sputtering with the polysilicon layer 3 exposed. In this state, annealing is performed at 400 ° C. for 60 seconds using an RTA apparatus to cause a silicidation reaction between the nickel layer 13 and silicon. In the polysilicon layer 3 of the gate electrode, the silicon layer directly contacts the nickel layer 13 and the silicidation reaction proceeds. In the source / drain region 8, since the cobalt silicide region 11 already formed on the surface exists, the diffusion of nickel from the nickel layer 13 is suppressed. For this reason, even when the polysilicon layer 3 is fully silicidized, only a thin CoNiSi layer 14 is formed on the surface of the source / drain region 8.

  As shown in FIG. 3F, the unreacted nickel layer 13 is removed by wet etching to obtain a fully silicidized MOS transistor structure.

  After forming a silicide region in the source / drain region using a metal having a high solid phase diffusion temperature in silicon, the silicon layer of the gate electrode is exposed and a silicidation reaction with a metal having a low solid phase diffusion temperature in silicon is performed. By doing so, it becomes easy to fully silicide the gate electrode and limit the depth of the silicide region of the source / drain region. In addition to Co and Ni, other metal pairs having different solid phase diffusion temperatures can be used.

In the above embodiment , the silicidation reaction is performed twice to limit the depth of the silicide region of the source / drain region. Hereinafter, an embodiment will be described in which only one silicidation reaction is used and the bottom surface of the silicide region is separated from the junction surface of the source / drain region.

As shown in FIG. 4A, a gate insulating layer 2 made of a silicon oxide layer having a thickness of 2 nm is formed on the surface of the silicon substrate 1 by thermal oxidation. Subsequently, a polysilicon layer 35 having a thickness of 50 nm is formed on the gate insulating layer 2 by thermal CVD. B is ion-implanted into the polysilicon layer 35 with an acceleration energy of 0.5 keV and a dose of 2E15 cm ⁻² . Since the acceleration energy is low, the surface of the polysilicon layer 35 becomes a high-concentration B-added region.

  As shown in FIG. 4B, the polysilicon layer 35 is patterned by plasma etching using a resist pattern to form a gate electrode. After the etching of the polysilicon layer 35, a post-treatment with dilute HF is performed to remove the gate insulating film 2 around the gate electrode 35. Using the gate electrode 35 as a mask, B is ion-implanted to form an extension 27.

A silicon nitride layer is formed by thermal CVD, and the entire surface is etched by plasma to form a sidewall 28 on the side wall of the gate electrode 35. Using the gate electrode 35 on which the sidewall 28 is formed as a mask, B ions are ion-implanted with an acceleration energy of 5 keV and a dose amount of 3E15 cm ⁻² to form a source / drain region 29. Compared to the acceleration energy of 0.5 keV at the time of ion implantation of B ions shown in FIG. 4A, the acceleration energy is significantly higher as 5 keV, so that the B concentration on the surface of the source / drain region 29 is much higher than the B concentration on the surface of the gate electrode 35. Low.

As shown in FIG. 4C, a silicon layer 37 having a thickness of 30 nm is epitaxially grown by thermal CVD. For example, after pre-baking at 700-900 ° C. for 1-5 minutes, the deposition temperature is 650-750 ° C., the deposition pressure is 40-100 torr, the supply gas is SiH ₂ Cl ₂ 50-200 sccm, HCl 5-20 sccm, H ₂ 10 Selective epitaxial growth of silicon is performed at -20 slm. Since the gate electrode 35 has a high B concentration on the surface, a silicon layer does not grow thereon. The silicon layer does not grow on the insulating layer 28. The silicon layer 37 is selectively grown epitaxially only on the exposed surface of the source / drain region 29.

As shown in FIG. 4D, B is ion-implanted with an acceleration energy of 3 keV and a dose of 5E15 cm ⁻² . B is added to the grown silicon layer 37 and the gate electrode 35 at an appropriate concentration. Subsequently, the implanted B is activated by annealing at 1000 ° C. for 1 second using an RTA apparatus.

  As shown in FIG. 4E, a nickel layer 39 is formed by sputtering with a thickness of 30 nm on the surface lifted by growing the silicon layer 37 on the source / drain regions 29. An annealing is performed at 400 ° C. for 1 minute using an RTA apparatus to cause a silicidation reaction. Thereafter, the unreacted nickel layer 39 is removed by wet etching.

  As shown in FIG. 4F, the gate electrode 35 is converted into a silicide layer 40 by a silicidation reaction. A silicide layer 41 is formed in the source / drain region 29 whose surface is raised. Since the epitaxial silicon layer 37 is formed on the surface of the source / drain region 29 and the silicon surface is lifted, the bottom surface of the silicide layer 41 is separated from the junction surface of the source / drain region 29 by a sufficient distance. Leakage current at the junction surface of the source / drain region 29 can be reduced.

In the above-described embodiment , since the B concentration on the surface of the gate electrode is set high, the growth of silicon thereon can be prevented, and the irregular growth of silicon on the gate electrode, which becomes an obstacle to subsequent processes, can be prevented. . Even if another p-type impurity such as Ga or In is used in place of B, the same silicon growth suppression may be possible.

5A-5G illustrate another embodiment of the present invention.

  As shown in FIG. 5A, a silicon oxide layer 2 having a thickness of 2 nm is formed on the surface of the silicon substrate 1 by thermal oxidation, and then a polysilicon layer 25 having a thickness of 50 nm is formed by thermal CVD. An insulating cap layer 26 made of a silicon oxide layer having a thickness of 20 nm is further formed on the polysilicon layer 25 by thermal CVD. The laminated structure of the insulating cap layer 26 and the polysilicon layer 25 is patterned using a resist mask, and the gate insulating film 2 around the gate electrode is removed with diluted HF. B ions are implanted to form a shallow extension 27.

As shown in FIG. 5B, a silicon nitride layer is formed by thermal CVD, and the sidewalls 28 are left on the sidewalls of the gate electrode structure by whole surface etching using plasma. In this state, B is ion-implanted with an acceleration energy of 5 keV and a dose of 3E15 cm ⁻² to form source / drain regions 29.

  As shown in FIG. 5C, a silicon layer 37 having a thickness of 30 nm is epitaxially formed by thermal CVD. Silicon does not grow on the surfaces of the insulating cap layer 26 and the sidewalls 28, and the silicon layer 37 is selectively grown epitaxially on the exposed source / drain region 29 surfaces.

As shown in FIG. 5D, B is ion-implanted into the silicon layer 37 on the source / drain region 29 with an acceleration energy of 3 keV and a dose of 5E15 cm ⁻² . Subsequently, annealing is performed at 1000 ° C. for 1 second using an RTA apparatus to activate the ion-implanted B.

  As shown in FIG. 5E, the insulating cap layer 26 on the polysilicon layer 25 is etched and removed using dilute HF. Note that the insulating cap layer 26 may be removed by plasma etching instead of removal by a chemical solution.

  As shown in FIG. 5F, a nickel layer 39 having a thickness of 30 nm is formed by sputtering so as to cover the surfaces of the polysilicon layer 25 and the epitaxial silicon layer 37 from which the insulating cap layer has been removed. Using an RTA apparatus, annealing at 400 ° C. for 1 minute is performed to cause a silicidation reaction. A silicidation reaction occurs from the surfaces of the epitaxial silicon layer 37 and the polysilicon gate electrode 25 on the source / drain regions 29 to form a NiSi layer.

  After the silicidation reaction, the unreacted nickel layer 39 is removed by wet etching.

  FIG. 5G schematically shows a cross-sectional structure of a silicon substrate in which a silicidation reaction is performed and an unreacted nickel layer is removed. The gate electrode is formed by full silicidation of the NiSi layer 40, and the NiSi layer 41 is formed in the source / drain region 29. The bottom surface of the NiSi layer 41 is separated from the junction surface of the source / drain region 29 by a sufficient distance to reduce leakage current.

  When Al replacement technology is used, an Al gate electrode having a resistance lower than that of silicide can be formed. However, although the work function of the Al gate is suitable for an n-channel MOSFET, it is inappropriate for a p-channel MOSFET. If the gate electrode of the p-channel MOSFET is formed by full silicidation and the gate electrode of the n-channel MOSFET is formed by Al substitution technology, a high-performance transistor can be provided.

  If a mask or the like is used so that the gate electrode of the p-channel MOSFET is not replaced with Al, the number of processes is greatly increased. When the present inventors form a metal-rich silicide having a metal composition higher than that of silicon, even if Al is in contact with the surface, Al substitution is prevented, and the composition, form, or work of the silicide is prevented. We found that the functions can be kept substantially the same. The work function 4.9 eV of nickel silicide is suitable for a p-channel MOSFET, and the work function 3.9 eV of a substituted Al gate is suitable for an n-channel MOSFET.

6A-6G are schematic cross-sectional views illustrating other embodiments of the present invention.

  As shown in FIG. 6A, an element isolation region is formed in the silicon substrate 1, and an n-well 44 for a p-channel MOSFET and a p-well 45 for an n-channel MOSFET are formed. A gate insulating film made of, for example, a silicon oxide layer having a thickness of 2 nm is formed on the surface of the silicon substrate 1, and a polysilicon layer 25 having a thickness of 50 nm is formed thereon. In the n-channel MOSFET region, a silicon oxide layer 26 serving as an insulating cap layer having a thickness of, for example, 20 nm is formed on the polysilicon layer 25. The resist pattern RP1 is patterned into a gate electrode shape of an n-channel MOSFET by lithography. Using the resist pattern RP1 as a mask, the insulating cap layer 26 is etched into a gate electrode shape. Thereafter, the resist pattern RP1 is removed.

  As shown in FIG. 6B, a gate electrode-shaped resist pattern RP2 is formed on the polysilicon layer in the p-channel MOSFET region. Using the resist pattern RP2 and the insulating cap layer 26 as a mask, the polysilicon layer 25 is etched to form a gate electrode. Using the gate electrode as a mask, the extensions 46 and 47 are separately ion-implanted using a resist mask.

  As shown in FIG. 6C, after the sidewall 48 is formed, ion implantation of the source / drain contact region 49 of the p-channel MOSFET and the source / drain contact region 50 of the n-channel MOSFET is separately performed using a resist mask. The polysilicon layer 25 of the p-channel MOSFET becomes a p-type polysilicon layer 25p by ion implantation of p-type impurities.

As shown in FIG. 6D, a nickel layer 51 having a thickness of 30 nm to 50 nm, for example, a thickness of 30 nm, is formed on the silicon substrate surface by sputtering. In the n-channel MOSFET, since the polysilicon layer 25 is covered with the insulating cap layer 26, it is not in contact with the nickel layer 51. In this state, annealing for causing a silicidation reaction is performed at 400 ° C. for 40 seconds. Depending on the Ni thickness, Ni-rich silicide is formed.

As shown in FIG. 6E, nickel silicide regions 53 and 52 are formed in the gate electrode and source / drain regions of the p-channel MOSFET, and a nickel silicide region 52 is formed in the source / drain region 50 of the n-channel MOSFET. By selecting the thickness of the nickel layer 51, the work function can be adjusted in the range of 0.5 eV. Nickel silicide layer serving as the gate electrode 53, selects the annealing conditions so that the metallic rich.

  As shown in FIG. 6F, an interlayer insulating layer 55 such as silicon oxide is formed on the surface of the silicon substrate so as to cover the gate electrode, and contact holes for the gate electrode and the source / drain regions are patterned.

  As shown in FIG. 6G, an aluminum layer 57 is formed on the interlayer insulating layer 55 with the contact holes patterned by sputtering or the like. In this state, for example, when annealing is performed at 350 ° C. for 3 hours, the polysilicon layer 25 in contact with the aluminum layer 57 is replaced with aluminum and converted into the aluminum gate electrode 59. The metal-rich silicide gate electrode 53 is not replaced with aluminum and maintains a nickel silicide phase. Thus, a nickel-rich silicide electrode 53 is formed in the p-channel MOSFET, and a replacement Al gate electrode 59 is formed in the n-channel MOSFET. Thereafter, the aluminum layer 57 is patterned to form an electrode structure.

  7A-7E are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

  As shown in FIG. 7A, a process similar to that shown in FIGS. 6A-6C is performed, and a p-type polysilicon layer 25p is applied to the p-channel MOSFET and an insulating cap layer 26 covers the surface of the polysilicon layer 25 in the n-channel MOSFET Create In this state, the doped silicon layer 60 is formed. Thereafter, chemical mechanical polishing (CMP) is performed to expose the surface of the p-type polysilicon layer 25p of the p-channel MOSFET. Note that the insulating cap layer 26 on the surface of the polysilicon layer 25 of the n-channel MOSFET remains due to the difference in the etching rate of CMP.

  As shown in FIG. 7B, for example, a nickel layer 62 having a thickness of 30 nm is formed. Nickel layer 62 is in contact with polysilicon layer 25p in the p-channel MOSFET. When annealing is performed at 400 ° C. for 40 seconds, nickel-rich nickel silicide regions 63 and 64 are formed in the silicon layer in contact with the nickel layer 62. The polysilicon layer 25p of the p-channel MOSFET is fully silicidized. The silicide region 63 is in a state separated from the junction surface of the source / drain regions 49 and 50 by a certain distance. The unreacted nickel layer 62 is removed by wet etching.

  As shown in FIG. 7C, an interlayer insulating layer 55 such as silicon oxide is formed on the silicon substrate surface to form contact holes. In the n-channel MOSFET, a contact hole is formed through the insulating cap layer 26.

  As shown in FIG. 7D, an aluminum layer 65 is formed to fill the contact hole. Thereafter, substitution annealing is performed at 350 ° C. for about 3 hours.

  As shown in FIG. 7E, in the n-channel MOSFET, the polysilicon layer 25 is replaced with aluminum, and an aluminum gate electrode 66 is formed. In the p-channel MOSFET, the nickel-rich silicide gate electrode 64 is held as it is. Thereafter, the aluminum layer 65 is patterned to form an electrode.

  In the above embodiment, the nickel silicide gate electrode is formed. However, other metals may be used instead of nickel, and metal-rich silicides of these metals may be formed.

Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

  The features of the present invention will be described below.

(Appendix 1) A silicon substrate,
A gate insulating layer formed on the silicon substrate;
A gate electrode of a first silicide layer formed on the gate insulating layer by a silicidation reaction at a first temperature;
Source / drain regions formed in the silicon substrate on both sides of the gate electrode;
A source / drain silicide region of a second silicide layer formed in the source / drain region by a silicidation reaction at a second temperature higher than the first temperature;
A semiconductor device.

    (Additional remark 2) It has the 3rd silicide layer which contains both the metal of the 1st silicide layer and the metal of the 2nd silicide layer which were further formed on the 2nd silicide layer, The metal of the 2nd silicide layer The semiconductor device according to appendix 1, wherein the metal is a metal having a higher solid phase diffusion temperature in silicon than the metal of the first silicide layer.

    (Supplementary note 3) The semiconductor device according to supplementary note 2, wherein the first silicide layer is nickel silicide, and the second silicide is cobalt silicide.

    (Supplementary note 4) The semiconductor device according to supplementary note 1, wherein the metal of the first silicide layer and the metal of the second silicide layer are the same metal having different valences.

    (Supplementary note 5) The semiconductor device according to supplementary note 1, wherein the metal of the first silicide layer and the metal of the second silicide layer are any one of Ni, Co, and W.

(Supplementary Note 6) The first silicide layer is NiSi layer, the second silicide layer is of Supplementary Notes 4 wherein the NiSi ₂ layer.

(Appendix 7) A silicon substrate,
A gate insulating layer formed on the silicon substrate;
A gate electrode formed of one kind of silicide layer on the gate insulating layer;
Source / drain regions formed in the silicon substrate on both sides of the gate electrode;
A source / drain silicide region formed of two types of silicide layers in the source / drain region;
A semiconductor device.

    (Supplementary Note 8) The source / drain silicide layer includes a deep first silicide region formed of a first metal silicide having a high solid phase diffusion temperature and a second metal having a low solid phase diffusion temperature in the first silicide region. And a shallow second silicon region formed by diffusion of the semiconductor device.

(Appendix 9) Forming an insulated gate structure on a silicon substrate by laminating a gate insulating layer, a silicon layer, and an insulating cap layer;
Forming an insulating sidewall on a sidewall of the insulating gate structure;
Forming source / drain regions in the silicon substrate on both sides of an insulated gate structure with the insulating sidewall;
With the source / drain region exposed, a first metal layer is formed on the silicon substrate, a first silicidation reaction is performed at a first temperature, and a first silicide layer is formed on the source / drain region. Forming a step;
The insulating cap layer is removed, a second metal layer is formed on the silicon substrate, a second silicidation reaction is performed at a second temperature lower than the first temperature, and silicon having the insulated gate structure is formed. Fully silicidizing the layer and not substantially increasing the depth of the first silicide layer in the source / drain region;
A method of manufacturing a semiconductor device including:

    (Supplementary note 10) The semiconductor according to supplementary note 9, wherein when there is no first silicide layer, a depth of the silicide layer formed by the second silicidation reaction is greater than a depth of the first silicide layer. Device manufacturing method.

    (Additional remark 11) The manufacturing method of the semiconductor device of Additional remark 9 whose said 1st metal layer is a cobalt layer and whose said 2nd metal layer is a nickel layer.

    (Additional remark 12) The manufacturing method of the semiconductor device of Additional remark 11 whose said 1st temperature is 550 degreeC or more and whose said 2nd temperature is 400 degrees C or less.

    (Supplementary note 13) The method for manufacturing a semiconductor device according to supplementary note 9, wherein the first metal layer and the second metal layer are formed of any one of Ni, Co, and W.

    (Supplementary note 14) The semiconductor according to supplementary note 13, wherein the first metal layer and the second metal layer are nickel layers, the first temperature is 750 ° C. or more, and the second temperature is 400 degrees or less. Device manufacturing method.

(Supplementary Note 15) A step of forming a stacked layer of a gate insulating layer and a polysilicon layer on a semiconductor substrate;
Doping the surface of the polysilicon layer with a high concentration of p-type impurities with a first acceleration energy;
Patterning the polysilicon layer and the gate insulating layer to form a gate electrode and exposing a substrate silicon surface on both sides thereof;
Deeply implanting p-type impurities into the exposed substrate silicon surface with a second acceleration energy higher than the first acceleration energy;
Growing a silicon layer only on the substrate silicon surface without growing on the polysilicon layer surface; and
A method of manufacturing a semiconductor device including:

    (Supplementary note 16) The method for manufacturing a semiconductor device according to supplementary note 15, wherein the p-type impurity is any one of B, Ga, and In.

    (Additional remark 17) Furthermore, the manufacturing method of the semiconductor device of Additional remark 15 including the process of performing silicidation reaction from the said polysilicon layer surface and the said substrate silicon surface.

(Supplementary Note 18) A step of forming a stack of a gate insulating layer, a polysilicon layer, and an insulating cap layer on a semiconductor substrate;
Patterning the insulating cap layer, the polysilicon layer, and the gate insulating layer to form a gate electrode and exposing a substrate silicon surface on both sides thereof;
Ion implantation of impurities into the exposed substrate silicon surface;
Growing a silicon layer on the substrate silicon surface;
Removing the insulating cap layer;
Performing a silicidation reaction from the polysilicon layer surface and the substrate silicon surface;
A method of manufacturing a semiconductor device including:

(Supplementary Note 19) A step of forming a stacked layer of a gate insulating layer, a polysilicon layer, and an insulating cap layer on a semiconductor substrate including a p-channel MOSFET region and an n-channel MOSFET region;
Patterning the insulating cap layer and leaving the gate electrode shape in the n-channel MOSFET region; and
A gate electrode-shaped resist pattern is formed on the polysilicon layer in the p-channel MOSFET region, and the polysilicon layer and the gate insulating layer are patterned using the resist pattern and the insulating cap layer as a mask to form a gate electrode. And the process of exposing the silicon surface of the substrate on both sides,
Performing a silicidation reaction from the exposed substrate silicon surface and the polysilicon gate electrode surface of the p-channel MOSFET to form a metal-rich silicide region;
Forming an insulating layer covering the silicide region;
Forming a contact hole reaching the gate electrode through the insulating layer and the insulating cap layer;
Filling the contact holes to form an aluminum layer;
Performing annealing and replacing the gate electrode of the n-channel MOSFET with aluminum;
A method of manufacturing a semiconductor device including:

(Appendix 20) A step of forming a stacked layer of a gate insulating layer, a polysilicon layer, and an insulating cap layer on a semiconductor substrate including a p-channel MOSFET region and an n-channel MOSFET region;
Patterning the insulating cap layer and leaving the gate electrode shape in the n-channel MOSFET region; and
A gate electrode-shaped resist pattern is formed on the polysilicon layer in the p-channel MOSFET region, and the polysilicon layer and the gate insulating layer are patterned using the resist pattern and the insulating cap layer as a mask to form a gate electrode. And the process of exposing the silicon surface of the substrate on both sides,
Growing a silicon layer embedding the gate electrode on the substrate;
Chemically mechanically polishing the silicon layer, leaving the insulating cap layer of the n-channel MOSFET, and exposing the gate electrode of the p-channel MOSFET;
Performing a silicidation reaction from the silicon layer surface and the polysilicon gate electrode surface of the p-channel MOSFET to form a metal-rich silicide region;
Forming an insulating layer covering the silicide region;
Forming a contact hole reaching the gate electrode through the insulating layer and the insulating cap layer;
Filling the contact holes to form an aluminum layer;
Performing annealing and replacing the gate electrode of the n-channel MOSFET with aluminum;
A method of manufacturing a semiconductor device including:

  It can be used for a semiconductor device having a fine CMOSFET.

1A to 1E are cross-sectional views and graphs for explaining a preliminary experiment and its results. 2A to 2H are cross-sectional views of a substrate illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG 3A~3F is a cross-sectional view of the substrate for explaining a manufacturing method of a semiconductor device according to another embodiment of the present invention. FIG 4A~4F is a cross-sectional view of a substrate for explaining the method of manufacturing a semiconductor device according to another embodiment of the present invention. FIG 5A~5G is a cross-sectional view of the substrate for explaining a manufacturing method of a semiconductor device according to another embodiment of the present invention. 6A to 6G are cross-sectional views of a substrate for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 7A to 7E are cross-sectional views of a substrate for explaining a method of manufacturing a semiconductor device according to another embodiment of the present invention .

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate insulating layer 3 Polysilicon layer 4 Extension 5 Insulating cap layer 6 Insulating sidewall 8 Source / drain region 10 Cobalt layer 11 Cobalt silicide region 13 Nickel layer 14 Cobalt nickel silicide region 22, 24 Nickel layer 23 NiSi ₂ Layer 25 Polysilicon layer 26 Insulating cap layer 28 Side wall 29 Source / drain region 30 Nickel layer 31 NiSi ₂ region 32 Nickel layer 33 NiSi gate electrode 35 Polysilicon layer 37 Silicon layer 39 Nickel layer 40, 41 NiSi region 44 n-well 45 p-well 46, 47 extension 49, 50 source / drain contact region 51 nickel layer 52, 53 (Ni-rich) nickel silicide region 55 interlayer insulation 57 Al layer 59 substituted Al region 62 nickel layer 63, 64 (Ni-rich) nickel silicide region 65 Al layer 66 substituted Al region

Claims (2)

forming a stack of a gate insulating layer, a polysilicon layer, and an insulating cap layer on a silicon substrate including a p-channel MOSFET region and an n-channel MOSFET region;
Patterning the insulating cap layer and leaving the patterned insulating cap layer in a gate electrode shape on the polysilicon layer in the n-channel MOSFET region;
A gate electrode-shaped resist pattern is formed on the polysilicon layer in the p-channel MOSFET region from which the insulating cap layer has been removed, and the polysilicon layer and gate are formed using the resist pattern and the patterned insulating cap layer as a mask. patterning the insulating layer, thereby forming a gate electrode on the p-channel and n-channel MOSFET region, a step of exposing the silicon substrate table surface on both sides,
Perform silicidation reaction from the exposed silicon substrate table surface and the polysilicon gate electrode surface of the p-channel MOSFET, to form a metal rich silicide regions in said silicon substrate surface, a polysilicon gate electrode of the p-channel MOSFET Forming a metal-rich silicide region by full silicidation; and
Forming an insulating layer covering the silicide region;
The insulating layer, a step of penetrating the insulating cap layer is formed the p-channel MOSFET of the gate electrode and the n-channel MOSFET comprising a silicide region the polysilicon gate electrode contact hole reaching the respective,
Filling each contact hole to form an aluminum layer;
Performing annealing and replacing the polysilicon gate electrode of the n-channel MOSFET with aluminum without replacing the gate electrode made of the metal-rich silicide region of the p-channel MOSFET with aluminum ; and
A method of manufacturing a semiconductor device including: forming a stack of a gate insulating layer, a polysilicon layer, and an insulating cap layer on a silicon substrate including a p-channel MOSFET region and an n-channel MOSFET region;
Patterning the insulating cap layer and leaving the patterned insulating cap layer in a gate electrode shape on the polysilicon layer in the n-channel MOSFET region;
A gate electrode-shaped resist pattern is formed on the polysilicon layer in the p-channel MOSFET region from which the cap layer has been removed, and the polysilicon layer and the gate insulation are formed using the resist pattern and the patterned insulating cap layer as a mask. a step of patterning the layer, to form a gate electrode on the p-channel and n-channel MOSFET region, exposing the silicon substrate table surface on both sides,
Growing a silicon layer embedding the gate electrode on the silicon substrate;
Chemically mechanical polishing the silicon layer, leaving a patterned insulating cap layer of the n-channel MOSFET, exposing a polysilicon gate electrode of the p-channel MOSFET;
A silicidation reaction is performed from the surface of the silicon layer and the exposed polysilicon gate electrode surface of the p-channel MOSFET to form a metal-rich silicide region on the silicon layer surface, and a polysilicon gate electrode of the p-channel MOSFET is formed. Forming a metal-rich silicide region by full silicidation; and
Forming an insulating layer covering the silicide region;
The insulating layer, a step of penetrating the insulating cap layer is formed the p-channel MOSFET of the gate electrode and the n-channel MOSFET comprising a silicide region the polysilicon gate electrode contact hole reaching the respective,
Filling each contact hole to form an aluminum layer;
Performing annealing and replacing the polysilicon gate electrode of the n-channel MOSFET with aluminum without replacing the gate electrode made of the metal-rich silicide region of the p-channel MOSFET with aluminum ; and
A method of manufacturing a semiconductor device including:

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