JP4743629B2 - Adaptive array antenna receiver - Google Patents

Description

  The present invention relates to an adaptive array antenna receiving apparatus.

  As a high-speed wireless transmission system, a wireless LAN (Local Area Network) is spreading. Among the wireless LAN standards, IEEE 802.11a and g employ an OFDM (Orthogonal Frequency Division Multiplexing) transmission system as a modulation system. In addition, the OFDM method is adopted in terrestrial digital broadcasting, for which some services have been started.

  OFDM is a modulation scheme that uses a large number of orthogonal carriers, and is a type of multicarrier digital modulation scheme. OFDM has a number of features such as relatively high frequency utilization efficiency and being capable of modulation / demodulation processing by FFT (Fast Fourier Transform).

  Since each carrier is set to a low transmission rate with respect to frequency selective fading, flat fading is observed when one carrier is seen. In addition, a guard interval is set at the head of each OFDM symbol in order to reduce the influence of delayed waves. Therefore, particularly in a multipath environment, it exhibits excellent performance with respect to the single carrier method.

  On the other hand, an adaptive array antenna is known as a system that ensures good communication quality by suppressing interference waves. An MMSE (Minimum Mean Square Error) adaptive array antenna, which is one of the operation principles, is a system that determines an optimum weight by minimizing an error signal between a reference signal prepared on the receiving side and an actual array output signal. It is. Strictly speaking, the desired signal itself is required as a reference signal. However, in practice, since there is prior knowledge about the properties (frequency band, modulation method, etc.) of the desired signal, it is appropriate to process the combined output signal of the array. Can be obtained.

As a method for optimizing such weights, the head guard interval and the tail guard interval are extracted from the OFDM symbol, and the weights are optimized so that the extracted head guard interval matches the tail guard interval. There has been proposed a method of performing optimization over weights of OFDM symbol sections and finally optimizing weights (Non-patent Document 1).
Satoshi Hori, Nobuyoshi Kikuma, Naoki Inagaki, “MMSE Adaptive Array Using Guard Intervals in OFDM”, IEICE Transactions B Vol. J85-B No. 9 pp. 1608-1615 September 2002

  However, in the method described in Non-Patent Document 1, the weight adjusted so that the head guard interval matches the tail guard interval in one symbol interval is used for adjusting the weight in the next symbol interval. There is a problem that it takes a long time to be optimized.

  Therefore, the present invention has been made to solve such a problem, and an object of the present invention is to provide an adaptive array antenna receiving apparatus that completes optimization of weights before reception processing is started.

  According to the present invention, an adaptive array antenna receiving apparatus is an adaptive array antenna receiving apparatus that receives and processes a transmission signal including a plurality of data sections in which transmission data is stored, the array antenna, a weight controller, a signal And processing means. The array antenna receives a plurality of received signals by a plurality of antenna elements. The weight controller includes signal power versus interference power from a plurality of received signals based on the received signals of the first and second signals that are included in one data section of the plurality of data sections and have the same waveform. A plurality of weights for generating a combined reception signal in which the ratio or the signal power to noise power ratio is maximized are optimized until reception processing of reception signals in a plurality of data sections is started. The signal processing means processes the received signals in a plurality of data sections using a plurality of weights optimized by the weight controller, and outputs a demodulated signal. Then, the weight controller performs a plurality of weight optimization processing for bringing the received signal of the first signal before being multiplied by the plurality of weights closer to the received signal of the second signal after being multiplied by the plurality of weights. Repeat to optimize multiple weights.

  Preferably, the transmission signal further includes a preamble for adjusting reception characteristics in the array antenna. The weight controller repeatedly performs the optimization process using the received signal of the preamble and the received signal of one data section.

  Preferably, the adaptive array antenna receiving apparatus further includes an interference wave detector. The interference wave detector detects the occurrence and / or disappearance of interference waves for a plurality of received signals. The weight controller repeatedly performs the optimization process when the interference wave detector detects the occurrence and / or disappearance of the interference wave.

  In the present invention, based on the received signals of the first and second signals having the same waveform included in one data section until the reception processing of the received signals received by the plurality of antenna elements is started, A plurality of weight optimization processes for generating a composite reception signal in which the signal power-to-interference power ratio or the signal power-to-noise power ratio is maximized from the reception signal are repeatedly performed, and the plurality of optimization processes are performed. Reception processing of the received signal is performed using the weight.

  Therefore, according to the present invention, it is possible to complete the optimization of the weight and start the reception process of the reception signal before the reception process is started.

  Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
1 is a schematic block diagram showing a configuration of an adaptive array antenna receiving apparatus according to Embodiment 1 of the present invention. An adaptive array antenna receiving apparatus 100 according to Embodiment 1 of the present invention includes an array antenna 10, a buffer 20, multipliers 31 to 3M (M is an integer of 2 or more), an adder 40, and a tail detector 50. , A head detector 60, a weight controller 70, a GI (Guard Interval) remover 80, an FFT 90, a channel estimator 110, and a demodulator 120.

  The array antenna 10 includes M antenna elements 1 to M. Array antenna 10 receives incoming radio waves by antenna elements 1 to M and outputs M received signals RS_1 to RS_M to buffer 20.

  The buffer 20 holds the M received signals RS_1 to RS_M from the array antenna 10 for a certain period of time, and outputs the held M received signals RS_1 to RS_M to the tail detector 50. The received signals RS_1 to RS_M are output to M multipliers 31 to 3M, respectively.

The multipliers 31 to 3 </ b> M receive M received signals RS_ <b> 1 to RS_M from the buffer 20, and receive M weights w ₁ (i) to w _M (i) from the weight controller 70. I is composed of i = 0, 1, 2, 3,..., And the number of optimization processes for optimizing _M weights w ₁ (i) to w _M (i) by a method to be described later. To express. The multipliers 31 to 3M respectively multiply the reception signals RS_1 to RS_M and the weights w ₁ (i) to w _M (i), and the multiplication results RS_1 * w ₁ (i) to RS_M * w _M (I) is output to the adder 40.

The adder 40 receives M multiplication results RS_1 * w ₁ (i) to RS_M * w _M (i) from the multipliers 31 to 3M, and receives the M multiplication results RS_1 * w ₁ (i) to RS_M * w _M (i) is added to generate a composite output signal RS. Then, the adder 40 outputs the generated combined output signal RS to the head detector 60 and the GI remover 80.

  The tail detector 50 receives M received signals RS_1 to RS_M from the buffer 20, detects M tail signals RSt_1 to RSt_M from the received M received signals RS_1 to RS_M, and detects the detected M number of signals. The tail signals RSt_1 to RSt_M are output to the wait controller 70.

  The head detector 60 receives the combined output signal RS from the adder 40 and detects the head signal RSh (i) from the received combined output signal RS. Then, the head detector 60 outputs the detected head signal RSh (i) to the weight controller 70.

The weight controller 70 receives M tail signals RSt_1 to RSt_M from the tail detector 50 and receives a head signal RSh (i) from the head detector 60. Then, the weight controller 70 determines the square error between the weighted synthesis result of the M tail signals RSt_1 to RSt_M and the M weights w ₁ (i) to w _M (i) and the head signal RSh (i). M weights w ₁ (i) to w _M (i) are adjusted so as to be minimized, and the adjusted M weights w ₁ (i + 1) to w _M (i + 1) are respectively supplied to multipliers 31 to 3M. Output.

Thereafter, the weight controller 70 receives the head signal RSh (i + 1) detected from the synthesized output signal RS synthesized using the _M weights w ₁ (i + 1) to w _M (i + 1), and the received head The M weights w ₁ (i + 1) to w _M (i + 1) are adjusted so that the square error between the signal RSh (i + 1) and the combined tail signal RSt is minimized, and the adjusted M weights w ₁ (i + 1) are adjusted. ) To w _M (i + 1) are output to the multipliers 31 to 3M, respectively.

The weight controller 70 uses the head signal RSh (i) detected from the combined output signal RS reflecting the adjusted M weights w ₁ (i) to w _M (i) to use the M weights w ₁ ( i) to w _M (i) adjustment is repeated a reference number of times (for example, 5 to 6 times). Thereby, the M weights w ₁ (i) to w _M (i) are optimized.

  The GI remover 80 receives the combined output signal RS from the adder 40, removes the guard interval from the received combined output signal RS, and outputs the combined output signal RS from which the guard interval has been removed to the FFT 90. The FFT 90 performs a fast Fourier transform on the combined output signal RS received from the GI remover 80 and outputs the combined output signal RS after the fast Fourier transform to the channel estimator 110 and the demodulator 120.

  Channel estimator 110 estimates propagation path fluctuation for each pilot subcarrier (PSC) based on combined output signal RS received from FFT 90, and based on the estimated propagation path fluctuation, A plurality of subcarriers existing between pilot subcarriers are linearly interpolated. Channel estimator 110 then outputs the estimated propagation path fluctuation and the result of the primary interpolation to demodulator 120.

  Demodulator 120 demodulates synthesized output signal RS based on synthesized output signal RS received from FFT 90, propagation path fluctuation received from channel estimator 110, and the result of linear interpolation, and outputs a demodulated signal.

  FIG. 2 is a time slot configuration diagram showing a unit of data to be received by the adaptive array antenna receiving apparatus 100 shown in FIG. The time slot TSL includes a preamble PRE and a payload PLD.

  The preamble PRE is provided at the head of the time slot TSL. In the preamble PRE, the same signal is continuously written twice or more, and is used to adjust reception characteristics such as gain in the array antenna 10.

  The payload PLD includes n (n is an integer of 2 or more) symbols SYM1 to SYMn. Each of n symbols SYM1 to SYMn includes GI and data. The GI is provided at the head of each symbol SYM1 to SYMn.

  FIG. 3 is a conceptual diagram showing one symbol shown in FIG. The GI is composed of a waveform obtained by copying the tail of the data. One symbol has a symbol length SYML, and the data has an effective symbol length SYMEL. Thus, one symbol includes a GI having the same waveform as the tail of the tail of the data at the head.

  As described above, data is stored in n symbols SYM1 to SYMn and transmitted / received in units of time slots TSL. Therefore, adaptive array antenna receiver 100 receives time slot TSL having n symbols SYM1 to SYMn each containing data.

FIG. 4 is a diagram for explaining an optimization method of _M weights w ₁ (i) to w _M (i). The array antenna 10 receives one time slot TSL by the antenna elements 1 to M, and receives signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2) for n symbols SYM1 to SYMn, ..., RS_1 (n) to RS_M (n) are sequentially output to the buffer 20. In this case, received signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2),..., RS_1 (n) to RS_M (n) are received signals of symbols SYM1 to SYMn, respectively. is there.

The buffer 20 sequentially receives the received signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2),..., RS_1 (n) to RS_M (n) from the array antenna 10, and receives the array antenna 10. The reception signals RS_1 (1) to RS_M (1) received first are output to the multipliers 31 to 3M and the tail detector 50. Then, the buffer 20 receives the received signals RS_1 (1) to RS_M (1), RS_1 (2) for a certain time Tconst when M weights w ₁ (i) to w _M (i) are optimized by the weight controller 70. ) To RS_M (2),..., RS_1 (n) to RS_M (n), and when a predetermined time Tconst elapses, the received signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M ( 2),..., RS_1 (n) to RS_M (n) are sequentially output to the multipliers 31 to 3M.

Multipliers 31 to 3M receive initial values w ₁ (0) to w _M (0) of _M weights from weight controller 70, and receive signals RS_1 (1) to RS_M (1) from buffer 20, respectively. . Then, the multiplier 31~3M the received signal RS_1 (1) ~RS_M (1) of the M weighted respectively to an initial value _w 1 (0) _~w multiplied by M (0), the multiplication result RS_1 (1 ) * W ₁ (0) to RS_M (1) * w _M (0) are output to the adder 40.

The adder 40 receives the multiplication results RS_1 (1) * w ₁ (0) to RS_M (1) * w _M (0) from the multipliers 31 to 3M, and receives the multiplication results RS_1 (1) * w _{1 received.} (0) to RS_M (1) * w _M (0) are added to generate a combined output signal RS (0). Then, the adder 40 outputs the combined output signal RS (0) to the head detector 60.

  The tail detector 50 receives the received signals RS_1 (1) to RS_M (1) from the buffer 20, and the tail signals RSt_1 (1) to RSt_M (1) from the received received signals RS_1 (1) to RS_M (1), respectively. Is detected. Then, the tail detector 50 outputs the detected tail signals RSt_1 (1) to RSt_M (1) to the weight controller 70. Further, the head detector 60 detects the head signal RSh (0) from the combined output signal RS (0), and outputs the detected head signal RSh (0) to the weight controller 70.

The weight controller 70 receives the tail signals RSt_1 (1) to RSt_M (1) from the tail detector 50 and the head signal RSh (0) from the head detector 60. Then, the weight controller 70 combines the tail signals RSt_1 (1) to RSt_M (1) to generate a combined tail signal RSt. As a result, the head signal RSh and the combined tail signal RSt are extracted from the symbol SYM1 shown in FIG. The combined tail signal RSt is generated by weighted combining of M tail signals RSt_1 to RSt_M and M weights w ₁ (i) to w _M (i).

Then, the weight controller 70, based on the extracted head signal RSh (0) and the combined tail signal RSt, M weights so that the square error between the head signal RSh (0) and the combined tail signal RSt is minimized. w ₁ (1) to w _M (1) are calculated, and the calculated M weights w ₁ (1) to w _M (1) are output to multipliers 31 to 3M, respectively.

Upon receiving _M weights w ₁ (1) to w _M (1) from the weight controller 70, the multipliers 31 to 3M receive _M weights for the received signals RS_1 (1) to RS_M (1), respectively. multiplied by _{w 1 (1) ~w M (} 1), the multiplication result _{RS_1 (1) * w 1 (} 1) ~RS_M (1) * w M (1) is output to the adder 40.

The adder 40 receives the multiplication results RS_1 (1) * w ₁ (1) to RS_M (1) * w _M (1) from the multipliers 31 to 3M, and receives the multiplication results RS_1 (1) * w _{1 received.} (1) to RS_M (1) * w _M (1) are added to generate a combined output signal RS (1). Then, the adder 40 outputs the combined output signal RS (1) to the head detector 60. The head detector 60 detects the head signal RSh (1) from the combined output signal RS (1), and outputs the detected head signal RSh (1) to the weight controller 70.

When receiving the head signal RSh (1) from the head detector 60, the weight controller 70 receives the M weights w ₁ (2) so that the square error between the head signal RSh (1) and the combined tail signal RSt is minimized. ) To w _M (2), and outputs the calculated M weights w ₁ (2) to w _M (2) to the multipliers 31 to 3M, respectively.

Thereafter, the weight controller 70 calculates the _M weights w ₁ (i) to w _M (i) so that the square error between the head signal RSh (i) and the combined tail signal RSt is minimized. Is repeated the reference number i_std (for example, 5 to 6 times). The wait control unit 70, when the number of preferred process of the M weights _{w 1 (i) ~w M (} i) reaches the reference number T_std, the M weights _w 1 (i) _~w M ( i) is determined to be optimized, and M weights w ₁ (i_std) to w _M (i_std) are output to multipliers 31 to 3M, respectively. The weight controller 70 repeats the optimization process of the _M weights w ₁ (i) to w _M (i) for the reference number i_std within a predetermined time Tconst, and optimizes the M weights w ₁ ( i_std) to w _M (i_std) are output to multipliers 31 to 3M, respectively.

That is, in the wait controller 70, the buffer 20 holds the received signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2), ..., RS_1 (n) to RS_M (n). M weights w ₁ (i_std) to w _M (i_std) are generated during a certain time Tconst, and the buffer 20 receives the received signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2). ),..., RS_1 (n) to RS_M (n) are output to the multipliers 31 to 3M, respectively, to the multipliers 31 to 3M having _M weights w ₁ (i_std) to w _M (i_std). Has completed the output.

Then, the multipliers 31 to 3M multiply the reception signals RS_1 (1) to RS_M (1) by M weights w ₁ (i_std) to w _M (i_std), respectively, and the multiplication result RS_1 (1) * w ₁ (i_std) to RS_M (1) * w _M (i_std) are output to the adder 40. After that, the multipliers 31 to 3M respectively add _M weights w ₁ (i_std) to w _M (i_std) to the received signals RS_1 (2) to RS_M (2), ..., RS_1 (n) to RS_M (n). ) Sequentially, and the multiplication results RS_1 (2) * w ₁ (i_std) to RS_M (2) * w _M (i_std), RS_1 (3) * w ₁ (i_std) to RS_M (3) * w _M (3) i_std),..., RS_1 (n) * w ₁ (i_std) to RS_M (n) * w _M (i_std) are sequentially output to the adder 40.

The adder 40 receives multiplication results RS_1 (1) * w ₁ (i_std) to RS_M (1) * w _M (i_std), RS_1 (2) * w ₁ (i_std) to RS_M (2) from the multipliers 31 to 3M. * W _M (i_std), RS_1 (3) * w ₁ (i_std) to RS_M (3) * w _M (i_std),..., RS_1 (n) * w ₁ (i_std) to RS_M (n) * w _M (i_std) is sequentially received. The adder 40 adds the multiplication results RS_1 (1) * w ₁ (i_std) to RS_M (1) * w _M (i_std), and adds the combined output signal RS1 that is the received signal of the symbol SYM1 to the GI remover 80. Then, multiplication results RS_1 (2) * w ₁ (i_std) to RS_M (2) * w _M (i_std) are added, and the combined output signal RS2 that is the received signal of the symbol SYM2 is supplied to the GI remover 80. In the same manner, the multiplication results RS_1 (n) * w ₁ (i_std) to RS_M (n) * w _M (i_std) are added in the same manner, and the combined output signal RSn that is the received signal of the symbol SYMn is added to the GI remover Output to 80.

As described above, in the present invention, reception processing of the reception signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2),..., RS_1 (n) to RS_M (n) is started. Until the head signal RSh and M tail signals RSt_1 to RSt_M included in the first symbol SYM1 among the n symbols SYM1 to SYMn are detected, and the detected M tail signals RSt_1 to RSt_M the M weights _w 1 (i) _~w M (i) and weighted combination result between, M-number of the weight _w 1 as square errors between the head signal RSh is minimized (i) _~w M (i) Is optimized. Then, using the optimized M weights w ₁ (i) to w _M (i), the received signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2),. Reception processing of RS_1 (n) to RS_M (n) is performed.

Therefore, according to the present invention, the optimization of the _M weights w ₁ (i) to w _M (i) is completed before the reception process is started, and the reception signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2),..., RS_1 (n) to RS_M (n) can be received.

  FIG. 5 is a timing chart of pilot subcarriers. In the OFDM transmission scheme, there are a plurality of subcarriers having different frequencies. Hereinafter, an example of subcarrier arrangement in the IEEE 802.11a system, which is one system of the wireless LAN, will be described.

  In the IEEE802.11a system, 52 subcarriers are provided. Of the 52 subcarriers, one pilot subcarrier PSC exists for every 14 subcarriers. As a result, there are four pilot subcarriers PSC0 to PSC3.

  Assuming that the frequencies of 52 subcarriers are f-26 to f26 excluding f0, pilot subcarriers PSC0 to PSC3 have frequencies f-21, f-7, f7, and f21, respectively, and subcarriers SC0 to SC4. , SC6 to SC18, SC20 to SC25, SC27 to SC32, SC34 to SC46, SC48 to SC52 have frequencies f-26 to f-22, f-20 to f-8, f-6 to f-1, and f1, respectively. To f6, f8 to f20, and f22 to f26.

  Each of pilot subcarriers PSC0 to PSC3 is a signal having a constant amplitude, and includes a plurality of symbols in the time direction. Further, the four pilot subcarriers PSC0 to PSC3 have known phases. The channel estimator 110 shown in FIG. 1 knows in advance the complex amplitudes of the four pilot subcarriers PSC0 to PSC3, that is, the amplitude and phase.

  Channel estimator 110 shown in FIG. 1 detects four pilot subcarriers PSC0 to PSC3 based on the received signal received from FFT 90, and detects the complex amplitudes of the detected four pilot subcarriers PSC0 to PSC3 in advance. The propagation path fluctuations HPSC0 to HPSC3 in each subcarrier are estimated using the known complex amplitude. Channel estimator 110 then determines the propagation path fluctuations in subcarriers SC0 to SC4, SC6 to SC18, SC20 to SC25, SC27 to SC32, SC34 to SC46, and SC48 to SC52 based on the estimated propagation path fluctuations HPSC0 to HPSC3. The estimation results HSC0 to HSC4, HSC6 to HSC18, HSC20 to HSC25, HSC27 to HSC32, HSC34 to HSC46, and HSC48 to HSC52 are temporarily interpolated so as to be linearly arranged between the two pilot subcarriers.

  More specifically, channel estimator 110 is arranged so that propagation path fluctuation estimation results HSC0 to HSC4 of subcarriers SC0 to SC4 are linearly aligned with the phase of estimation result HPSC0 of pilot subcarrier PSC0. The primary interpolation is performed, and the channel fluctuation estimation results HSC6 to HSC18 of the subcarriers SC6 to SC18 are between the channel fluctuation estimation result HPSC0 of the pilot subcarrier PSC0 and the channel fluctuation estimation result HPSC1 of the pilot subcarrier PSC1. Linear interpolation is performed so that the lines are linearly arranged. The channel estimator 110 similarly applies to the estimation results HSC20 to HSC25, HSC27 to HSC32, HSC34 to HSC46, and HSC48 to HSC52 of the propagation path fluctuations of the subcarriers SC20 to SC25, SC27 to SC32, SC34 to SC46, SC48 to SC52. Perform primary interpolation.

  The channel estimator 110 then estimates the propagation fluctuations HPSC0 to HPSC3 of the pilot subcarriers PSC0 to PSC3, and subcarriers SC0 to SC4, SC6 to SC18, SC20 to SC25, SC27 to SC32, SC34 to SC46 that have undergone primary interpolation. , SC48 to SC52, the channel fluctuation estimation results HSC0 to HSC4, HSC6 to HSC18, HSC20 to HSC25, HSC27 to HSC32, HSC34 to HSC46, and HSC48 to HSC52 are output to the demodulator 120.

  FIG. 6 is a flowchart for explaining reception signal reception processing in adaptive array antenna reception apparatus 100 shown in FIG. When a series of operations is started, array antenna 10 receives a transmission signal including a plurality of data sections (symbols SYM1 to SYMn) by M antenna elements 1 to M (step S1), and the received plurality of received antennas. Received signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2),..., RS_1 (n) to RS_M (n) are sequentially output to the buffer 20.

  The buffer 20 receives the first data section among the received signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2),..., RS_1 (n) to RS_M (n). The signals RS_1 (1) to RS_M (1) are output to the multipliers 31 to 3M and to the tail detector 50, respectively.

Thereafter, multipliers 31 to 3M multiply initial values w ₁ (0) to w _M (0) of _M weights received from weight controller 70 and reception signals RS_1 (1) to RS_M (1), respectively. The multiplication results RS_1 (1) * w ₁ (0) to RS_M (1) * w _M (0) are output to the adder 40. The adder 40 adds the multiplication results RS_1 (1) * w ₁ (0) to RS_M (1) * w _M (0) to generate a combined output signal RS (0) and outputs it to the head detector 60. The head detector 60 detects the head signal RSh (0) from the combined output signal RS (0) and outputs it to the weight controller 70.

  Further, the tail detector 50 detects the tail signals RSt_1 (1) to RSt_M (1) based on the reception signals RS_1 (1) to RS_M (1), and outputs them to the weight controller 70. Accordingly, the head signal RSh (0) and the M tail signals RSt_1 to RSt_M are detected based on the reception signals RS_1 (1) to RS_M (1) of the first data section among the plurality of data sections ( Step S2).

Thereafter, the weight controller 70 sets i = 1 (step S3), M tail signals RSt_1 (1) to RSt_M (1), M weights w ₁ (0) to w _M (0), and so on. Is calculated. Then, the weight controller 70 has a plurality of weights w ₁ (i) to so that the square error between the calculated weighting calculation result and the head signal RSh (i−1) (= RSh (0)) is minimized. w _M (i) is calculated (step S4), and the calculated plurality of weights w ₁ (i) to w _M (i) are output to multipliers 31 to 3M, respectively.

Multipliers 31 to 3M respectively multiply M weights w ₁ (i) to w _M (i) received from weight controller 70 and reception signals RS_1 (1) to RS_M (1), and the multiplication results. RS_1 (1) * w ₁ (i) to RS_M (1) * w _M (i) are output to the adder 40. The adder 40 adds the multiplication results RS_1 (1) * w ₁ (i) to RS_M (1) * w _M (i), generates a combined output signal RS (i), and outputs it to the head detector 60. The head detector 60 detects the head signal RSh (i) from the combined output signal RS (i) and outputs it to the weight controller 70.

As a result, a combined output signal RS (i) is generated using the plurality of weights w ₁ (i) to w _M (i) and the received signals RS_1 (1) to RS_M (1), and the generated combined output is generated. A head signal RSh (i) is detected from the signal RS (i) (step S5).

  Thereafter, the wait controller 70 determines whether i = i_std (step S6), and if i = i_std is not satisfied, sets i = i + 1 (step S7).

And a series of operation | movement returns to step S4, and step S4-step S7 mentioned above are repeatedly performed until it determines with it being i = i_std in step S6. Thereafter, when it is determined in step S6 that i = i_std, the weight controller 70 determines that the plurality of weights w ₁ (i) to w _M (i) are optimized (step S8). The weights w ₁ (i_std) to w _M (i_std) are output to the multipliers 31 to 3M, respectively.

After the weight controller 70 determines that the plurality of weights w ₁ (i) to w _M (i) have been optimized, the buffer 20 detects that the predetermined time Tconst has elapsed, and receives the received signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2),..., RS_1 (n) to RS_M (n) are sequentially output to multipliers 31 to 3M, respectively.

The multipliers 31 to 3M respectively receive the received signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2),..., RS_1 (n) to RS_M (n). The weights w ₁ (i_std) to w _M (i_std) are multiplied, and the multiplication results RS_1 (1) * w ₁ (i_std) to RS_M (1) * w _M (i_std), RS_1 (2) * w ₁ ( i_std) to RS_M (2) * w _M (i_std),..., RS_1 (n) * w ₁ (i_std) to RS_M (n) * w _M (i_std) are sequentially output to the adder 40.

The adder 40 performs multiplication results RS_1 (1) * w ₁ (i_std) to RS_M (1) * w _M (i_std), RS_1 (2) * w ₁ (i_std) to RS_M (2) * w _M (i_std). ,..., RS_1 (n) * w ₁ (i_std) to RS_M (n) * w _M (i_std) are sequentially received, and the received multiplication results RS_1 (1) * w ₁ (i_std) to RS_M (1). * W _M (i_std), RS_1 (2) * w ₁ (i_std) to RS_M (2) * w _M (i_std),..., RS_1 (n) * w ₁ (i_std) to RS_M (n) * w _M (i_std) is sequentially added, and the combined output signals RS1 to RSn are sequentially output to the GI remover 80. In this case, the combined output signal RS1 is composed of the addition results of the multiplication results RS_1 (1) * w ₁ (i_std) to RS_M (1) * w _M (i_std), and the combined output signal RS2 is the multiplication result RS_1 (2). * W ₁ (i_std) to RS_M (2) * w _M (i_std) is added, and the combined output signal RSn is similarly multiplied by the multiplication result RS_1 (n) * w ₁ (i_std) to RS_M ( n) It consists of the addition result of * w _M (i_std).

  The GI remover 80 sequentially receives the combined output signals RS1 to RSn and sequentially removes the guard intervals (GI) from the received combined output signals RS1 to RSn. The GI remover 80 sequentially outputs the combined output signals RS1 to RSn from which the guard interval (GI) has been removed to the FFT 90, and the FFT 90 sequentially outputs the combined output signals RS1 to RSn received from the GI remover 80 at high speed. The Fourier transform is performed, and the fast Fourier transform combined output signals RS1 to RSn are output to the channel estimator 110 and the demodulator 120.

  Channel estimator 110 performs channel estimation (estimation of propagation path fluctuation in pilot subcarrier PSC and primary interpolation of subcarrier SC) based on the combined output signals RS1 to RSn received from FFT 90, and performs channel estimation. Is output to the demodulator 120.

  Demodulator 120 demodulates combined output signals RS1 to RSn based on combined output signals RS1 to RSn received from FFT 90 and the result of channel estimation received from channel estimator 110, and outputs a demodulated signal. As a result, the processing of the received signals in a plurality of data sections is completed using the optimized plurality of weights (step S9). And a series of operation | movement is complete | finished.

In the flowchart shown in FIG. 6, the wait controller 70, the weight _w 1 (i) _~w weights when the number of preferred process of M (i) has reached the reference number i_std _w 1 (i) ~w _M Although it has been described that (i) is determined to be optimized, in the present invention, the weight controller 70 is not limited to this, and the weight controller 70 determines the power PWh (i) of the head signal RSh (i) and the power PWt of the combined tail signal RSt. May be determined that the weights w ₁ (i) to w _M (i) are optimized.

  FIG. 7 is another flowchart for explaining reception signal reception processing in adaptive array antenna reception apparatus 100 shown in FIG. The flowchart shown in FIG. 7 is the same as the flowchart shown in FIG. 6 except that step S6 of the flowchart shown in FIG. 6 is replaced with steps S5A to S5D.

  When a series of operations is started and the above-described steps S1 to S5 are sequentially executed, the weight controller 70 detects the power PWt of the combined tail signal RSt (step S5A), and the power of the head signal RSh (i). PWh (i) is detected (step S5B).

  Then, the weight controller 70 calculates an error ΔPW between the power PWh (i) and the power PWt (step S5C), and determines whether or not the error ΔPW is equal to or less than the threshold value PWth (step S5D).

  When it is determined in step S5D that the error ΔPW is not less than or equal to the threshold value PWth, step S7 described above is executed, and the series of operations returns to step S4. In step S5D, steps S4, S5, S5A to S5D, and S7 described above are repeatedly executed until it is determined that error ΔPW is equal to or smaller than threshold value PWth.

  Thereafter, when it is determined in step S5D that error ΔPW is equal to or smaller than threshold value PWth, steps S8 and S9 described above are sequentially executed, and a series of operations is completed.

In the above, it detects the head signal RSh and the M-tail signal RSt_1~RSt_M contained in one symbol SYM1--, the M-tail signal RSt_1~RSt_M and M-way and _w 1 and to w _M Although it has been described that the optimization process of the plurality of weights w _{1 to} w _M is repeatedly performed so that the square error between the weighted synthesis result and the head signal RSh is minimized, the present invention is not limited to this, and the time slot is not limited thereto. TSL preamble PRE may be using two signals included in (see FIG. 2) repeating preferred process of the plurality of weights w ₁ to w _M.

  The preamble PRE includes two signals SG1 and SG2 having the same waveform. When the buffer 20 receives the preamble PRE from the array antenna 10, the received signal SGR_1 of the received signals SGR_1 (1) to SGR_M (1) of the signal SG1 and the received signals SGR_1 (2) to SGR_M (2) of the signal SG2. (1) to SGR_M (1) are output to the tail detector 50, the reception signals SGR_1 (2) to SGR_M (2) are output to the multipliers 31 to 3M, respectively, and the reception signals SGR_1 (1) to SGR_M (1) are output. ), SGR_1 (2) to SGR_M (2) are held for a predetermined time Tconst.

Then, tail detector 50 outputs received signals SGR_1 (1) to SGR_M (1) received from buffer 20 to weight controller 70 as they are, and multipliers 31 to 3M receive received signals SGR_1 (2) to SGR_M ( 2) are multiplied by weights w ₁ (0) to w _M (0), respectively, and the multiplication results SGR_1 (2) * w ₁ (0) to SGR_M (2) * w _M (0) are output to the adder 40. . The adder 40 adds the multiplication results SGR_1 (2) * w ₁ (0) to SGR_M (2) * w _M (0) to generate a combined output signal SG2, and the head detection is performed on the generated combined output signal SG2. To the device 60. Then, the head detector 60 outputs the combined output signal SG2 received from the adder 40 to the weight controller 70 as it is.

The weight controller 70 synthesizes the signal SG1 based on the received signals SGR_1 (1) to SGR_M (1) received from the tail detector 50 so that the square error between the signals SG1 and SG2 is minimized. The weights w _{1 to} w _M are repeatedly optimized.

The operation in which the weight controller 70 repeatedly performs the optimization process of the plurality of weights w _{1 to} w _M based on the two signals SG1 and SG2 included in the preamble PRE is performed according to the flowchart shown in FIG. 6 or the flowchart shown in FIG. It is.

In the present invention, weight controller 70 preferably optimizes a plurality of weights w _{1 to} w _M based on two signals SG1 and SG2 included in preamble PRE, and a head signal included in symbol SYM1. Both the optimization processing of the plurality of weights w _{1 to} w _M based on RSh and M tail signals RSt_1 to RSt_M is performed.

[Embodiment 2]
FIG. 8 is a schematic block diagram showing a configuration of an adaptive array antenna receiving apparatus according to the second embodiment. Adaptive array antenna receiving apparatus 100A according to the second embodiment replaces weight controller 70 and channel estimator 110 of adaptive array antenna receiving apparatus 100 shown in FIG. 1 with weight controller 70A and channel estimator 110A, respectively, and detects interference waves. The other components are the same as those of the adaptive array antenna receiving apparatus 100.

  In adaptive array antenna receiving apparatus 100A, FFT 90 adds combined output signals RS1 to RSn obtained by fast Fourier transform to channel estimator 110A and demodulator 120 and also outputs to interference wave detector 130.

  The interference wave detector 130 determines that the interference wave is superimposed on the combined output signals RS1 to RSn based on the complex amplitude variation of the pilot subcarrier PSC included in the combined output signals RS1 to RSn, or the interference wave is combined output. It is detected that the signals RS1 to RSn are removed. That is, when the instantaneous fluctuation amount of the complex amplitude of the pilot subcarrier PSC included in the combined output signals RS1 to RSn is greater than or equal to a certain level, the interference wave detector 130 generates and / or disappears an interference wave at that time. Estimated.

  When detecting the generation and / or disappearance of the interference wave, the interference wave detector 130 generates a signal SGIF indicating that the interference wave has been generated and / or disappeared, and outputs the signal SGIF to the weight controller 70A and the channel estimator 110A. To do.

When the weight controller 70A receives the signal SGIF from the interference wave detector 130, the weight controller 70A uses the symbols at the time when the generation and / or extinction of the interference wave occurs according to the above-described method to select a plurality of weights w _{1 to} w _M. Repeat the process. When channel estimator 110A receives signal SGIF from interference wave detector 130, channel estimator 110A performs channel estimation using the symbol at the time when the generation and / or extinction of the interference wave occurs by the method described above.

As described above, the weight controller 70A repeatedly performs optimization processing of the plurality of weights w _{1 to} w _M using the symbol at the time when the generation and / or disappearance of the interference wave occurs using the signal SGIF as a trigger, and performs channel estimation. Unit 110A performs channel estimation using signal SGIF as a trigger.

FIG. 9 is a diagram for explaining the timing at which interference waves are generated and / or disappear. As described in the first embodiment, a plurality of weights w _{1 to} w _M are optimized based on the head signal RSh and the tail signal RSt of the symbol SYM1 included in the payload PLD of the time slot TSL, and the optimized When middle interference wave IFR doing the reception processing of the data included in the symbol SYM1~SYMn using a plurality of weights _w 1 to w _M is detected, a plurality of weights _w 1 to w _M was already optimized Thus, the symbol SYM cannot be accurately received (see (a) of FIG. 9).

Further, as described in the first embodiment, based on the head signal RSh and the tail signal RSt of the symbol SYM1 included in the payload PLD of the time slot TSL, a plurality of weights w ₁ to w ₁ in a state where the interference wave IFR is superimposed. If the optimize w _M, the interference wave IFR while you are performing reception processing of the data included in the symbol SYM1~SYMn disappears using a plurality of weights w ₁ to w _M that its optimization, already optimized When the plurality of weights w _{1 to} w _M are used, it is not possible to perform an optimal reception process of the symbol SYM (see FIG. 9B).

Furthermore, as described in the first embodiment, based on the head signal RSh of the symbol SYM1 and the synthesized tail signal RSt included in the payload PLD of the time slot TSL, a plurality of weights w ₁ in a state where the interference wave IFR1 is superimposed. interference with optimizing to w _M, a new interference wave IFR2 occurs during that performs reception processing of data included in the symbol SYM1~SYMn using a plurality of weights _w 1 to w _M that the optimized When IFR1 disappears, the symbol SYM cannot be accurately received using a plurality of already optimized weights w _{1 to} w _M (see FIG. 9C).

Therefore, in the second embodiment, as shown in FIGS. 9A to 9C, when the occurrence and / or disappearance of the interference wave IFR is detected, a plurality of weights w _{1 to} w _M are optimized. I decided to start over.

  FIG. 10 is a flowchart for explaining reception signal reception processing in adaptive array antenna reception apparatus 100A shown in FIG. The flowchart shown in FIG. 10 is the same as the flowchart shown in FIG. 6 except that steps S10 and S11 are added to the flowchart shown in FIG.

  When the above-described steps S1 to S9 are sequentially executed, the interference wave detector 130 generates the signal SGIF and outputs the signal SGIF to the weight controller 70A when the generation and / or disappearance of the interference wave is detected by the above-described method. To do. Then, the weight controller 70A determines whether or not the interference wave is generated and / or extinguished depending on whether or not the signal SGIF is received from the interference wave detector 130 (step S10).

  When it is determined in step S10 that the interference wave has been generated and / or disappeared, the series of operations returns to step S3, and the above-described steps S3 to S10 are sequentially executed. In this case, when channel estimator 110A receives signal SGIF from interference wave detector 130, channel estimator performs channel estimation again by the method described above and outputs the result of channel estimation to demodulator 120 in step S9.

  On the other hand, when it is determined in step S10 that an interference wave has not occurred and / or disappeared, processing of received signals in a plurality of data sections is continued using a plurality of optimized weights (step S11). And a series of operation | movement is complete | finished.

  FIG. 11 is another flowchart for explaining reception signal reception processing in adaptive array antenna reception apparatus 100A shown in FIG. The flowchart shown in FIG. 11 is obtained by adding steps S10 and S11 to the flowchart shown in FIG. 7, and is otherwise the same as the flowchart shown in FIG.

  When the above-described steps S1 to S5, S5A to S5D, and S7 to S9 are sequentially executed, steps S10 and S11 described in FIG. 10 are sequentially executed. And a series of operation | movement is complete | finished.

Thus, in the second embodiment, a plurality of weights w ₁ in addition to the preferred process of to w _M, a plurality of weights w ₁ when the occurrence of interference waves and / or disappearance of when receiving timeslots TSL It repeats the preferred process of to w _M.

  Therefore, according to the present invention, interference signals are superimposed on the received signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2),..., RS_1 (n) to RS_M (n) or The reception signal RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2),..., RS_1 (n) to RS_M (n) also when the interference wave is removed. From RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2), ..., RS_1 (n) to RS_M (n), the signal power to interference power ratio or signal power to noise power ratio is maximized Then, reception processing of the reception signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2),..., RS_1 (n) to RS_M (n) can be performed.

  Others are the same as in the first embodiment.

In the above description, among the plurality of symbols SYM1 to SYMn included in the payload PLD, the head signal RSh and M tail signals RSt_1 to RSt_M included in the first symbol SYM1 are detected, and M tail signals RSt_1 to RSt_1 are detected. Although it has been described that the optimization process of the plurality of weights w _{1 to} w _M is repeatedly performed so that the square error between the weighted synthesis result of RSt_M and M weights w _{1 to} w _M and the head signal RSh is minimized. In the present invention, the head signal RSh and M tail signals RSt_1 to RSt_M included in any one symbol SYMj (1 ≦ j ≦ n) of the plurality of symbols SYM1 to SYMn are detected. and, with the weight of the M pieces of the tail signal RSt_1~RSt_M and M weights _w 1 ~w _M And combining the results may be repeated performing suitable processing of a plurality of weights w ₁ to w _M as square errors between the head signal RSh is minimized.

Further, in the above, the head signal RSh and M tail signals RSt_1 to RSt_M included in one symbol SYMj among the plurality of symbols SYM1 to SYMn included in the payload PLD are detected, and M tail signals RSt_1 to RSt_1 are detected. Although it has been described that the optimization process of the plurality of weights w _{1 to} w _M is repeatedly performed so that the square error between the weighted synthesis result of RSt_M and M weights w _{1 to} w _M and the head signal RSh is minimized. In the present invention, the head signals RSh and M included in two symbols SYMj and SYMk (k = j + α, α is a positive integer) among the plurality of symbols SYM1 to SYMn included in the payload PLD are not limited thereto. M tail signals RSt_1 to RSt_M are detected and M tail signals RSt_1 to RSt are detected. The optimization process for the plurality of weights w _{1 to} w _M may be repeatedly performed so that the square error between the weighted combination result of _M and M weights w _{1 to} w _M and the head signal RSh is minimized. Good.

In this case, weight controllers 70 and 70A detect head signal RSh and M tail signals RSt_1 to RSt_M included in symbol SYMj, M tail signals RSt_1 to RSt_M, and M weights w _{1 to} w _M. A process A for optimizing a plurality of weights w _{1 to} w _M so that a square error between the weighted synthesis result of the head signal RSh and the head signal RSh is minimized, and the head signals RSh and M of the symbols SYMk The tail signals RSt_1 to RSt_M are detected, and a plurality of weights are provided so that a square error between the weighted synthesis result of the _M tail signals RSt_1 to RSt_M and the M weights w _{1 to} w _M and the head signal RSh is minimized. The process B for performing the optimization process of w _{1 to} w _M is sequentially repeated.

Further, in the above, the optimization process of the plurality of weights w _{1 to} w _M is performed based on the head signal RSh and the tail signal RSt included in the symbol SYM or the two SG1 and SG2 included in the preamble PRE of the time slot TSL. Although it has been described that it is repeated, the present invention is not limited to this, and as long as two signals have the same waveform, a plurality of weights w _{1 to} w _M are preferable based on two signals having any same waveform. The conversion process may be repeated.

Further, the reference number i_std may be determined according to the radio wave environment around the adaptive array antenna receiving apparatuses 100 and 100A. This is because the degree of superimposition of the interference wave IFR differs depending on the radio wave environment, and the degree of optimization of the plurality of weights w _{1 to} w _M differs.

Furthermore, in the present invention, the square error between the head signal RSh and the combined tail signal RSt generated by weighted combining of the _M tail signals RSt_1 to RSt_M and the M weights w _{1 to} w _M is minimized. M weights w _{1 to} w _M may be repeatedly performed, and M weights w ₁ to w so that the square error between the M tail signals RSt_1 to RSt_M and the head signal RSh is minimized. preferred treatment of w _M may be repeatedly performed.

  In the present invention, the plurality of tail signals RSt_1 to RSt_M constitute a “first signal received signal”, and the head signal RSh constitutes a “second signal received signal”.

  The combined output signal SG2 forms a “desired wave of a known received signal”, and each of the combined output signals RS (1) to RS (n) forms a “combined received signal”.

Further, the received signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2),..., RS_1 (n) to RS_M (using the optimized weights w _{1 to} w _M The multipliers 31 to 3M, the adder 40, the GI remover 80, the FFT 90, the channel estimator 110, and the demodulator 120 that perform the reception processing of n) constitute “signal processing means”.

Further, the received signals RS_1 (1) to RS_M (1), RS_1 (2) to RS_M (2),..., RS_1 (n) to RS_M (using the optimized weights w _{1 to} w _M The multipliers 31 to 3M, the adder 40, the GI remover 80, the FFT 90, the channel estimator 110A, and the demodulator 120 that perform the reception processing of n) constitute “signal processing means”.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

  The present invention is applied to an adaptive array antenna receiving apparatus that completes weight optimization by the time reception processing is started.

It is a schematic block diagram which shows the structure of the adaptive array antenna receiver by Embodiment 1 of this invention. It is a block diagram of the time slot which shows the unit of the data made into the reception object by the adaptive array antenna receiver shown in FIG. FIG. 3 is a conceptual diagram showing one symbol shown in FIG. 2. It is a figure for demonstrating the optimization method of M weight. It is a timing chart of a pilot subcarrier. 6 is a flowchart for explaining reception signal reception processing in the adaptive array antenna reception apparatus shown in FIG. 1. 6 is another flowchart for explaining reception signal reception processing in the adaptive array antenna receiver shown in FIG. 1. 6 is a schematic block diagram showing a configuration of an adaptive array antenna receiving apparatus according to Embodiment 2. FIG. It is a figure for demonstrating the generation | occurrence | production and / or disappearance of an interference wave. FIG. 9 is a flowchart for explaining reception signal reception processing in the adaptive array antenna reception apparatus shown in FIG. 8. FIG. FIG. 10 is another flowchart for explaining reception signal reception processing in the adaptive array antenna reception apparatus shown in FIG. 8. FIG.

Explanation of symbols

  1 to M antenna element, 10 array antenna, 20 buffer, 31 to 3M multiplier, 40 adder, 50 tail detector, 60 head detector, 70 weight controller, 80 GI remover, 90 FFT, 100, 100A adaptive Array antenna receiver, 110, 110A channel estimator, 120 demodulator, 130 interference wave detector.

Claims (3)

An adaptive array antenna receiving apparatus for receiving a transmission signal including a plurality of data sections in which transmission data is stored,
An array antenna for receiving the transmission signal by a plurality of antenna elements;
A buffer for holding a plurality of received signals of a plurality of data included in the plurality of data sections for a certain period of time;
A first detection for receiving, from the buffer, a reception signal first received by the array antenna among the plurality of reception signals, and detecting a plurality of tail signals from a plurality of data reception signals constituting the received signal. And
The plurality of data reception signals are respectively multiplied by a plurality of weights for generating a combined reception signal in which the signal power to interference power ratio or the signal power to noise power ratio is maximized from the plurality of reception signals, and the plurality A second detector for detecting a head signal from a combined signal obtained by adding the multiplication results of
A plurality of tail signals detected by the first detector are combined to generate a combined tail signal having the same waveform as the head signal detected by the second detector, and the generated combined tail signal and the A weight controller for optimizing the plurality of weights by performing a optimization process for calculating the plurality of weights so that a square error with a head signal is minimized until the predetermined time elapses ;
When the predetermined time has elapsed, receiving the plurality of received signals from the buffer, using a plurality of weights that are optimized by the weight controller processes the received signals of the multiple signal processing for outputting the demodulated signal Means and
The weight controller, the repeated only reference number of the preferred process the same signal interval corresponding to the interval of the plurality of data reception signal, that to optimize the plurality of weights, adaptive array antenna receiving apparatus. The transmission signal further includes a preamble for adjusting reception characteristics in the array antenna;
2. The adaptive array antenna receiving apparatus according to claim 1, wherein the weight controller repeatedly performs the optimization process using received signals of two signals having the same waveform included in the preamble and the plurality of data received signals. 3. . An interference wave detector for detecting at least one of generation of interference waves with respect to the plurality of received signals and extinction of the interference waves;
3. The weight controller according to claim 1, wherein when the interference wave detector detects at least one of the generation of the interference wave and the disappearance of the interference wave, the weight controller repeatedly performs the optimization process. 4. Adaptive array antenna receiver.

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