JP4742835B2 - LIGHT EMITTING DEVICE AND ELECTRONIC DEVICE - Google Patents

Description

The present invention relates to a light emitting device having an organic EL element protected by a thin film sealing structure and an electronic apparatus having the same.

As a kind of light-emitting element, organic electroluminescence that emits light when excited by an electric field (
EL) elements are known. In a manufacturing process of a device including an organic EL element, sealing is performed to prevent the organic EL element from being deteriorated by oxygen, moisture, or the like. As this sealing technology,
There is known a thin film sealing technique in which an extremely thin inorganic film is used as a gas barrier layer to cover an organic EL element (Patent Documents 1 to 4).

JP-A-9-185994 Japanese Patent Laid-Open No. 2001-284041 JP 2000-223264 A JP 2003-17244 A

In many cases, not only pixel circuits corresponding to each of the organic EL elements but also peripheral circuits that generate signals related to driving or inspection of the pixel circuits are arranged on the substrate on which the organic EL elements are arranged. In such a device, in order to reduce the size of the substrate, it is desirable that the distance between the light emitting region provided with the pixel circuit and the peripheral circuit is small. Also, the peripheral circuit on the substrate is usually a transistor,
It is preferable that the performance can be prevented from deteriorating due to separation of components such as hydrogen from the transistor. Therefore, it is conceivable to extend the gas barrier layer contributing to sealing not only to the light emitting region but also to the peripheral circuit region.

However, since the gas barrier layer used for sealing the thin film is dense to block small molecules of water vapor or air, stress concentration is likely to occur due to a step or a sudden shape change. When the area of the peripheral circuit is covered with a gas barrier layer, the gas barrier layer is bent due to a step or unevenness that may be caused by the peripheral circuit, and stress is concentrated on the bent portion, which is easily damaged. .

Therefore, the present invention protects not only the pixel circuit but also the peripheral circuit with a gas barrier layer,
Provided are a light-emitting device capable of suppressing stress concentration on a part of a gas barrier layer, and an electronic apparatus having the same.

A light-emitting device according to the present invention includes a plurality of pixel circuits provided in a light-emitting region on a substrate, and each of the plurality of pixel circuits includes an organic EL element, and the organic EL element includes a first electrode and a second electrode. A light-emitting device having an electrode and a light-emitting layer sandwiched between the first electrode and the second electrode, disposed outside the light-emitting region on the substrate, for driving or inspecting the plurality of pixel circuits A peripheral circuit for generating a related signal; an electrode protective film covering each of the organic EL elements and the peripheral circuit so as to cover the light emitting region and the peripheral circuit; and the organic EL element sandwiching the electrode protective film And a first surface opposite to the electrode protection film and a second surface opposite to the first surface, wherein the first surface is opposite to the peripheral circuit. The unevenness of the second surface rather than the unevenness of the first surface A planarizing film formed to be small, and a gas barrier layer covering the planarizing film and further shielding each of the organic EL elements from outside air, the planarizing film and the gas barrier layer being the peripheral It covers at least part of the circuit area.

According to the present invention, since the planarization film covers at least a part of the region of the peripheral circuit, the planarization film relaxes the step or unevenness that may be caused by the peripheral circuit, and the gas barrier layer that covers the planarization film By relaxing the bending angle, it is possible to suppress stress from being concentrated on a part of the gas barrier layer. Further, the peripheral circuit can be protected by a sealing structure having a gas barrier layer in addition to the electrode protective film. For example, when the planarizing film is manufactured from an organic compound, the electrode protective film can suppress deterioration of the peripheral circuit due to gas or impurities generated by the planarized film after manufacturing. The peripheral circuit referred to in this specification can include, for example, a drive circuit for driving a light emitting element, an inspection circuit for inspecting a light emitting element or a wiring, or the like.

It is preferable that the gas barrier layer is in direct contact with the electrode protective film outside the peripheral circuit on the substrate. According to this aspect, since the gas barrier layer is in direct contact with the electrode protective film outside the peripheral circuit, air or moisture from the outside is transferred to the planarization layer sandwiched between the gas barrier layer and the electrode protective film. Can be prevented. Further, even if a defect occurs in the electrode protective film, the gas barrier layer can prevent the sealing performance from being damaged by the defect of the electrode protective film in the portion where the gas barrier layer is in direct contact with the electrode protective film.

In this aspect, the second electrode is a common electrode provided in common to the plurality of light emitting elements, and a second electrode power line for supplying a potential to the second electrode is provided on the substrate. It is disposed on the outside of the peripheral circuits, at a position overlapping the second electrode power supply line, preferably wherein the gas barrier layer is in direct contact with the electrode protective film.

In order to prevent air from flowing into the planarization layer sandwiched between the gas barrier layer and the electrode protective film from the outside, it is preferable that the length of the portion where the gas barrier layer directly contacts the electrode protective film is larger.
However, when these direct contact portions are enlarged, there is a risk that the substrate must be enlarged. In this aspect, since the gas barrier layer is in direct contact with the electrode protective film at a position overlapping the second electrode power line, the gas barrier is only positioned outside the wide second electrode power line. Compared with the case where the layer is in direct contact with the electrode protective film, the area of the substrate can be reduced. Further, if the second electrode power line having a large width is disposed between the peripheral circuit and the light emitting region, the substrate may be forced to be enlarged because the distance between the light emitting region and the peripheral circuit is wide. is there. However, in this aspect, since the second electrode power line is disposed outside the peripheral circuit and overlaps the second electrode power line, the gas barrier layer is in direct contact with the electrode protective film. It doesn't have to be large. In addition, since the second electrode power line is often formed at a different height from the second electrode, the part that electrically connects the second electrode power line and the second electrode is connected to other parts. A step is likely to be generated, and a defect due to the step may occur in the electrode protective film. However, even if a defect due to such a step occurs in the electrode protective film, the gas barrier layer is in direct contact with the electrode protective film at a position overlapping the power supply line for the second electrode. The gas barrier layer can prevent the sealing performance from being impaired.

Preferably, the planarizing film has an inclined surface that is inclined with respect to the substrate by connecting the first surface and the second surface, and the inclined surface overlaps the peripheral circuit.

The inclined surface of the planarizing film of this aspect is more relaxed than the case where the first surface and the second surface are connected by a surface perpendicular to the substrate, so that the gas barrier layer covering the planarizing film can be relaxed by bending the gas barrier layer. The stress concentration in can be relaxed. The fact that the inclined surface of the planarizing film overlaps the peripheral circuit means that the planarizing film terminates at or near the peripheral circuit. In this case, the area occupied by the flattening film can be reduced compared to the case where the inclined surface of the flattening film is completely outside the peripheral circuit, so that the area of the substrate can be reduced. is there.

In this aspect, a circuit protective film that covers the peripheral circuit and seals the peripheral circuit, and is disposed on the opposite side of the peripheral circuit across the circuit protective film, and faces the circuit protective film And a circuit step flattening film having a surface opposite to the circuit protection film, and having a surface with a surface opposite to the circuit protection film, the surface having a surface unevenness smaller than that of the circuit protection film. The organic EL element is disposed on the opposite side of the circuit protective film across the circuit level flattening film, and includes a partition wall that defines the light emitting layer of each of the organic EL elements. A first region in which the partition wall and the circuit step flattening film overlap each other on the inner side of the substrate, and the outer side of the first region is formed on the outer side of the substrate. One of the partition wall and the circuit step planarizing film is formed. There is a second region, and there is a third region outside the partition wall and the circuit step planarization film, and the inclined surface of the planarization film is the first region, It is preferable that the second region overlaps with the third region and terminates in the third region.
In this aspect, there is a first region having a large height on the inner side on the substrate, a second region having a slightly lower height on the outer side, and a third region having a considerably lower height on the outer side. Due to the presence of the region, the height of the electrode protection film on the substrate can be gradually decreased from the inside toward the outside. In this state, the inclined surface of the planarizing film overlaps with the first region, the second region, and the third region, and terminates at the third region, so that the inclined surface of the planarizing film draws a gentle curve. Easy to form. For this reason, since the bending angle of the gas barrier layer covering the planarizing film is also relaxed, it is possible to suppress stress concentration on a part of the gas barrier layer.

An electronic apparatus according to the present invention includes the light emitting device described above. Examples of such electronic devices include personal computers, mobile phones, and portable information terminals in which a light emitting device is applied to a display device, and also irradiates light on an image carrier in an image printing apparatus using an electrophotographic method. As a printer head for forming a latent image, a light emitting device may be used.

Hereinafter, various embodiments according to the present invention will be described with reference to the accompanying drawings. In these drawings, the ratio of dimensions of each part is appropriately changed from the actual one.

<First Embodiment>
FIG. 1A is a schematic plan view showing a part of the configuration of the light emitting device 1 according to the first embodiment of the present invention, and FIG. 1B is an auxiliary wiring 150 after the state of FIG. FIG. 6 is a plan view showing a state where a pixel electrode 76 is further formed. As shown in FIG. 1A, the light emitting device 1 includes a panel 10 and a flexible substrate 20. Connection terminals are formed at the end of the panel 10,
This connection terminal and the connection terminal formed on the flexible substrate 20 are connected to an ACF (anisotropic).
The film is fixed by pressure through a film-like adhesive containing conductive particles called “conductive film”. The flexible substrate 20 is provided with a data line driving circuit 200, and various power supply voltages are supplied to the panel 10 through the flexible substrate 20.

The panel 10 is provided with a light emitting area A and a circuit area B outside the light emitting area A (that is, between the substrate or the outer periphery of the panel 10 and the light emitting area A). The circuit region B has a scanning line driving circuit 100A.
And 100B, and a precharge circuit 120 are formed. The precharge circuit 120 is a circuit for setting the potential of the data line 112 to a predetermined potential prior to the write operation. Scan line driving circuits 100A and 100B, and precharge circuit 120
Is a peripheral circuit around the light emitting region A. However, the peripheral circuit may include a unit circuit P and an inspection circuit (not shown) for inspecting the quality of the wiring, or may be a peripheral circuit in which the data line driving circuit 200 is provided in the circuit region B.

In the light emitting region A, a plurality of scanning lines 111 and a plurality of data lines 112 are formed, and a plurality of unit circuits (pixel circuits) P are provided in the vicinity of each of the intersections. Unit circuit P is O
It includes an LED (organic light emitting diode) element and receives power from the current supply line 113. The plurality of current supply lines 113 are connected to the first electrode power line 130.

FIG. 2 is a circuit diagram illustrating details of the unit circuit P of the light emitting device 1. Each unit circuit P includes an n-channel transistor 68, a p-channel transistor 60, a capacitor element 69, and an O
The LED element 70 is included. The source electrode of the p-channel transistor 60 is the current supply line 11.
3, while its drain electrode is connected to the anode of the OLED element 70. Also,
A capacitor 69 is provided between the source electrode and the gate electrode of the transistor 60. The gate electrode of the n-channel transistor 68 is connected to the scanning line 111, the source electrode is connected to the data line 112, and the drain electrode is connected to the gate electrode of the transistor 60.

In the unit circuit P, when the scanning line driving circuits 100A and 100B select the scanning line 111 corresponding to the unit circuit P, the transistor 68 is turned on, and the data signal supplied via the data line 112 is transferred to the internal capacitive element. 69. Then, the transistor 60 supplies a current corresponding to the level of the data signal to the OLED element 70. As a result, the OLED element 70 emits light with a luminance corresponding to the level of the data signal.

Further, as shown in FIG. 1A, the outer peripheral side of the circuit region B (that is, the substrate or panel 1).
A U-shaped second electrode power line 140 is formed between the outer periphery of 0 and the circuit region B). The second electrode power supply line 140 is a wiring for supplying a power supply voltage (Vss: ground level in this example) to the cathode (second electrode) of the OLED element as will be described later. The OLED element has a light emitting functional layer (including a light emitting layer) 74 sandwiched between a pixel electrode 76 (anode) and a common electrode 72 (cathode) (see FIG. 4). The common electrode 72 is formed over the light emitting region A and the circuit region B as shown in FIG. Also, the common electrode 72 and the second electrode power line 14
An auxiliary wiring 150 connecting 0 is formed in the circuit region B so as to cover the peripheral circuit. The auxiliary wiring 150 includes a first portion 150 a of the auxiliary wiring provided in the light emitting region A and a second portion 150 b of the auxiliary wiring provided in the circuit region B. In the light emitting area A, auxiliary wiring 1
The first portion 150a of the auxiliary wiring 150 is formed in a lattice shape so that the first portion 150a of the 50 and the pixel electrode 76 do not contact each other. That is, the first portion 150 a of the auxiliary wiring 150 is disposed between the OLED elements 70. The auxiliary wiring referred to in this specification is a conductor that overlaps and is electrically connected to the common electrode 72 and reduces the resistance of the common electrode 72. For clarity,
FIG. 3 is an enlarged view of a part of FIG.

The light emitting device 1 of this embodiment is configured in the form of top emission, and light from the light emitting functional layer 74 is emitted through the common electrode 72. The common electrode 72 is made of a transparent material. For this reason, the circuit area B cannot be shielded by the common electrode 72.
On the other hand, the auxiliary wiring 150 described above can be shielded by the auxiliary wiring 150 because a metal having conductivity and light shielding properties is used. Thereby, it can suppress that light injects into a peripheral circuit and a photocurrent generate | occur | produces. The auxiliary wiring 150 is formed in the same process as the pixel electrode 76 in the light emitting region A. Therefore, no special process is required to add light shielding properties to the circuit region B.

FIG. 4 shows a partial cross-sectional view of the light emitting device 1. In the figure, the OLED element 7 is located in the light emitting area A.
On the other hand, a scanning line driving circuit 100A as a peripheral circuit is formed in the circuit region B while 0 is formed. In the figure, the upper surface of the light emitting device 1 is an emission surface from which light is emitted. As shown in the figure, a base protective layer 31 is formed on a substrate 30, and transistors 40, 50, and 60 are formed thereon. Transistor 40 is an n-channel type, and transistors 50 and 60 are p-channel type. The transistors 40 and 50 are part of the scanning line driving circuit 100A, and the transistor 60 and the OLED element 70 are part of the unit circuit P.

The transistors 40, 50, and 60 are provided on a base protective layer 31 mainly composed of silicon oxide formed on the surface of the substrate 30. A silicon layer 40 is formed on the base protective layer 31.
1, 501 and 601 are formed. A gate insulating layer 32 is provided on the base protective layer 31 so as to cover the silicon layers 401, 501 and 601. The gate insulating layer 32 is made of, for example, silicon oxide. Of the upper surface of the gate insulating layer 32, silicon layers 401 and 501 are formed.
Gate electrodes 42, 52, and 62 are provided in a portion facing 601 and 601. In the transistor 40, the silicon layer 401 is doped with the group V element through the gate electrode 42, and the drain region 40c and the source region 40a are formed. Here, the region not doped with the group V element is the channel region 40b.

In the transistors 50 and 60, the silicon layer 5 is interposed through the gate electrodes 52 and 62.
01 and 601 are doped with group III elements through gate electrodes 52 and 62,
Drain regions 50a and 60a and source regions 50c and 60c are formed. Here, the regions not doped with the group III element are the channel regions 50b and 60b.
It becomes. The gate electrodes 42, 52, and 6 of the transistors 40, 50, and 60 are shown.
The scanning line 111 is formed at the same time as 2 is formed.

Gate insulating layer 3 is formed so that first interlayer insulating layer 33 covers gate electrodes 42, 52 and 62.
2 is formed on the upper layer. Silicon oxide or the like is used as a material for the first interlayer insulating layer 33. Furthermore, the silicon layers 401, 501, and the source electrodes 41, 51, and 63, the drain / source electrode 43, and the drain electrode 61 through the contact holes that open through the gate insulating layer 32 and the first interlayer insulating layer 33, and 601 is connected. Further, the second electrode power line 140, the data line 112, and the current supply line 113 are formed in the same process as these electrodes. These electrodes, the second electrode power line 140 and the like are formed of a material such as conductive aluminum.

The circuit protective film 34 includes source electrodes 41, 51 and 63, a drain / source electrode 43,
It is provided in the upper layer of the first interlayer insulating layer 33 so as to cover the drain electrode 61 and the second electrode power line 140. The circuit protective film 34 is formed of a material having a low gas permeability such as silicon nitride or silicon oxynitride. These silicon nitride and silicon oxynitride may be an amorphous material or may contain hydrogen. By the circuit protection film 34, the transistor 40,
Hydrogen desorption from 50 and 60 can be prevented. Note that the circuit protective film 34 may be formed under the source electrode or the drain electrode.

A circuit level flattening film 35 is provided on the circuit protective film 34. The circuit level difference flattening film 35 has an unevenness on the upper surface opposite to the circuit protection film 34 smaller than the unevenness on the lower surface facing the circuit protection film 34. That is, the circuit step flattening film 35 is used to flatten unevenness caused by the transistors 40, 50, 60, the scanning line 111, the data line 112, the current supply line 113, and the like. For example, an acrylic or polyimide organic polymer material is used as the material of the circuit level flattening film 35. In this case, a photosensitive material for patterning is mixed with an organic resin,
Similar to the photoresist, patterning may be performed by exposure. Alternatively, the circuit step flattening film 35 may be formed by chemical vapor deposition (CVD) from an inorganic material such as silicon oxide or silicon oxynitride, and the upper surface thereof may be flattened by etching or the like. When an inorganic material is formed by a chemical vapor deposition method, the film thickness is 1 μm or less and is almost uniform, so the upper surface is easily affected by the unevenness of the lower layer, while the organic resin is coated. Therefore, the film thickness can be increased to about 2 to 3 μm, and the upper surface thereof is hardly affected by the unevenness of the lower layer, so that it is suitable for the material of the circuit step flattening film 35. However, an inorganic material such as silicon oxide or silicon oxynitride can be used for the circuit step flattening film 35 as long as a certain degree of unevenness is allowed.

On the circuit level difference planarizing film 35, the pixel electrode 76 (first electrode) and the first portion 150a of the auxiliary wiring are formed in the light emitting region A, and at the same time, the second portion 150b of the auxiliary wiring is formed in the circuit region B. That is, the pixel electrode 76 and the auxiliary wiring 150 are simultaneously formed in the same layer using the same material. In this embodiment, the pixel electrode 76 is an anode of the OLED element 70 and is connected to the drain electrode 61 of the transistor 60 through a contact hole that penetrates the circuit step flattening film 35 and the circuit protection film 34. The material of the pixel electrode 76 that is an anode is preferably a material having a high work function, and for example, nickel, gold, platinum, or an alloy thereof is preferable. Since these materials have reflectivity, the light emitted from the light emitting functional layer 74 is reflected toward the common electrode 72. In the circuit region B, the auxiliary wiring 150 is connected to the second electrode power line 140 through a contact hole formed in the circuit protection film 34.

Next, the partition wall 37 is formed. The partition 37 insulates between the pixel electrode 76 and the common electrode 72 (second electrode) formed thereafter, or between the plurality of pixel electrodes 76.
By providing the partition wall 37, each pixel electrode 76 can be controlled independently, and each of the plurality of light emitting elements can emit light with a predetermined luminance. For example, acrylic or polyimide is a material for the partition wall 37. In this case, a photosensitive material may be mixed for patterning and patterned by exposure in the same manner as the photoresist. A contact hole CH is formed in the partition wall 37 at the same time. In the light emitting region 37, the first portion 150a of the auxiliary wiring 150 and a common electrode 72 described later are connected through the contact hole CH. Also,
The same layer as the partition wall 37 is not provided on the second portion 150 b of the auxiliary wiring 150 in the circuit region B.

Next, a light emitting functional layer 74 including at least a light emitting layer is formed on the pixel electrode 76. An organic EL material is used for the light emitting layer. The organic EL material may be a low molecular material or a high molecular material. As another layer constituting the light emitting functional layer 74, a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, a hole block layer, and a part or all of the electron block layer may be provided. .

Next, the common electrode 72 (second electrode) is formed so as to cover the auxiliary wiring 150 and the light emitting functional layer 74 over the light emitting region A and the circuit region B. The common electrode 72 is transparent and OL
Light from the ED element 70 passes through the common electrode 74 and is emitted in the upper direction in the figure. In order for the common electrode 72 of this embodiment to function as the cathode of all OLED elements 70, the common electrode 72 is formed of a material having a low work function so that electrons can be easily injected. For example,
Aluminum, calcium, magnesium, lithium, etc., and alloys thereof. In addition, it is desirable that this alloy uses a material having a low work function and a material capable of stabilizing the material. For example, an alloy of magnesium and silver is suitable. When these metals or alloys are used for the common electrode 72, the thickness may be reduced in order to obtain translucency.

The common electrode 72 (second electrode) includes a material having a low work function, or a first layer made of a material having a low work function and a material that stabilizes the material, and ITO (indium tin oxi).
de), IZO (indium zinc oxide), or a light-transmitting and conductive second layer made of an oxidized conductive material such as ZnO ₂ , and the first layer is provided on the light emitting functional layer side. There may be. An oxidized conductive material such as ITO, IZO, or ZnO ₂ is a dense material and has a low gas permeability. If the common electrode 72 is formed of such a material, the common electrode 72 is formed over the light emitting region A and the circuit region B. Therefore, the unit circuit P in the light emitting region A and the peripheral circuits in the circuit region B emit light that will be described later. It is protected from the gas or outside air generated in the element leveling flattening film 82, and their deterioration is suppressed. Thus, if the common electrode 72 (second electrode) includes the second layer, the common electrode 72 is superior in light transmittance and conductivity as compared with the material forming the first layer. The power supply impedance of 72 can be greatly reduced, and the light extraction efficiency from the light emitting functional layer can be improved. The common electrode 72 (second electrode) includes a first layer made of a material having a low work function, a material that stabilizes the material, and a second layer made of the above-described oxidized conductive material. Thus, it is possible to prevent the first layer and the second layer from reacting and deteriorating the electron injection efficiency.

Prior to the formation of the common electrode 72, the contact hole CH is formed in the partition wall 37. The first portion 1 of the auxiliary wiring in the light emitting region 37 through the contact hole CH
50a and the common electrode 72 are connected. By connecting the common electrode 72 to the first portion 150a (see FIG. 1B) of the auxiliary wiring formed in a lattice shape in the light emitting region A, the power source impedance of the common electrode 72 can be greatly reduced. . In addition, since the second portion 150b of the auxiliary wiring is not covered with the partition wall 37 in the circuit region B, the common electrode 72 is used.
The contact resistance can be lowered because of the surface contact with a large area. Therefore, the power supply impedance can be greatly reduced.

Next, an electrode protective film 80 is formed so as to cover the common electrode 72. Similar to the circuit protective film 34, the electrode protective film 80 is formed of an inorganic material having a low gas permeability such as silicon nitride or silicon oxynitride. These silicon nitride and silicon oxynitride may be an amorphous material or may contain hydrogen. Further, a light emitting element step flattening film 82 is formed so as to cover the electrode protective film 80. The light-emitting element step planarizing film 82 is a layer formed such that the unevenness on the surface opposite to the electrode protective film 80 is smaller than the unevenness on the surface facing the electrode protective film 80, that is, the contact hole CH, partition wall 37 is a film for flattening the step formed in the OLED element 70 and the OLED element 70. Similarly to the circuit level flattening film 35, the light emitting element leveling flattened film 82 may be formed by vapor deposition from an inorganic material such as silicon oxide, and the upper surface thereof may be flattened by etching or the like. For the same reason as described above, it is preferable to form the light emitting element step flattening film 82 with an organic compound such as urethane, acrylic, epoxy, or cyanoacrylate. Further, it is preferable to form the light emitting element step flattening film 82 with an organic compound having a thermal expansion coefficient similar to that of the partition wall 37 so that a gas barrier layer 84 described later is not broken even if the partition wall 37 expands and contracts due to temperature. When an organic compound is used as the light emitting element step planarizing film 82, gas or impurities generated by the light emitting element step planarizing film 82 may be penetrated into the lower layer during or after curing. 80 to prevent this, OL
The lifetime of the ED element 70 can be prevented from being lowered.

In addition, a gas barrier layer 84 is formed so as to cover the light emitting element step flattening film 82. The material of the gas barrier layer 84 is formed of an inorganic material having a low gas permeability such as silicon nitride or silicon oxynitride. These silicon nitride and silicon oxynitride may be an amorphous material or may contain hydrogen. The gas barrier layer 84 is formed as a thin film having high density and high hardness by high density plasma vapor deposition. The gas barrier layer 84 prevents outside air and moisture from entering the light emitting device 1. That is, the gas barrier layer 84 further shields each of the OLED elements 70 surrounded by the light emitting element step flattening film 82 and the electrode protection film 80 from the outside air. The light-emitting element leveling film 82 and the gas barrier layer 84 are formed of peripheral circuits (scanning line driving circuits 100A and 100B having transistors 40 and 50 and the precharge circuit 12).
The entire area 0) is covered.

As shown in FIG. 4, in the portion where the transistors 40 and 50 of the peripheral circuit are present and not present,
A height step or unevenness may occur on the upper surface of the circuit protection film 34. Also, in the transistors 40 and 50, the height of the elements varies, so that a height step or unevenness may occur on the upper surface of the circuit protection film 34. In this embodiment, since the circuit step planarizing film 35 covers the peripheral circuit region, the circuit step planarizing film 35 relaxes the step or unevenness that may be caused by the peripheral circuit. Is thin, it may not be possible to flatten such a step or unevenness. Auxiliary wiring 15 on circuit step planarizing film 35
0, the common electrode 72 and the electrode protection film 80 are formed to have a substantially uniform thickness by vapor deposition, and it is difficult to smooth such a step or unevenness.

However, in this embodiment, since the light emitting element step flattening film 82 covers the entire area of the peripheral circuit, the light emitting element step flattening film 82 relaxes the step or unevenness that may be caused by the peripheral circuit. Since the bending angle of the gas barrier layer 84 covering the element step planarizing film 82 is also relaxed, it is possible to suppress stress concentration on a part of the gas barrier layer 84. Further, the peripheral circuit can be protected by the sealing structure having the gas barrier layer 84 in addition to the electrode protective film 80. For example, when the light emitting element step planarizing film 82 is made of an organic compound, the peripheral circuit is deteriorated by the gas or impurities generated by the light emitting element step planarizing film 82 during or after curing. Can be suppressed.

As shown in FIG. 4, the gas barrier layer 84 is in direct contact with the electrode protection film 80 outside the peripheral circuit on the substrate 30. Therefore, air or moisture from the outside can be prevented from entering the light emitting element step flattening film 82 sandwiched between the gas barrier layer 84 and the electrode protective film 80. In addition, even if a defect occurs in the electrode protective film 80, the gas barrier layer 84 indicates that the sealing performance is impaired due to the defect in the electrode protective film 80 in the portion where the gas barrier layer 84 is in direct contact with the electrode protective film 80. Can be prevented.

In order to prevent air from flowing into the light emitting element step flattening film 82 sandwiched between the gas barrier layer 84 and the electrode protective film 80 from the outside, the length of the portion where the gas barrier layer 84 is in direct contact with the electrode protective film 80 Is more preferable as it is larger. However, when these direct contact parts are enlarged,
There is a risk that the substrate 30 must be enlarged. In this embodiment, as shown in FIG.
Since the gas barrier layer 84 is in direct contact with the electrode protection film 80 at a position where the common electrode 72 in the second electrode power supply line 140 overlaps with the portion in direct contact with the second electrode power supply line 140, the second width is increased. The gas barrier layer 84 is disposed only on the outer side of the electrode power line 140 at the electrode protective film 8.
Compared with the case of direct contact with 0, the area of the substrate 30 can be reduced. Also,
If the second electrode power line 140 having a large width is disposed between the peripheral circuit and the light emitting area A, the substrate 30 must be enlarged because the distance between the light emitting area A and the peripheral circuit is wide. There is a fear. However, in this embodiment, the gas barrier layer 84 is in direct contact with the electrode protection film 80 at a position where the second electrode power line 140 is disposed outside the peripheral circuit and overlaps the second electrode power line 140. Therefore, it is not necessary to make the substrate 30 too large. Furthermore, since the second electrode power line 140 is formed at a height different from that of the common electrode 72, the portion that electrically connects the second electrode power line 140 and the common electrode 72 is connected to other parts. A level difference may occur, and a defect due to the level difference may occur in the electrode protection film 80 accordingly. However, even if a defect due to such a step occurs in the electrode protection film 80, the gas barrier layer 84 is in direct contact with the electrode protection film 80 at a position overlapping the second electrode power line 140, so that the electrode protection The gas barrier layer 84 can prevent the sealing performance from being damaged by the defect of the film 80.

The light-emitting element step planarizing film 82 is an inclined surface that connects a large uneven surface (lower surface in the drawing) facing the electrode protective film 80 and a flat surface (upper surface in the drawing) opposite to the electrode protective film 80. 82a. In the light emitting element step flattening film 82, the light emitting element step flattening film 8 is formed by connecting the inclined surface 82a to the lower surface in the drawing and the upper surface in the drawing in a plane perpendicular to the substrate 30.
2 to relax the bending angle of the gas barrier layer 84 covering 2, and the stress concentration in the gas barrier layer 84 can be relaxed. The fact that the inclined surface 82a overlaps with the peripheral circuit means that the light emitting element step flattening film 82 terminates at or around the peripheral circuit. In this case,
Compared to the case where the inclined surface 82a is completely outside the peripheral circuit, the area occupied by the light-emitting element step planarizing film 82 can be reduced, so that the area of the substrate 30 can be reduced.

As shown in FIG. 4, there is a first region B1 in which a partition wall 37 and a circuit leveling flattening film 35 overlap each other in the circuit region B on the substrate 30, and there is no partition wall 37 on the outer side. There is a second region B2 in which the circuit level flattening film 35 is formed, and there is a third region B3 in which neither the partition wall 37 nor the circuit level flattening film 35 is formed. Accordingly, there is a first region B1 having a large height on the inner side in the circuit region B on the substrate, a second region B2 having a slightly lower height on the outer side, and a considerably lower height on the outer side. Due to the presence of the third region B3, the height of the electrode protection film 80 on the substrate can be gradually decreased from the inside toward the outside.

The inclined surface 82a of the light-emitting element step planarizing film 82 overlaps the first region B1, the second region B2, and the third region B3 and terminates in the third region B3. Inclined surface 8 of light-emitting element step planarizing film 82
2a overlaps the first region B1, the second region B2, and the third region B3 and terminates at the third region B3, so that the inclined surface 82 of the light emitting element step planarizing film 82 draws a gentle curve.
It is easy to form a. For this reason, since the bending angle of the gas barrier layer 84 covering the light emitting element step planarizing film 82 is also relaxed, it is possible to suppress stress from being concentrated on the bent portion of the gas barrier layer 84.
In particular, when the light emitting element step planarizing film 82 is formed by coating and solidifying a liquid organic compound having a high viscosity, the organic compound extends along the surface of the electrode protective film 80, and therefore, the light emitting element step planarizing film 82 is rapidly bent. Since it is easy to form the inclined surface 82a having no gas, the breakage of the gas barrier layer 84 can be suppressed.

FIG. 5 is a schematic plan view showing a part of the configuration of a light emitting device 1A according to a modification of the first embodiment of the present invention, and shows a state similar to FIG. In this modification, unlike the case of FIG. 1A, the second electrode power line 140 is formed in a short rectangle instead of a U-shape. Similar to the above, after the state of FIG. 5, the auxiliary wiring 150 and the pixel electrode 76 are further formed,
The state is exactly the same as in FIG. The auxiliary wiring 150 covers the circuit region B widely, and is connected to the second electrode power line 140 in the circuit region B. Therefore, the second electrode power line 14
It is not necessary to form 0 long in a U-shape as shown in FIG. 1A, and there is no problem even if it is formed in a short rectangle as in this modification. In this modification, the area for forming the second electrode power supply line 140 can be saved.

FIG. 6 is a partial cross-sectional view of a light emitting device 1A according to a modification of FIG. This figure shows a cross section that crosses the light emitting region A and the scanning line drive circuits 100A and 100B as peripheral circuits but does not cross the second electrode power line 140. A circuit step flattening film 35 overlaps at least part of the transistors 40 and 50 constituting the peripheral circuit, and the circuit step flattening film 35 is covered with the first portion 150 a of the auxiliary wiring 150. On the peripheral circuit, the end portion of the electrode protection film 80 is the circuit protection film 34.
In this case, moisture or gas is prevented from entering through the end of the circuit level difference flattening film 35.

In this modification, since the light emitting element leveling film 82 covers a part of the peripheral circuit, the light emitting element leveling film 82 relaxes the level difference or unevenness that may be caused by the peripheral circuit, and the light emitting element leveling film is flat. Since the bending angle of the gas barrier layer 84 covering the chemical film 82 is also relaxed, it is possible to suppress stress concentration on a part of the gas barrier layer 84. Further, the gas barrier layer 84 terminates in direct contact with the circuit protection film 34 in a region overlapping the peripheral circuit. Therefore, the area of the substrate 30 can be reduced as compared with the case where the gas barrier layer 84 terminates outside the peripheral circuit. Since the gas barrier layer 84 is in direct contact with the circuit protective film 34 and the end of the electrode protective film 80 is in direct contact with the circuit protective film 34, the gas barrier layer 84 is disposed between the circuit step planarizing film 35 and the electrode protective film 80. The OLED element 70 is sealed.

In FIG. 6, the gas barrier layer 84 terminates in direct contact with the circuit protection film 34, but the gas barrier layer 84 may terminate in direct contact with the end portion of the electrode protection film 80. Again,
Compared with the case where the gas barrier layer 84 terminates outside the peripheral circuit, the area of the substrate 30 can be reduced, and the OLED disposed between the circuit step planarizing film 35 and the electrode protective film 80 is provided.
The element 70 is sealed.

Also in this modification, there is a first region B1 in which the partition wall 37 and the circuit leveling flattening film 35 are overlapped on the inner side in the circuit region B on the substrate 30, and there is no partition 37 on the outer side and the circuit level difference. There is a second region B2 in which the planarizing film 35 is formed, and on the outside thereof, the partition 3
7, there is a third region B3 in which neither the circuit level difference flattening film 35 is formed. Accordingly, there is a first region B1 having a large height on the inner side in the circuit region B on the substrate, a second region B2 having a slightly lower height on the outer side, and a considerably lower height on the outer side. Due to the presence of the third region B3, the height of the electrode protection film 80 on the substrate can be gradually decreased from the inside toward the outside.

The inclined surface 82a of the light-emitting element step planarizing film 82 overlaps the first region B1, the second region B2, and the third region B3 and terminates in the third region B3. Inclined surface 8 of light-emitting element step planarizing film 82
2a overlaps the first region B1, the second region B2, and the third region B3 and terminates at the third region B3, so that the inclined surface 82 of the light emitting element step planarizing film 82 draws a gentle curve.
It is easy to form a. For this reason, since the bending angle of the gas barrier layer 84 covering the light emitting element step planarizing film 82 is also relaxed, it is possible to suppress stress from being concentrated on the bent portion of the gas barrier layer 84.
In particular, when the light emitting element step planarizing film 82 is formed by coating and solidifying a liquid organic compound having a high viscosity, the organic compound extends along the surface of the electrode protective film 80, and therefore, the light emitting element step planarizing film 82 is rapidly bent. Since it is easy to form the inclined surface 82a having no gas, the breakage of the gas barrier layer 84 can be suppressed.

Second Embodiment
In the first embodiment described above, the OLED in which the auxiliary wiring 150 is formed in the light emitting region A.
It was formed simultaneously with the pixel electrode 76 which is a constituent element of the element 70. On the other hand, in the second embodiment, the auxiliary wiring 150 is formed independently of the formation of the OLED element 70.

FIG. 7 shows a cross-sectional view of the light emitting device 2 according to the second embodiment. As shown in this figure, the auxiliary wiring 150 is formed on the common electrode 72 so as to be in surface contact, and an electrode protection film 80 is formed so as to cover the auxiliary wiring 150 and the common electrode 72. Conversely, the auxiliary wiring 150 may be formed so as to be in surface contact under the common electrode 72.
If the auxiliary wiring 150 is formed so as to be in surface contact with the common electrode 72, the common electrode 7 is formed due to the step of the auxiliary wiring 150 or the stress of the auxiliary wiring 150 when the common electrode 72 is formed.
There is no risk of disconnection 2. On the other hand, when the auxiliary wiring 150 is formed so as to be in surface contact with the common electrode 72, it can be formed on the partition wall 37 before the light emitting functional layer 74 is formed.
In this case, since the light emitting functional layer 74 is not formed, the pattern of the auxiliary wiring 150 can be formed by photolithography or the like, and with the same accuracy as the wiring of the transistors 40, 50, 60 and the scanning line 111. The auxiliary wiring 150 can be formed.

The material of the auxiliary wiring 150 is the same as that of the first embodiment, and has light shielding properties and conductivity. Since the auxiliary wiring 150 is in contact with the common electrode 72 on the surface in the circuit region B, the connection resistance can be lowered. Therefore, the power supply impedance can be greatly reduced. Further, the auxiliary wiring 150 is disposed in a region where the OLED element 70 is not formed in the light emitting region A. For example, the auxiliary wiring 150 is formed on the partition wall 37. Therefore, the first
There is no need to form the contact hole CH and connect the common electrode 72 and the auxiliary wiring 150 in the light emitting region A as in the embodiment. When the contact hole CH is formed, it is necessary to form the common electrode 72 and the electrode protective film 80 on the inner surface of the contact hole CH, so that the structure becomes complicated and the reliability is lowered. On the other hand, in the second embodiment, the auxiliary wiring 1
Since 50 is formed on the partition wall 37, the structure can be simplified and the reliability can be improved.

In this embodiment, the auxiliary wiring 150 protrudes outside the common electrode 72 at the end of the common electrode 72, and the electrode protection film 80 covers the outer side. By forming in this way, it is possible to prevent moisture and air entering from the end of the panel 10 from reaching the light emitting functional layer 74 along the surface of the common electrode 72. In this embodiment, the pixel electrode 76 is opaque and reflective, but the pixel electrode 76 may be formed of a transparent conductive material to realize dual emission.

Also in this embodiment, since the light emitting element leveling film 82 covers the entire area of the peripheral circuit, the light emitting element leveling film 82 relaxes the level difference or unevenness that may be caused by the peripheral circuit. Since the bending angle of the gas barrier layer 84 covering the planarizing film 82 is also relaxed, it is possible to suppress stress concentration on a part of the gas barrier layer 84. Further, the electrode protective film 80
In addition, the peripheral circuit can be protected by the sealing structure having the gas barrier layer 84. For example, when the light emitting element step planarizing film 82 is made of an organic compound, the peripheral circuit is deteriorated by the gas or impurities generated by the light emitting element step planarizing film 82 during or after curing. Can be suppressed.

As shown in FIG. 7, the gas barrier layer 84 is in direct contact with the electrode protective film 80 outside the peripheral circuit on the substrate 30. Therefore, air or moisture from the outside can be prevented from entering the light emitting element step flattening film 82 sandwiched between the gas barrier layer 84 and the electrode protective film 80. In addition, even if a defect occurs in the electrode protective film 80, the gas barrier layer 84 indicates that the sealing performance is impaired due to the defect in the electrode protective film 80 in the portion where the gas barrier layer 84 is in direct contact with the electrode protective film 80. Can be prevented.

Further, since the gas barrier layer 84 is in direct contact with the electrode protection film 80 at a position where the common electrode 72 in the second electrode power supply line 140 overlaps with the portion in direct contact with the second electrode power supply line 140, the width is wide. Compared with the case where the gas barrier layer 84 is in direct contact with the electrode protection film 80 only at a position outside the second electrode power line 140, the area of the substrate 30 can be reduced. Further, if the second electrode power line 140 having a large width is disposed between the peripheral circuit and the light emitting region A, the substrate 30 must be enlarged because the distance between the light emitting region A and the peripheral circuit is wide. There is a risk of not being able to. However, in this embodiment, the gas barrier layer 84 is disposed at the position where the second electrode power line 140 is disposed outside the peripheral circuit and overlaps the second electrode power line 140.
Since it is in direct contact with 0, the substrate 30 does not have to be very large. Furthermore, since the second electrode power line 140 is formed at a height different from that of the common electrode 72, the portion that electrically connects the second electrode power line 140 and the common electrode 72 is connected to other parts. A level difference may occur, and a defect due to the level difference may occur in the electrode protection film 80 accordingly. However, even if a defect due to such a step occurs in the electrode protection film 80, the gas barrier layer 84 is in direct contact with the electrode protection film 80 at a position overlapping the second electrode power line 140, so that the electrode protection The gas barrier layer 84 can prevent the sealing performance from being damaged by the defect of the film 80.

The light-emitting element step planarizing film 82 is an inclined surface that connects a large uneven surface (lower surface in the drawing) facing the electrode protective film 80 and a flat surface (upper surface in the drawing) opposite to the electrode protective film 80. 82a. In the light emitting element step flattening film 82, the light emitting element step flattening film 8 is formed by connecting the inclined surface 82a to the lower surface in the drawing and the upper surface in the drawing in a plane perpendicular to the substrate 30.
2 to relax the bending angle of the gas barrier layer 84 covering 2, and the stress concentration in the gas barrier layer 84 can be relaxed. The fact that the inclined surface 82a overlaps with the peripheral circuit means that the light emitting element step flattening film 82 terminates at or around the peripheral circuit. In this case,
Compared to the case where the inclined surface 82a is completely outside the peripheral circuit, the area occupied by the light-emitting element step planarizing film 82 can be reduced, so that the area of the substrate 30 can be reduced.

As shown in FIG. 7, there is a first region B1 in which a partition wall 37 and a circuit leveling flattening film 35 overlap each other in the circuit region B on the substrate 30, and there is no partition wall 37 on the outer side. There is a second region B2 in which the circuit level flattening film 35 is formed, and there is a third region B3 in which neither the partition wall 37 nor the circuit level flattening film 35 is formed. Accordingly, there is a first region B1 having a large height on the inner side in the circuit region B on the substrate, a second region B2 having a slightly lower height on the outer side, and a considerably lower height on the outer side. Due to the presence of the third region B3, the height of the electrode protection film 80 on the substrate can be gradually decreased from the inside toward the outside.

The inclined surface 82a of the light-emitting element step planarizing film 82 overlaps the first region B1, the second region B2, and the third region B3 and terminates in the third region B3. Inclined surface 8 of light-emitting element step planarizing film 82
2a overlaps the first region B1, the second region B2, and the third region B3 and terminates at the third region B3, so that the inclined surface 82 of the light emitting element step planarizing film 82 draws a gentle curve.
It is easy to form a. For this reason, since the bending angle of the gas barrier layer 84 covering the light emitting element step planarizing film 82 is also relaxed, it is possible to suppress stress from being concentrated on the bent portion of the gas barrier layer 84.
In particular, when the light emitting element step planarizing film 82 is formed by coating and solidifying a liquid organic compound having a high viscosity, the organic compound extends along the surface of the electrode protective film 80, and therefore, the light emitting element step planarizing film 82 is rapidly bent. Since it is easy to form the inclined surface 82a having no gas, the breakage of the gas barrier layer 84 can be suppressed.

<Third Embodiment>
FIG. 8A is a schematic plan view showing a part of the configuration of the light-emitting device 3 according to the third embodiment of the present invention, and FIG. 8B is the common electrode 72 after the state of FIG. FIG. 9 is a plan view showing a state in which an auxiliary wiring 150 is further formed after the state of FIG. 8B. FIG. 10 is a partial cross-sectional view of the light emitting device 3. 11 shows the light emitting device 3 shown in FIG.
It is a partial sectional view different from 0.

In the first embodiment described above, the second electrode power line 140 is provided outside the peripheral circuit (scanning line drive circuits 100A and 100B, precharge circuit 120) in the circuit region B as shown in FIG.
However, in the third embodiment, the second electrode power supply line 140 is provided between the peripheral circuit and the light emitting region A. The second electrode power line 140 and the common electrode 72 are connected by a contact hole CH as shown in FIG.

As shown in FIG. 10, at least a portion of the scanning line 111 extending from the circuit region B to the light emitting region A that overlaps the second electrode power line 140 is arranged at a different height from the second electrode power line 140. The two are insulated by a first interlayer insulating layer 33. Although not shown, data line 1
The same applies to the portion of 12 that overlaps at least the second electrode power line 140 and the portion of the current feed line 113 that overlaps at least the second electrode power line 140. At least a portion of the scanning line 111, the data line 112, or the current supply line 113 that overlaps the power supply line 140 for the second electrode is simultaneously formed on the gate insulating layer 32 from the same material as the gate electrodes 42, 52, and 62. (
Although not shown, the same applies to other embodiments). Then, a second layer is formed on the first interlayer insulating layer 33.
An electrode power line 140 is formed.

In this embodiment, since the common electrode 72 and the auxiliary wiring 150 do not overlap with the peripheral circuits (the scanning line driving circuits 100A and 100B and the precharge circuit 120), a parasitic circuit is formed in the gap between the peripheral circuit and the common electrode 72 or the auxiliary wiring 150. No capacity is generated. Therefore, it is possible to suppress deterioration of a signal transmitted from the peripheral circuit (for example, a shift pulse generated when the shift register in the scanning line driving circuits 100A and 100B selects the scanning line 111 as described above).

In this embodiment, the circuit level difference flattening film 35 and the circuit protective film 34 are formed of peripheral circuits (scanning line drive circuits 100A and 100B having transistors 40 and 50 and a precharge circuit 120).
), The peripheral circuit is mechanically protected by the circuit step flattening film 35 and the circuit protective film 34 in the manufacturing process of the light emitting device. In particular, if the auxiliary wiring 150 or the common electrode 72 is formed by vapor deposition, it is possible to prevent a mask that patterns the auxiliary wiring 150 or the common electrode 72 from contacting the peripheral circuit and damaging the peripheral circuit during vapor deposition. Such a mask is disposed on the circuit step leveling film 35 and the outermost partition wall 37. In addition, for example, static electricity generated in a cleaning process after deposition can be prevented from flowing into the peripheral circuit and being damaged. The thin circuit protection film 34 formed of a dense and fragile material is vulnerable to impact, but the thicker and buffering circuit step planarization film 35 overlaps the circuit protection film 34 and the peripheral circuit. Mechanical protection to peripheral circuits and protection from static electricity are more reliable.

As shown in FIG. 11, a terminal 112 </ b> A of a data line 112 (see FIG. 1A) is formed in the circuit region B between the outer peripheral edge of the substrate 30 and the light emitting region A. The terminal 112 </ b> A is bonded to the flexible substrate 20 by ACF and is electrically connected to the data line driving circuit 200, and supplies a signal to the unit circuit P through the data line 112. A portion of the data line 112 other than the terminal 112A is covered with a circuit protective film 34, and further partially covered with a circuit step flattening film 35. Since the data line 112 has a portion covered with the circuit step planarizing film 35 and the circuit protective film 34, the data line 112 is mechanically formed by the circuit step planarizing film 35 and the circuit protective film 34 in the manufacturing process of the light emitting device. Protected. In particular, if the auxiliary wiring 150 or the common electrode 72 is formed by vapor deposition, the auxiliary wiring 150 or the common electrode 7 is formed at the time of vapor deposition.
It is possible to prevent the mask for patterning 2 from coming into contact with the data line 112 and being disconnected.
Such a mask is disposed on the circuit step leveling film 35 and the outermost partition wall 37. Further, for example, static electricity generated in a cleaning process after vapor deposition can be prevented from flowing into the unit circuit P and being damaged. The thin circuit protection film 34 formed of a dense and fragile material is vulnerable to impact, but the thicker and buffering circuit step planarization film 35 overlaps the circuit protection film 34 and the peripheral circuit. The mechanical protection to the data line 112 and the protection of the unit circuit P from static electricity are more reliable. Further, since the partition wall 37 and the circuit step flattening film 35 are interposed between the data line 112 and the auxiliary wiring 150 or the common electrode 72, parasitic capacitance is hardly generated between them.

11 shows that the data line 112 protects the circuit protective film 34 and the circuit leveling flattening film 35. As shown in FIG. The first electrode power supply line 130 and the second electrode power supply line 140 that supply the first electrode have a portion extending in parallel with the data line 112, and the portion extending in parallel with the data line 112 has an ACF on the flexible substrate 20. And a terminal that is bonded to and electrically connected to the power source. The first electrode power supply line 130 and the second electrode power supply line 140 also have portions covered by the circuit level difference flattening film 35 and the circuit protective film 34, so that they are mechanically protected in the manufacturing process of the light emitting device. And is protected from static electricity flow.

Also in this embodiment, since the light emitting element leveling film 82 covers the entire area of the peripheral circuit, the light emitting element leveling film 82 relaxes the level difference or unevenness that may be caused by the peripheral circuit. Since the bending angle of the gas barrier layer 84 covering the planarizing film 82 is also relaxed, it is possible to suppress stress concentration on a part of the gas barrier layer 84. Further, the electrode protective film 80
In addition, the peripheral circuit can be protected by the sealing structure having the gas barrier layer 84. For example, when the light emitting element step planarizing film 82 is made of an organic compound, the peripheral circuit is deteriorated by the gas or impurities generated by the light emitting element step planarizing film 82 during or after curing. Can be suppressed.

As shown in FIG. 10, the gas barrier layer 84 is in direct contact with the electrode protection film 80 outside the peripheral circuit on the substrate 30. Therefore, air or moisture from the outside can be prevented from entering the light emitting element step flattening film 82 sandwiched between the gas barrier layer 84 and the electrode protective film 80. In addition, even if a defect occurs in the electrode protective film 80, the gas barrier layer 84 indicates that the sealing performance is impaired due to the defect in the electrode protective film 80 in the portion where the gas barrier layer 84 is in direct contact with the electrode protective film 80. Can be prevented.

The light-emitting element step planarizing film 82 is an inclined surface that connects a large uneven surface (lower surface in the drawing) facing the electrode protective film 80 and a flat surface (upper surface in the drawing) opposite to the electrode protective film 80. 82a. In the light emitting element step flattening film 82, the light emitting element step flattening film 8 is formed by connecting the inclined surface 82a to the lower surface in the drawing and the upper surface in the drawing in a plane perpendicular to the substrate 30.
2 to relax the bending angle of the gas barrier layer 84 covering 2, and the stress concentration in the gas barrier layer 84 can be relaxed. The fact that the inclined surface 82a overlaps with the peripheral circuit means that the light emitting element step flattening film 82 terminates at or around the peripheral circuit. In this case,
Compared to the case where the inclined surface 82a is completely outside the peripheral circuit, the area occupied by the light-emitting element step planarizing film 82 can be reduced, so that the area of the substrate 30 can be reduced.

As shown in FIGS. 10 and 11, a partition wall 37 is provided on the inner side in the circuit region B on the substrate 30.
There is a first region B1 formed by overlapping the circuit step planarizing film 35, and there is a second region B2 outside the partition wall 37 where the circuit step planarizing film 35 is formed. On the outside thereof, there is a third region B3 in which neither the partition wall 37 nor the circuit level difference flattening film 35 is formed.
Accordingly, there is a first region B1 having a large height on the inner side in the circuit region B on the substrate, a second region B2 having a slightly lower height on the outer side, and a considerably lower height on the outer side. Third
With the region B3, the height of the electrode protection film 80 on the substrate can be gradually decreased from the inside toward the outside.

The inclined surface 82a of the light-emitting element step planarizing film 82 overlaps the first region B1, the second region B2, and the third region B3 and terminates in the third region B3. Inclined surface 8 of light-emitting element step planarizing film 82
2a overlaps the first region B1, the second region B2, and the third region B3 and terminates at the third region B3, so that the inclined surface 82 of the light emitting element step planarizing film 82 draws a gentle curve.
It is easy to form a. For this reason, since the bending angle of the gas barrier layer 84 covering the light emitting element step planarizing film 82 is also relaxed, it is possible to suppress stress from being concentrated on the bent portion of the gas barrier layer 84.
In particular, when the light emitting element step planarizing film 82 is formed by coating and solidifying a liquid organic compound having a high viscosity, the organic compound extends along the surface of the electrode protective film 80, and therefore, the light emitting element step planarizing film 82 is rapidly bent. Since it is easy to form the inclined surface 82a having no gas, the breakage of the gas barrier layer 84 can be suppressed.

<Modification>
The present invention is not limited to the above-described embodiments. For example, the following modifications are possible.
Moreover, in each embodiment mentioned above, although the common electrode 72 was the cathode of the OLED element 70, it may be an anode.
Further, in each of the above-described embodiments, the auxiliary wiring 150 and the pixel electrode 76 are made of a metal material having a light shielding property, for example, an aluminum layer, and a transparent oxide conductive material, for example, ITO, I
ZO, or it may be composed of two layers of a layer of ZnO ₂ and the like. Since such a transparent oxide conductive material has low gas permeability, the peripheral circuit can be protected from, for example, gas or impurities generated in the outside air or the light-emitting element step planarizing film 82 after curing.
In addition, although the auxiliary wirings 150 are arranged in a lattice pattern in the light emitting region A in each of the above-described embodiments, this need not be provided.
In each of the embodiments described above, a single common electrode 72 is provided as the cathode of all the OLED elements 70. However, a plurality of common electrodes are provided, and each of the common electrodes has a different OL.
You may arrange | position so that it may become a cathode of ED element 70. FIG.
11 is a partial cross-sectional view different from FIG. 10 of the light-emitting device 3 of the third embodiment, but a cross-section different from FIG. 7 of the light-emitting device 2 according to the second embodiment is as shown in FIG. Also good.

In the above-described embodiment, the partition wall 37 and the circuit level difference flattening film 35 are formed in the first region B1.
In the second region B2, there is no partition wall 37 and the circuit step planarizing film 35 is formed. In the third region B3, neither the partition wall 37 nor the circuit step planarizing film 35 is formed. However, in the first region B1, the partition wall 37 and the circuit step planarizing film 35 are formed so as to overlap each other, in the second region B2, the partition wall 37 is formed without the circuit step planarizing film 35, and in the third region B3, the partition wall is formed. It is possible to make a modification in which neither the step 37 nor the circuit step flattening film 35 is formed. In particular, the second and third embodiments may be modified in this way. When deformed in this way, the bending angle of the inclined surface 82a of the light emitting element step flattening film 82 at the boundary between the first region B1 and the second region B2 and the gas barrier layer 84 covering the inclined surface 82a is relaxed, and stress on this portion is reduced. Concentration is suppressed.

In the embodiment described above, the common electrode 72 overlaps the second electrode power line 140, and the auxiliary wiring 150 overlaps the common electrode 72 at this overlapping portion. The common electrode 72 may not be overlapped and may be connected by an auxiliary wiring 150 therebetween.
When the common electrode 72 is used as a cathode, the material generally has a low work function and high reactivity, so that the material should be kept as far as possible from the sealing portion (the portion where the gas barrier layer 84 and the substrate (electrode protective film 84) are in contact). Is preferred. If the common electrode 72 does not overlap the second electrode power line 140, the common electrode can be terminated at an inner portion on the substrate, and the common electrode 72 can be disposed far from the sealing portion. Easy.
In this case, the peripheral circuit may not be covered by the common electrode 72, but, as in the first and second embodiments described above, the common electrode 72 and the auxiliary wiring 150 are covered so as to cover the peripheral circuit.
If the common electrode 72 and the auxiliary wiring 150 are stacked on the peripheral circuit, the common electrode 72 and the auxiliary wiring 150 are in surface contact with each other over a wide area, and these can be connected with low resistance.

<Application example>
Next, electronic devices to which the light emitting device according to the present invention is applied will be described. FIG. 12 is a perspective view illustrating a configuration of a mobile personal computer in which the light emitting device 1 according to the above embodiment is applied to a display device. The personal computer 2000 includes a light emitting device 1 as a display device and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. The light emitting device 1 (1A, 2, 3) includes an OLED element 70.
Therefore, it is possible to display an easy-to-see screen with a wide viewing angle.

FIG. 13 shows a mobile phone to which the light emitting device 1 according to the above embodiment is applied. Mobile phone 3
000 includes a plurality of operation buttons 3001, scroll buttons 3002, and a light emitting device 1 (1A, 2, 3) as a display device. By operating the scroll button 3002, the screen displayed on the light emitting device 1 (1A, 2, 3) is scrolled.

FIG. 14 shows a portable information terminal (PDA: Personal) to which the light emitting device 1 according to the embodiment is applied.
Digital Assistant). The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and a light emitting device 1 (1A, 2, 3) as a display device. When the power switch 4002 is operated, various kinds of information such as an address book and a schedule book are displayed on the light emitting device 1.

As electronic devices to which the light emitting device according to the present invention is applied, in addition to those shown in FIGS. 12 to 14, a digital still camera, a television, a video camera, a car navigation device, a pager, an electronic notebook, electronic paper, a calculator, a word processor , Workstations, videophones, POS terminals, light sources such as printer heads that form a latent image by irradiating an image carrier in an image printing apparatus using electrophotography, printers, scanners, copiers, video Examples include a player and a device equipped with a touch panel.

(A) is a schematic plan view which shows a part of structure of the light-emitting device concerning 1st Embodiment of this invention, (B) is the state which further formed the auxiliary wiring and the pixel electrode after the state of (A). FIG. It is a circuit diagram which shows the detail of the pixel circuit of the apparatus. FIG. 2 is an enlarged view of a part of FIG. It is a fragmentary sectional view of the apparatus. It is a schematic plan view which shows a part of structure of the light-emitting device which concerns on the modification of 1st Embodiment of this invention, Comprising: It is a figure which shows the state similar to FIG. 1 (A). FIG. 6 is a partial cross-sectional view of the apparatus of FIG. It is a fragmentary sectional view of the light-emitting device concerning a 2nd embodiment of the present invention. (A) is a schematic top view which shows a part of structure of the light-emitting device which concerns on 3rd Embodiment of this invention, (B) is a top view which shows the state which further formed the common electrode after the state of (A) It is. FIG. 9 is a plan view showing a state in which auxiliary wiring is further formed after the state of FIG. It is a fragmentary sectional view of the apparatus. It is a fragmentary sectional view different from FIG. 10 of the same apparatus. It is a perspective view which shows the external appearance of the personal computer which has the light-emitting device based on this invention. It is a perspective view which shows the external appearance of the mobile telephone which has a light-emitting device which concerns on this invention. It is a perspective view which shows the external appearance of the portable information terminal which has the light-emitting device which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1A, 2,3 ... Light-emitting device, 30 ... Board | substrate, 70 ... OLED element (Light emitting element, organic EL)
Element), 34 ... circuit protective film, 35 ... circuit step flattening film, 37 ... partition wall, 72 ... common electrode (second electrode), 74 ... light emitting functional layer, 76 ... pixel electrode (first electrode), 80 ... electrode Protective film, 82 ...
Light emitting element step flattening film, 82a ... inclined surface, 84 ... gas barrier layer, 100A, 100B ... scanning line driving circuit (peripheral circuit), 111 ... scanning line, 112 ... data line, 112A ... terminal, 11
3 ... power supply line, 120 ... precharge circuit (peripheral circuit), 140 ... second electrode power line,
150: auxiliary wiring, A: light emitting region, B: circuit region, B1: first region, B2: second region, B3: third region, P: unit circuit (pixel circuit).

Claims (3)

A plurality of pixel circuits provided in a light emitting region on the substrate, each of the plurality of pixel circuits having an organic EL element, wherein the organic EL element includes a first electrode, a second electrode, and the first electrode; have a light-emitting layer sandwiched between the second electrode, the second electrode is a common electrode provided in common to a plurality of the light emitting element, a light-emitting device,
A peripheral circuit disposed outside the light emitting region on the substrate and generating a signal related to driving or inspection of the plurality of pixel circuits;
A second electrode power supply line disposed outside the peripheral circuit on the substrate for supplying a potential to the second electrode;
An electrode protective film that covers the second electrode, which is the common electrode, is in contact with the second electrode, covers the light emitting region and the peripheral circuit, and seals each of the organic EL elements and the peripheral circuit; ,
The organic EL element and the peripheral circuit are disposed on the opposite side of the electrode protective film, and a first surface facing the electrode protective film and a second surface on the opposite side to the first surface A planarization film formed such that the unevenness of the second surface is smaller than the unevenness of the first surface,
A gas barrier layer that covers the planarization film and further shields each of the organic EL elements from outside air;
The planarization film and the gas barrier layer cover at least a part of the region of the peripheral circuit ;
On the substrate, the gas barrier layer is in direct contact with the electrode protective film outside the peripheral circuit, and the position where the gas barrier layer is in direct contact with the electrode protective film is at the second electrode power line. Overlapping position,
The planarizing film has an inclined surface that connects the first surface and the second surface and is inclined with respect to the substrate, and the inclined surface overlaps the peripheral circuit. Light-emitting device. A circuit protective film that covers the peripheral circuit and seals the peripheral circuit;
The circuit protection film is disposed on the opposite side of the peripheral circuit across the circuit protection film, and has a surface facing the circuit protection film and a surface opposite to the circuit protection film, A circuit step planarizing film in which the unevenness on the surface opposite to the circuit protective film is smaller than the unevenness on the surface facing
A partition that is disposed on the opposite side of the circuit protective film with the circuit step planarizing film interposed therebetween, and that defines the light emitting layer of each of the organic EL elements,
The organic EL element is disposed between the circuit step flattening film and the electrode protective film,
On the inner side of the substrate, there is a first region in which the partition wall and the circuit step flattening film are overlapped, and on the outer side, one of the partition wall and the circuit step flattening film is formed. There is a second region, and there is a third region outside the partition wall and the circuit step planarizing film, and the inclined surface of the planarizing film includes the first region, the second region, and the third region. 2. The light emitting device according to claim 1 , wherein the light emitting device overlaps with the second region and the third region and terminates in the third region. The electronic device provided with the light-emitting device in any one of Claim 1 or Claim 2 .

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