JP4741864B2 - Video display device - Google Patents

Description

  The present invention provides a video display device for displaying an input video signal on a display device.

  Various video display devices are used to display video signals such as moving images on a display device. This video display apparatus has a CPU mounted therein, and performs processing to process a video signal input under control of the CPU and display it on a display device. Therefore, when there is a problem with the program executed in the CPU, or when it is desired to change the video signal processing method or display method on the display device, it is required to update the internal program executed in the CPU. The

  Conventionally, when an internal CPU program is to be updated, the video display device is provided with a data transfer means such as a PC card and a LAN terminal capable of exchanging data with the outside like a device such as a PC (personal computer). There is a need. A conventional video display device having data transfer means for inputting program data from the outside and inputting the program data via the data transfer means is described in Patent Documents 1 and 2, for example. ing.

  However, in such a conventional video display apparatus, in addition to the video signal input terminal for inputting the video signal, an input terminal for inputting program data and data transfer means must be provided, so that the apparatus cost is reduced. There is a problem that it increases.

  Conventionally, a technique has been disclosed in which data such as character information and EPG (Electronic Program Guide) is superimposed on a video signal (see, for example, Patent Document 3). If the program data is superimposed on the video signal by using such a technique, the internal program can be updated without requiring an input terminal or data transmission means for inputting the program data.

However, the technology for superimposing various data on such a video signal superimposes data on the vertical blanking period or the like, which is a very short period in the video signal. In other words, there is a problem that rewriting time becomes long when program data is updated. Particularly in recent years, since the data capacity of the program data has been increased, if it is attempted to update the program data by such a method, it takes much time to update the internal program, which is not practical.
JP 2000-20304 A JP 2001-236233 A JP 11-275484 A

  In the above-described conventional video display device, when a program executed in the internal CPU is to be updated, an input terminal for inputting program data, a data transfer means, a video input terminal for inputting a video signal, etc. There is a problem that the cost of the apparatus increases because it is necessary to prepare for other than the above.

  An object of the present invention is to provide a video display device capable of updating a program executed in an internal CPU without providing a special data transfer means with the outside.

In order to achieve the above object, an image display device of the present invention includes an A / D conversion circuit that converts an input video signal into a digital signal, and an image for the digital signal output from the A / D conversion circuit. A video signal processing circuit for generating video data by performing signal processing, a display device driving circuit for displaying video data generated by the video signal processing circuit on a display device, the A / D conversion circuit, and the video signal A CPU for controlling video signal processing performed by a processing circuit and the display device driving circuit; and a storage means for storing program data executed by the CPU, wherein the input video signal is stored in the display device. In a video display device for displaying
The program data is superimposed and a video signal to be displayed on the display device is not superimposed in a period including the input video signal period corresponding to the video signal period displayed on the display device. When a video signal is input, program data is extracted from the digital signal by detecting a start position and an end position of the program data from a specific bit pattern included in the digital signal output from the A / D conversion circuit. characterized in that it comprises program extraction circuit you restore the original data format Te.

  The video display device of the present invention includes a program extraction circuit that extracts program data from an input video signal, so that the program data can be updated simply by inputting the program data converted into the video signal format from the video signal input terminal. Therefore, it is possible to update the program in the video display device without having any special data transfer means with the outside.

Further, the program extraction circuit,
A noise removal circuit for removing noise generated when the A / D conversion process included in the digital signal outputted from said A / D converter circuit,
A program determination circuit for determining whether the digital signal after the noise is removed by the noise removal circuit is a video signal or program data;
A data conversion circuit that restores the digital signal to the original program data when the digital signal input by the program determination circuit is determined to be program data;
Which may be Tei consists of.

Furthermore, the prior SL program extracting circuit, if the input video signal is judged whether the program data or the video signal, the input video signal is determined to be the program data, the display device driving circuit There may be subjected to treatment have a done that to display a video signal generated from the video signal the input to the display device.

  ADVANTAGE OF THE INVENTION According to this invention, when converting program data into a video signal format and inputting from a video signal input terminal, it becomes possible to prevent that an unnecessary image | video is displayed on a display device.

  As described above, according to the present invention, the program data is updated only by inputting the program data converted into the video signal format from the video signal input terminal, so that data is exchanged with the outside. Therefore, it is possible to obtain an effect that the program executed in the internal CPU can be updated without providing a special data transfer means.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a video display apparatus according to an embodiment of the present invention. Referring to FIG. 1, the video display apparatus according to the present embodiment includes an A / D conversion circuit 1, a program extraction circuit 11, a CPU 5, a volatile memory 6, a nonvolatile memory 7, and a video signal processing circuit 2. The display device drive circuit 3 and the display device 4 are included.

  The A / D conversion circuit 1 converts the video signal input from the video signal input terminal into a digital signal and outputs the digital signal to the video signal processing circuit 2 and the program extraction circuit 11.

  The CPU 5 controls the operation of the video display device, and controls video signal processing performed by the A / D conversion circuit 1, the video signal processing circuit 2, and the display device driving circuit 3.

  The nonvolatile memory 7 is a storage means for storing program data executed by the CPU 5. The volatile memory 6 is a memory for temporarily storing program data to be stored in the nonvolatile memory 7.

  The video signal processing circuit 2 generates video data by performing video signal processing on the digital signal output from the A / D conversion circuit 1. The display device drive circuit 3 causes the display device 4 to display the video data generated by the video signal processing circuit 2.

  The program extraction circuit 11 extracts the program data from the digital signal by detecting the start position and the end position of the program data from the specific bit pattern included in the digital signal output from the A / D conversion circuit 1. The program data is restored to the data format, and the program data stored in the nonvolatile memory 7 is updated.

  A normal video signal is converted into a digital signal by the A / D conversion circuit 1 and output from the video signal processing circuit 2 and the display device driving circuit 3 to the display device 4.

  When updating a program, first, the program data is converted into a video signal format that can be processed by the video signal display device of the present embodiment. At this time, a bit pattern that can specify the start position and the end position of the program data is added as information for determining whether the signal is an original video signal or program data. Also, the data is converted into a format that can easily remove errors and noise during A / D conversion and that can determine the synchronization period.

  FIG. 2 shows the data structure of the program data input from the video signal input terminal of the video display device of this embodiment.

  As shown in FIG. 2, the program data in the present embodiment has a data format in which data is not included in the vicinity of the horizontal synchronization signal, as in the case of a normal video signal. This is because the A / D conversion circuit 1 is performing clamping in the vicinity of the horizontal synchronization signal included in the normal video signal, and therefore it is necessary to maintain a reference signal level.

  Since the program data is not continuous in this way, the CPU 5 needs to determine which part of the input signal is the program data. Therefore, in order to determine the start position and end position of the program data, a specific bit pattern is inserted at the beginning and end of the program data. This bit pattern does not have a specific pattern, but it is necessary to use a pattern having a certain length so that it does not occur in normal data. For example, when the quantization bit is 8 bits, if the repetition of AAh and 55h continues for 10 patterns, the start position of the program data is set in advance.

  Further, the format in which noise can be easily removed means a format in which the noise margin is increased by reducing the number of quantization bits. For example, if the normal quantization bit is 8 bits and the signal level is 0.7V, the signal level per level is 0.7 / 255 = 0.00275V. On the other hand, for example, when the number of quantization bits is changed to 4 bits, the signal level per level becomes 0.7 V / 15 = 0.047 V, and the noise margin increases. In this case, if the noise level is 0.047 V or less, data can be restored without being affected by noise.

  However, if the information that represents the quantization bit number with 8 bits is represented with 4 bits, twice the amount of data is required. Therefore, the amount of information that can be sent decreases as the noise margin is secured.

  The A / D conversion circuit 1 converts the program data converted into the video signal into a digital signal and outputs it to the program extraction circuit 11. The program extraction circuit 11 removes noise generated during A / D conversion, and returns the data converted to the video signal format to the original program data. The CPU 5 stores the converted program data in the volatile memory 6 and updates the program data stored in the nonvolatile memory 7.

  FIG. 3 is a block diagram showing the configuration of the program extraction circuit 11. As shown in FIG. 3, the program extraction circuit 11 includes a noise removal circuit 21, a data conversion circuit 22, a program determination circuit 23, and a buffer memory 24.

  The noise removal circuit 21 removes noise generated during A / D conversion included in the digital signal output from the A / D conversion circuit 1.

  The program determination circuit 23 determines whether the digital signal from which noise has been removed by the noise removal circuit 21 is a video signal or program data, and outputs the determined result to the data conversion circuit 22.

  When the data conversion circuit 22 determines that the digital signal input by the program determination circuit 23 is program data, the data converted into the video signal format is restored to the original program data and stored in the buffer memory 24. To do.

  When the program determination circuit 23 determines that the data is program data, the video signal processing circuit 2 or the display device drive circuit 3 performs a process that does not cause the display device 4 to display.

  Next, the operation of the video display apparatus of this embodiment will be described with reference to the flowchart of FIG.

  The video signal converted into a digital signal by the A / D conversion circuit 1 is subjected to noise removal by the noise removal circuit 21 (step S1). For example, if the A / D conversion circuit 1 is 8 bits, the noise removal circuit 21 sets 0 to 127 of the digital signal as “0”, and 128 to 255 as “1”, the error in the A / D conversion circuit 1 And noise can be removed. In this case, program data to be input is created on the premise of conversion by the noise removal circuit 21.

  Next, the program determination circuit 23 determines the start and end of the input program data (steps S2 and S6). For example, the start or end of the program is determined based on the bit pattern of the data output from the noise removal circuit 21. The program discrimination circuit 23 also discriminates the synchronization portion of the video signal and sends a signal for starting and ending conversion to the data conversion circuit 22 (steps S3 and S7). Regarding the determination of the synchronization portion, as in the case of the program data determination means, when creating the program data to be input, it can be determined by adding, for example, a bit pattern that becomes a determination condition for the start and end of synchronization.

  The data conversion circuit 22 returns the program data output from the noise removal circuit 21 to its original form (step S4). In the above example, since 1 bit is output from the noise removal circuit 21, in this case, the bit structure (for example, 8 bits) to be stored in the buffer memory 24 is converted.

  The buffer memory 24 temporarily stores the data output from the data conversion circuit 22 (step S5).

  Finally, the CPU 5 stores the program data stored in the buffer memory 24 in the volatile memory 6 and updates the program stored in the nonvolatile memory 7.

  In the video display device according to the present embodiment, the program extraction circuit 11 is provided, so that the program data is extracted from the video signal input from the video signal input terminal and stored in the nonvolatile memory 7. Is updated. In other words, program data can be updated simply by inputting the program data converted into the video signal format from the video signal input terminal, so there is no need to have a storage device or communication device for exchanging data to the outside. It becomes possible to update the internal program. As a result, the present invention can be applied to a low-cost video display device that does not have an external storage device or a communication device.

  Further, by using the video display device of the present embodiment, it becomes possible to update the internal program using a video output device such as a DVD player or a PC as it is, so that a user who does not have knowledge about program update. In this case, the update work can be easily performed.

  In the present embodiment, as shown in FIG. 2, the case where the buffer memory 24 for temporarily storing the program data is provided in the program extraction circuit 11 has been described. However, the present invention is not limited to this. The circuit scale can be reduced if the program data is directly stored in the volatile memory 6 without using the buffer memory 24.

  Furthermore, in the present embodiment, as shown in FIG. 1, the case where the program extraction circuit 11 is configured separately from the CPU 5 is described, but the present invention is limited to such a configuration. Instead, the processing in the program extraction circuit 11 can be realized by the CPU 5.

It is a block diagram which shows the structure of the video display apparatus of one Embodiment of this invention. It is a figure for demonstrating the structure of the program data input into the video display apparatus of one Embodiment of this invention. It is a block diagram which shows the structure of the program extraction circuit 11 in FIG. It is a flowchart which shows operation | movement of the video display apparatus of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 A / D conversion circuit 2 Video signal processing circuit 3 Display device drive circuit 4 Display device 5 CPU
6 Volatile Memory 7 Nonvolatile Memory 11 Program Extraction Circuit 21 Noise Reduction Circuit 22 Data Conversion Circuit 23 Program Discrimination Circuit 24 Buffer Memory

Claims (3)

An A / D conversion circuit that converts an input video signal into a digital signal; a video signal processing circuit that generates video data by performing video signal processing on the digital signal output from the A / D conversion circuit; Controlling a video signal processing performed by a display device driving circuit for displaying video data generated by the video signal processing circuit on a display device, and the A / D conversion circuit, the video signal processing circuit, and the display device driving circuit. In a video display apparatus for displaying an input video signal on the display device, comprising: a CPU for performing the processing; and a storage means for storing program data executed by the CPU;
The program data is superimposed and a video signal to be displayed on the display device is not superimposed in a period including the input video signal period corresponding to the video signal period displayed on the display device. When a video signal is input, program data is extracted from the digital signal by detecting a start position and an end position of the program data from a specific bit pattern included in the digital signal output from the A / D conversion circuit. video display apparatus characterized by comprising a program extraction circuit you restore the original data format Te. The program extraction circuit comprises:
A noise removal circuit for removing noise generated when the A / D conversion process included in the digital signal outputted from said A / D converter circuit,
A program determination circuit for determining whether the digital signal after the noise is removed by the noise removal circuit is a video signal or program data;
A data conversion circuit that restores the digital signal to the original program data when the digital signal input by the program determination circuit is determined to be program data;
The video display device according to claim 1, comprising: The pre SL program extraction circuit, the input video signal is judged whether the program data or the video signal, when said input video signal is determined to be the program data, the display device driving circuit is the image display apparatus according to claim 1, wherein performing the processing not a done that to display a video signal generated from the video signal the input to the display device.

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