JP4741297B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a technique effectively applied to a semiconductor device having a wiring connected to a gate electrode through a plug and a method for manufacturing the same.

An auxiliary gate electrode type flash memory is disclosed in, for example, Japanese Patent Laid-Open No. 2005-85903 (Patent Document 1). A plurality of auxiliary gate electrodes extending in a predetermined direction are arranged adjacent to each other on a semiconductor substrate in the memory area of the flash memory. In the upper layer of the plurality of auxiliary gate electrodes, a plurality of word lines extending in a direction perpendicular to the extending direction of the auxiliary gate electrodes are arranged adjacent to each other. A floating gate electrode is arranged between each of the plurality of auxiliary gate electrodes and between each of the word lines and the semiconductor substrate in a state of being electrically separated from other members. . The floating gate electrode is formed so that the height of the upper surface is higher than the height of the upper surface of the auxiliary gate electrode.
JP 2005-85903 A

  According to the study of the present inventor, it has been found that there are the following problems.

  A semiconductor device having a nonvolatile memory has been increasingly miniaturized, and an important issue is how to reduce the size without causing various problems.

  In a low-capacity nonvolatile memory, since the design rule is relatively loose, there is a sufficient alignment margin when forming a contact hole and a plug on the auxiliary gate electrode. However, when miniaturization is promoted for increasing the capacity and miniaturization of the nonvolatile memory, the contact hole and the auxiliary gate electrode have insufficient alignment margins when forming the contact hole and the plug on the auxiliary gate electrode. . In particular, it becomes impossible to form the source line and the data line by a diffusion layer by ion implantation, and both the source line and the data line use an inversion layer under the auxiliary gate electrode. Therefore, it is necessary to form an auxiliary gate electrode having an elongated island-shaped pattern, and the alignment margin is likely to be insufficient in forming a contact hole for supplying a potential to the island-shaped auxiliary gate electrode. If the contact hole in the elongated gate-shaped auxiliary gate electrode is disconnected, the contact hole may penetrate to the semiconductor substrate, and the semiconductor substrate and the plug may be short-circuited. This reduces the manufacturing yield of the semiconductor device. Further, if a sufficient alignment margin is secured to prevent the contact hole from being disconnected, the memory cell becomes large, which is disadvantageous for increasing the capacity and size of the nonvolatile memory.

  An object of the present invention is to provide a technique capable of preventing problems caused by the contact holes being missed.

  Another object of the present invention is to provide a technique capable of improving the manufacturing yield of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In the present invention, a second conductor portion that is higher than the first conductor portion is provided via an insulating film next to the first conductor portion on the semiconductor substrate, and an upper surface end portion of the second conductor portion. Is a position that is directly above the end portion of the first conductor portion, or a position on the first conductor portion side that is directly above the end portion of the first conductor portion, and The first conductor portion is exposed at the bottom of the opening formed in the first insulating film formed so as to cover the first and second conductor portions, and the second conductor portion is exposed at the side of the opening. The third conductor portion exposed and formed in the opening is connected to the first and second conductor portions exposed from the opening.

  The present invention also includes a step of forming a first conductor portion on the semiconductor substrate, a step of forming a sidewall insulating film on a side surface of the first conductor portion, and the first conductor surface on the main surface of the semiconductor substrate. Forming a second conductor portion having an upper surface higher than the upper surface of the first conductor portion so as to be adjacent to the conductor portion with the sidewall insulating film interposed therebetween; and Forming a first insulating film so as to cover the two conductor parts; and exposing the first conductor part at the bottom of the first insulating film and exposing the second conductor part at the side surface thereof. Forming an opening, forming a third conductor portion connected to the first and second conductor portions exposed from the opening in the opening, and on the first insulating film; Forming a wiring electrically connected to the third conductor portion, and the second conductor The upper surface end portion of the first conductor portion is located at a position directly above the end portion of the first conductor portion, or at a position on the first conductor portion side beyond just above the end portion of the first conductor portion. As described above, the second conductor portion is formed.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  It is possible to prevent problems caused by the contact holes being missed.

  In addition, the manufacturing yield of the semiconductor device can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view or a perspective view may be hatched to make the drawing easy to see.

(Embodiment 1)
The semiconductor device of this embodiment and its manufacturing process will be described with reference to the drawings. In the present embodiment, an example in which the present invention is applied to, for example, a 4 Gbit (gigabit) AND type flash memory will be described.

  FIG. 1 is a fragmentary plan view of a semiconductor device (flash memory) according to an embodiment of the present invention during a manufacturing process, and FIGS. 2 and 3 are fragmentary sectional views. 1 corresponds to FIG. 2, and the sectional view taken along line BB in FIG. 1 corresponds to FIG. 1 indicates a first direction along the main surface of the semiconductor substrate 1, and reference Y in FIG. 1 indicates a second direction along the main surface of the semiconductor substrate 1 and orthogonal to the first direction X. Is shown. The same applies to symbols X and Y in other plan views. Note that the second direction Y may be a direction that intersects the first direction X, but it is more preferable if the second direction Y is a direction orthogonal to the first direction X as in the present embodiment. Further, FIG. 1 is a plan view, but the active region 3 is hatched for easy understanding of the drawing.

  First, as shown in FIGS. 1 to 3, a semiconductor substrate (semiconductor wafer) 1 made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm is prepared. An element isolation region 2 is formed. The element isolation region 2 is made of an insulator such as silicon oxide and can be formed by, for example, an STI (Shallow Trench Isolation) method. For example, after a groove (element isolation groove) is formed in the semiconductor substrate 1 by etching, a silicon oxide film is deposited on the semiconductor substrate 1 so as to fill the groove, and a CMP (Chemical Mechanical Polishing) method is used. The element isolation region 2 can be formed by removing the unnecessary silicon oxide film outside the trench and embedding the silicon oxide film only in the trench region (inside the trench). From the element isolation region 2, an active region (active region) 3 is defined on the main surface of the semiconductor substrate 1. That is, the region surrounded by the element isolation region 2 on the main surface of the semiconductor substrate 1 is the active region 3. The active region 3 is a region where a device is formed, and each active region 3 is electrically isolated by an element isolation region 2. As shown in FIG. 1, the active region 3 includes a rectangular area 3a having a relatively large area, and a plurality of strip-like areas 3b extending in the first direction X from both opposing sides of the rectangular area 3a to the outside. And a connecting portion 3c extending in the second direction Y so as to connect the end portions of the plurality of strip-like regions 3b. In FIG. 1, the right side of the rectangular area 3a is not shown, and the left side of the rectangular area 3a is shown. As will be described later, a plurality of memory cells MC and bit line inversion layers are formed in the rectangular region 3a, and a bit line inversion layer is formed in the strip-like region 3b.

  Next, a p-type well 4 is formed by selectively introducing a p-type impurity such as boron (B) into the memory region and the peripheral circuit region of the semiconductor substrate 1 using an ion implantation method or the like, An n-type well (not shown) is formed in the peripheral circuit region of the semiconductor substrate 1 by selectively introducing an n-type impurity such as phosphorus (P). In the region shown in FIGS. 1 to 3, the p-type well 4 is formed.

Next, in order to electrically connect an island-shaped AG channel portion (an inversion layer formed by an auxiliary gate electrode 15 described later) and a peripheral circuit portion (a selection MISFET Qsn described later), the region 6a shown in FIG. For example, an n-type impurity such as arsenic (As) is ion-implanted by about 1 × 10 ^{14 to} 5 × 10 ¹⁴ cm ^−2, so that an n-type semiconductor region (n-type impurity diffusion layer) is formed in the active region 3 in the region 6a. ) 6 is formed. The n-type semiconductor region 6 connects (electrically connects) a memory cell to be formed later and a selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) Qsn.

  Next, after a silicon oxide film having a thickness of, for example, about 20 nm is formed on the entire main surface of the semiconductor substrate 1 by a thermal oxidation method or the like, only in the region 7 shown in FIG. Then, the entire main surface of the semiconductor substrate 1 is oxidized (thermally oxidized) to form a silicon oxide film. As a result, gate insulation with a thickness of, for example, about 7 to 9 nm is formed in the active region 3 in the region 7 shown in FIG. A film (insulating film, insulating film for gate insulating film) 8 is formed. On the other hand, in the active region 3 other than the region 7 (in FIG. 1, the whole of the connecting portion 3c and the portion of the belt-like region 3b other than the vicinity of the rectangular region 3a) a gate insulating film (insulating film) having a thickness of about 23 to 27 nm. , An insulating film for a gate insulating film) 9 is formed. That is, the thickness of the gate insulating film 9 formed in the active region 3 other than the region 7 is relatively thicker than the thickness of the gate insulating film 8 formed in the active region 3 in the region 7. The relatively thin gate insulating film 8 is an insulating film having the same thickness as the gate insulating film (low breakdown voltage gate insulating film) for forming a low voltage transistor in the peripheral circuit, and the relatively thick gate insulating film 9 is formed in the peripheral circuit. This is an insulating film having the same thickness as a gate insulating film (high voltage gate insulating film) for forming a high voltage transistor. Therefore, the relatively thin gate insulating film 8 is formed in the same process as the gate insulating film for forming the low voltage transistor in the peripheral circuit, and the relatively thick gate insulating film 9 is formed in the gate insulating film for forming the high voltage transistor in the peripheral circuit. It can be formed in the same process as the film.

  Next, FIG. 4 and FIG. 5 are principal part sectional drawings in the manufacturing process of the semiconductor device following FIG. 4 and 5 correspond to cross-sectional views of the same process step, but FIG. 4 shows a region corresponding to FIG. 2 (cross section AA), and FIG. 5 shows a region corresponding to FIG. Cross section) is shown.

  As described above, after the gate insulating films 8 and 9 are formed, as shown in FIGS. 5 and 6, on the main surface of the semiconductor substrate 1, that is, on the gate insulating films 8 and 9, for example, a low resistance is provided. A conductor film (conductor film) 11 made of polycrystalline silicon (doped polysilicon film) is formed by a CVD (Chemical Vapor Deposition) method or the like so as to have a thickness of about 70 nm, for example. Subsequently, an insulating film (cap insulating film) 12 made of, for example, silicon nitride is formed on the conductor film 11 by a CVD method or the like so as to have a thickness of about 70 nm, for example. Subsequently, an insulating film 13 made of, for example, silicon oxide is formed on the insulating film 12 by a CVD method or the like so as to have a thickness of about 250 nm, for example.

  Next, FIGS. 6 to 9 are principal part plan views or principal part sectional views in the manufacturing process of the semiconductor device subsequent to FIGS. 4 and 5. Among these, FIG. 6 and FIG. 7 are main part plan views, but for the sake of easy understanding, in FIG. 6, the pattern shape of the conductor film 11 is shown with hatching to show other components. In FIG. 7, the active region 3, the region 6a, and the region 7 shown in FIG. 8 shows a region corresponding to FIG. 2 (AA cross section), and FIG. 9 shows a region corresponding to FIG. 3 (BB cross section).

  After the conductor film 11 and the insulating films 12 and 13 are formed as described above, the insulating film 13, the insulating film 12, and the insulating film 13 and the insulating film 12 are formed by using a photolithography method, a dry etching method, or the like as shown in FIGS. The conductor film 11 is patterned. Thereby, an auxiliary gate electrode (gate electrode, assist gate electrode, auxiliary gate wiring, first gate electrode) 15 made of the patterned conductor film 11 is formed. The auxiliary gate electrode 15 is a gate electrode (first gate electrode) for forming an inversion layer functioning as a bit line of the nonvolatile memory on the semiconductor substrate 1 (p-type well 4). As shown in FIGS. 6 and 7, each auxiliary gate electrode 15 extends in the first direction X.

  In the present embodiment, as shown in FIGS. 8 and 9, the side surface 16 of the pattern of the laminated film of the auxiliary gate electrode 15 and the insulating films 12 and 13 left after the patterning is in relation to the main surface of the semiconductor substrate 1. More preferably, it is inclined from a perpendicular direction, that is, has a tapered shape. The side surface 16 can also be regarded as the side wall of the groove 17 between the adjacent auxiliary gate electrode 15 and the laminated film pattern of the insulating films 12 and 13, and the side wall (side surface 16) of the groove 17 is the main surface of the semiconductor substrate 1. More preferably, it is inclined from a direction perpendicular to the direction, that is, has a tapered shape.

  8 and 9, the side surfaces of the insulating films 12 and 13 in the laminated film pattern of the auxiliary gate electrode 15 and the insulating films 12 and 13 have a tapered shape (that is, with respect to the main surface of the semiconductor substrate 1). In this case, the side surfaces of the insulating films 12 and 13 and the side surface of the auxiliary gate electrode 15 have a tapered shape (that is, from a direction perpendicular to the main surface of the semiconductor substrate 1). It is also possible to be in an inclined state. The inclination direction of the side surface 16 is a direction in which the dimension (width) in the second direction Y above the insulating film 13 is smaller than the dimension (width) in the second direction Y below the insulating film 13. That is, the side surface 16 of the semiconductor substrate 1 is such that the dimension in the second direction Y at the upper part of the pattern of the laminated film of the auxiliary gate electrode 15 and the insulating films 12 and 13 is smaller than the dimension in the second direction Y at the lower part. Inclined from a direction perpendicular to the main surface. The taper angle of the side surface 16 of the pattern of the laminated film of the auxiliary gate electrode 15 and the insulating films 12 and 13 is controlled by adjusting the shape of the photoresist pattern, the type of gas used for dry etching, the ratio of the gas, and the like. can do.

  After the auxiliary gate electrode 15 is formed, an insulating film (not shown) made of silicon oxide can be formed on the side surface of the auxiliary gate electrode 15 (conductor film 11) by performing a thermal oxidation treatment as necessary. If a thermal oxide film having a good film quality is formed on the side surface of the auxiliary gate electrode 15, the withstand voltage between the auxiliary gate electrode 15 and a floating gate electrode 41 described later can be further improved.

  Next, FIG. 10 and FIG. 11 are fragmentary cross-sectional views in the manufacturing process of the semiconductor device subsequent to FIG. 6 to FIG. 9. 10 and FIG. 11 correspond to cross-sectional views of the same process step, FIG. 10 shows a region corresponding to FIG. 2 (A-A cross section), and FIG. 11 shows a region corresponding to FIG. Cross section) is shown.

  An insulating film for forming a sidewall insulating film is formed on the semiconductor substrate 1 so as to cover the auxiliary gate electrode 15 and the laminated film of the insulating films 12 and 13 thereon. The insulating film for forming the sidewall insulating film is made of, for example, a silicon oxide film and can be formed by using a CVD method or the like, and the film thickness (deposited film thickness) can be set to about 40 nm, for example. Then, the insulating film for forming the side wall insulating film is etched back by anisotropic etching, so that the insulating film for forming the side wall insulating film is formed on the side wall of the laminated film of the auxiliary gate electrode 15 and the insulating films 12 and 13 thereon. A sidewall insulating film (sidewall spacer) 21 made of a film is formed, and other portions of the insulating film for forming the sidewall insulating film are removed. Thereby, the structure of FIG. 10 and FIG. 11 is obtained.

  In the present embodiment, as shown in FIGS. 10 and 11, the side surface 22 of the sidewall insulating film 21 is inclined from a direction perpendicular to the main surface of the semiconductor substrate 1, that is, has a tapered shape. It is more preferable. The inclination direction of the side surface 22 is such that the shape of the laminated film of the auxiliary gate electrode 15 and the insulating films 12 and 13 and the side wall insulating film 21 has a dimension (width) in the upper second direction Y that is lower than the first. The direction is smaller than the dimension (width) in the two directions Y. That is, the side surface 16 has an upper dimension (dimension in the second direction Y) and a lower dimension (second direction Y) of the sum of the laminated film of the auxiliary gate electrode 15 and the insulating films 12 and 13 and the sidewall insulating film 21. It is inclined from a direction perpendicular to the main surface of the semiconductor substrate 1 so as to be smaller than the dimension (1). In the sidewall insulating film 21, the side surface 22 is a side surface opposite to the side in contact with the laminated film of the auxiliary gate electrode 15 and the insulating films 12 and 13. Further, the side surface 22 can also be regarded as the side wall of the groove 23 between the adjacent side wall insulating films 21. In other words, the side wall (side surface 22) of the groove 23 is perpendicular to the main surface of the semiconductor substrate 1. More preferably, it is inclined from the direction, that is, has a tapered shape. The taper angle of the side surface 22 of the side wall insulating film 21 is controlled by adjusting the taper angle of the side surface 16, the type of gas used for dry etching of the insulating film for forming the side wall insulating film, the ratio of the gas, and the like. be able to.

  Next, FIG. 12 to FIG. 14 are principal part plan views or principal part sectional views in the manufacturing process of the semiconductor device following FIG. 10 and FIG. 11. Among these, FIG. 12 is a plan view of the main part, but for the sake of easy understanding, FIG. 12 shows the pattern shapes of the conductor film 11 (including the auxiliary gate electrode 15) and the conductor film 25 to show other configurations. Elements are not shown, and the pattern of the conductor film 25 is hatched. 13 and 14 correspond to cross-sectional views of the main part at the same process step, FIG. 13 shows a region corresponding to FIG. 2 (cross section AA), and FIG. 14 shows a region corresponding to FIG. (B-B cross section) is shown.

  After the sidewall insulating film 21 is formed as described above, the auxiliary gate electrode 15 and the insulating films 12 and 13 are formed by subjecting the semiconductor substrate 1 to thermal oxidation as shown in FIGS. An insulating film made of, for example, silicon oxide is formed on the main surface of the semiconductor substrate 1 at the bottom of the region (groove 23) between the stacked films. Then, a heat treatment (oxynitriding treatment) is performed in a gas atmosphere containing nitrogen, so that nitrogen is segregated at the interface between the insulating film and the semiconductor substrate 1 and the bottom of the trench 23 is made of silicon oxynitride (SiON). A film 24 is formed. The insulating film 24 is a film that functions as a tunnel insulating film of the memory cell MC, and the thickness thereof can be set to about 7 to 10 nm, for example.

  Next, on the main surface of the semiconductor substrate 1, for example, the groove 23 (that is, a region between the laminated film of the auxiliary gate electrode 15 and the insulating films 12 and 13 (including the sidewall insulating film 21)) is filled, for example, with a low A conductive film (conductor film) 25 made of resistive polycrystalline silicon (doped polysilicon) is deposited (formed). The conductor film 25 is a conductor film for forming a floating gate electrode 41 described later. The conductor film 25 can be formed using a CVD method or the like, and the film thickness (deposition film thickness) can be set to, for example, about 150 nm.

  Next, an etch back process or a CMP (Chemical Mechanical Polishing) process by an anisotropic dry etching method is performed on the conductor film 25 on the entire main surface of the semiconductor substrate 1. As a result, the conductor film 25 is left only in the trench 23 (that is, the region between the auxiliary gate electrode 15 and the laminated film of the insulating films 12 and 13). At this time, the depression from the upper surface of the insulating film 13 to the upper surface of the conductor film 25 is preferably within about 30 nm, for example. Thereby, the structure as shown in FIGS. At this stage, the height of the upper surface of the conductor film 25 is higher than the height of the upper surface of the conductor film 11 (including the auxiliary gate electrode 15). The conductor film 25 is adjacent to the auxiliary gate electrode 15 through the sidewall insulating film 21. Further, since the conductor film 25 is embedded in the groove 23 with the side surface 22 of the side wall insulating film 21 having a tapered shape as described above, the side surface of the conductor film 25 (in contact with the side surface 22 of the side wall insulating film 21). The side surface also has a tapered shape.

  Next, FIG. 15 to FIG. 17 are principal part plan views or principal part sectional views in the manufacturing process of the semiconductor device subsequent to FIG. 12 to FIG. 14. 15 is a plan view of the main part, and FIGS. 16 and 17 correspond to a cross-sectional view of the main part at the same process step, but FIG. 16 shows a region (A-A cross section) corresponding to FIG. FIG. 17 shows a region (BB cross section) corresponding to FIG.

  As shown in FIGS. 15 to 17, a resist pattern RP <b> 1 is exposed on the main surface of the semiconductor substrate 1 so that the memory region (region where the memory cell MC group is arranged) is exposed and the other region is covered by photolithography. After forming using the method, the insulating film 13 and the sidewall insulating film 21 exposed from the etching mask are etched by a dry etching method or the like. In this case, the insulating film 12 made of silicon nitride is used as an etching stopper by increasing the etching selection ratio between silicon oxide and silicon and silicon nitride so that silicon oxide is easier to remove than silicon and silicon nitride. At the same time, the insulating film 13 made of silicon oxide and the side wall insulating film 21 (the portion located on the side wall of the insulating film 13) are selectively removed. Thereby, in the memory region, a groove 27 is formed between the adjacent conductor films 25. At this time, if there is a possibility that the etching residue of the sidewall insulating film 21 is formed on a part of the side surface of the conductor film 25, the sidewall insulating film 21 made of silicon oxide is etched by performing a wet etching process. The rest can also be removed. Thereby, the structure of FIGS. 15-17 is obtained. Thereafter, the resist pattern RP1 is removed. Thus, the conductive film 25 for forming the floating gate electrode can be formed in a self-aligned manner with respect to the auxiliary gate electrode 15 without using a photomask.

  Next, FIGS. 18 to 21 are principal part plan views or principal part sectional views of the semiconductor device during the manufacturing process following FIGS. 15 to 17. Among these, FIG. 18 is a plan view of the principal part, but for the sake of easy understanding, FIG. 18 shows the pattern shape of the conductor film 11 (including the auxiliary gate electrode 15) and the word line 34 to show other configurations. Illustration of elements is omitted, and the pattern of the word line 34 is hatched. 19 to FIG. 21 correspond to a cross-sectional view of the main part in the same process step, FIG. 19 shows a region (A-A cross section) corresponding to FIG. 2, and FIG. Corresponding to the cross-sectional view, FIG. 21 shows a region (BB cross section) corresponding to FIG. The cross section taken along the line AA (FIG. 19) and the cross section taken along the line CC (FIG. 20) are both cut along the second direction Y, but the cutting position is in the first direction X. It is off.

  As shown in FIGS. 18 to 21, for example, an insulating film made of silicon oxide, an insulating film made of silicon nitride, and an insulating film made of silicon oxide are sequentially deposited from the lower layer on the main surface of the semiconductor substrate 1 by a CVD method or the like. As a result, an insulating film (ONO insulating film) 31 for the interlayer film is formed. The insulating films made of silicon oxide above and below the insulating film 31 can also be formed by a thermal oxidation method.

  Next, a conductor film 32 made of, for example, low-resistance polycrystalline silicon (doped polysilicon) is deposited (formed) on the main surface of the semiconductor substrate 1 (that is, on the insulating film 31). Then, a conductive film 33 having a lower resistance than the conductive film 32 is deposited (formed). Thereby, the conductor film 32 is embedded between the adjacent conductor films 25 (that is, the groove 27). The conductor film 33 is made of a refractory metal silicide film such as tungsten silicide. The conductor films 32 and 33 can be formed by, for example, a CVD method, and the film thickness (deposition film thickness) of each of the conductor films 32 and 33 can be set to, for example, about 100 nm. Further, an insulating film (not shown) can be formed on the conductor film 33. If an insulating film (not shown) is formed on the conductor film 33, the insulating film on the conductor film 33 functions as a protective film when performing an etching process using a word line 34 described later as an etching mask. In addition, the conductor films 32 and 33 can be prevented from being etched.

  Next, the conductor films 32 and 33 are patterned using a photolithography method, a dry etching method, or the like. A word line (control gate, gate electrode, gate wiring, second gate electrode) 34 of the memory cell is formed by the patterned conductor films 32 and 33. In this etching, the interlayer insulating film 31 can function as an etch stopper. When there is a possibility that the etching residue of the conductor film 32 may be generated outside the region where the word line 34 is to be formed (for example, the bottom or side surface of the groove 36 formed by the step of removing the insulating film 13 in FIGS. 15 to 17). By adding an isotropic etching process such as a wet etching method, the etching residue of the conductor film 32 can be removed. A portion of the word line 34 located between adjacent auxiliary gate electrodes 15 serves as a control gate electrode of the memory cell. For this reason, the word line 34 can also be regarded as a gate electrode (second gate electrode). Thereby, the structure as shown in FIGS. 18 to 21 is obtained. 19 (A-A cross section) corresponds to a cross section along the word line 34, and FIG. 20 (CC cross section) corresponds to a cross section between adjacent word lines 34.

  In the present embodiment, since the side surface of the conductor film 25 has a tapered shape as described above, the side wall of the groove 27 between the adjacent conductor films 25 has an inversely tapered shape (the opening diameter of the groove 27 is the bottom of the groove 27). From the top to the top). For this reason, when the conductor film 32 is embedded between the adjacent conductor films 25 (grooves 27), “so (voids)” are formed in the conductor films 32 between the adjacent conductor films 25 (in the grooves 27). there is a possibility. If there is "s" in the conductor film 32 between the adjacent conductor films 25 (in the groove 27), the conductive film 32 overlying the conductor film 32 is overlaid in the etching process of the conductor film 32 for forming the word line 34. The amount of etching may increase. Therefore, the etching of the conductor film 32 for forming the word line 34 is performed under the condition that the etching selection ratio (that is, the ratio of the etching rate of the conductor film 32 to the etching rate of the insulating film 31) is increased. Even if there is “s” in the conductor film 32 between the conductor films 25 (in the grooves 27), the amount of overetching of the insulating film 31 during the etching of the conductor film 32 can be suppressed, and the penetration of the insulating film 31 can be prevented. Can be prevented. Therefore, it is possible to prevent a problem that the side wall of the groove 27 between the adjacent conductor films 25 has an inversely tapered shape. The etching selection ratio can be controlled by adjusting the kind of etching gas and the gas ratio.

  Next, FIGS. 22 to 26 are main part plan views or main part cross-sectional views of the semiconductor device during the manufacturing process following FIGS. 18 to 21. Among these, FIG. 22 is a principal part top view, and FIGS. 23-26 is principal part sectional drawing. 23 shows a region (cross section AA) corresponding to FIG. 2, FIGS. 24 and 25 show a region (CC cross section) corresponding to FIG. 20, and FIG. 26 shows a region corresponding to FIG. (B-B cross section) is shown. 25 is a fragmentary cross-sectional view (CC cross-section) in the manufacturing process of the semiconductor device subsequent to FIG. 24, but the A-A cross-section of FIG. 24 and FIG. The BB cross section is the structure of FIG.

  As shown in FIGS. 22 to 24 and FIG. 26, after forming a resist pattern RP2 on the main surface of the semiconductor substrate 1 so that the memory region is exposed and the other region is covered by photolithography, Using this resist pattern RP2 and word line 34 as an etching mask, insulating film 31 in the region exposed from resist pattern RP2 and not covered with word line 34 is etched. At this time, as shown in FIG. 24, the insulating film 31 portion on the bottom of the trench 36 and the upper surface of the conductor film 25 is removed, but the insulating film 31 portion on the side wall of the conductor film 25 remains. At this time, the etching process of the insulating film 31 is slightly over-etched to remove the upper portion of the insulating film 31 on the side wall of the conductor film 25, thereby removing the insulating film 31 remaining on the side wall of the conductor film 25. It can also be lowered to make it difficult to lift off later. Thus, a structure as shown in FIG. 24 is obtained in the CC cross section, which is a region exposed from the resist pattern RP2 and not covered with the word line 34.

  Next, using resist pattern RP2 and word line 34 as an etching mask, conductive film 25 exposed therefrom is etched. That is, in the region exposed from the resist pattern RP2 and not covered with the word line 34, the conductor film 25 is removed, resulting in a structure as shown in FIG. In the region covered with the word line 34 (for example, the AA cross section shown in FIG. 23) and the region covered with the resist pattern RP2 (for example, the CC cross section shown in FIG. 26), the insulating film 31 and the conductor film 25 are formed. Remains without being removed. As a result, the conductor film 25 is patterned, and a floating gate electrode (floating gate electrode) 41 is formed by the patterned conductor film 25. Here, the floating gate electrode 41 is formed in a self-aligned manner with respect to the word line 34 by etching the conductive film 25 using the word line 34 as an etching mask. That is, the floating gate electrode 41 is formed in a self-aligned manner with respect to both the auxiliary gate electrode 15 and the word line 34. Thereby, structures as shown in FIGS. 22, 23, 25, and 26 are obtained. Thereafter, the resist pattern RP2 is removed. In this way, a memory cell of the nonvolatile memory is formed.

  The floating gate electrode 41 is a gate electrode (third gate electrode) for storing charges in the memory cell of the nonvolatile memory. A plurality of floating gate electrodes 41 are formed on the main surface of the semiconductor substrate 1, and each floating gate electrode 41 is formed on the main surface of the semiconductor substrate 1 via an insulating film 24, and includes a plurality of auxiliary gate electrodes. A plurality of word lines 34 are formed at positions that are adjacent to each other and overlap in a planar manner.

  In the present embodiment, as described above, in the etching process of the insulating film 31 and the conductor film 25, as shown in FIGS. 22 and 26, the resist is such that the memory area is exposed and the other areas are covered. Since the pattern RP2 is used as an etching mask, the conductor film 25 remains around the wide region 15a of the auxiliary gate electrode 15 as shown in FIG. The wide region 15a is a region for forming a contact portion (a contact hole 62 and a plug 63 described later) thereon, and the auxiliary gate electrode 15 is formed when the conductor film 11 and the insulating films 12 and 13 are patterned. The region in the vicinity of one end in the extending direction is formed in a pattern wider than the other. That is, the wide region 15 a is a conductor portion (first conductor portion) formed by a part of the pattern of the conductor film 11 constituting the auxiliary gate electrode 15. Therefore, the wide region 15 a is formed integrally with the auxiliary gate electrode 15 and can be regarded as a part of the auxiliary gate electrode 15. Since the conductor film 25 remaining around the wide region 15a of the auxiliary gate electrode 15 is formed of the conductor film 25 in the same layer as the floating gate electrode 41, it is called a dummy floating gate electrode (second conductor portion) 42. be able to. The dummy floating gate electrode 42 is composed of the conductor film 25 in the same layer as the floating gate electrode 41 and is formed in the same process, but as a floating gate electrode (a gate electrode for storing a charge in a memory cell of a nonvolatile memory). Is a non-functional conductor part (first conductor part). An insulating film such as a sidewall insulating film 21 is interposed between the wide region 15 a of the auxiliary gate electrode 15 and the dummy floating gate electrode 42, and the dummy floating gate electrode 42 is interposed through the sidewall insulating film 21. Adjacent to 15 wide regions 15a.

  Next, FIGS. 27 and 28 are a plan view and a cross-sectional view of main parts of the semiconductor device during the manufacturing process subsequent to FIGS. Of these, FIG. 27 is a plan view of the main part, and FIG. 28 corresponds to a cross-sectional view taken along the line DD of FIG.

  As shown in FIGS. 27 and 28, the conductor film 11 remaining on the outer periphery of the memory region and the peripheral circuit region is patterned using a photolithography technique, a dry etching technique, and the like. As a result, on the outer periphery of the memory region and the peripheral circuit region, the wiring portion (connection portion, fourth conductor portion) 15c made of the patterned conductor film 11 and the gate electrode of the MISFET of the peripheral circuit, for example, the gate electrode 45 of the selection MISFET Qsn. Form etc.

  Next, FIG. 29 to FIG. 36 are principal part plan views or principal part sectional views of the semiconductor device during the manufacturing process following FIG. 27 and FIG. 28. Among these, FIGS. 29-31 are principal part top views, and FIGS. 32-36 is principal part sectional drawing. 32 shows a region (A-A cross section) corresponding to FIG. 2, FIG. 33 shows a region (CC cross section) corresponding to FIG. 20, and FIG. 34 shows a region (B--) corresponding to FIG. FIG. 35 corresponds to a cross-sectional view taken along line EE in FIG. 29, and FIG. 36 corresponds to a cross-sectional view taken along line FF in FIG. 29 shows the same region as FIG. 27 and the like, but the left half of FIG. 30 and FIG. 31 corresponds to an enlarged part of FIG. 29, and the right side of FIG. 30 and FIG. Half corresponds to a part of the structure on the right side of FIG. FIG. 30 illustrates pattern shapes and positions of the auxiliary gate electrode 15, the word line 34, and the contact hole 62. In FIG. 31, the illustration of the word line 34 is omitted from FIG. 30, and the remaining pattern of the conductor film 11, that is, the floating gate electrode 41 and the dummy floating gate electrode 42 are hatched. Also in FIG. 30, at the positions corresponding to the lines AA, BB, CC and EE in FIG. 29, the lines AA, BB, CC and Although the EE line is described, in FIG. 30 and FIG. 31, only a part of the EE line is included in the plan view. Moreover, although the AA line and CC line of FIG. 30 and the AA line and CC line of FIG. 29 have shifted | deviated to the 1st direction X, the cross-sectional structure is substantially the same.

As shown in FIGS. 29 to 36, the n ⁻ type semiconductor region 51 for the source / drain of the selection MISFET Qsn, the n for the source / drain of the n-channel type MISFET for the peripheral circuit, using an ion implantation method or the like. ^{A −} type semiconductor region (not shown) and a p ⁻ type semiconductor region (not shown) for the source / drain of the p-channel type MISFET are formed separately.

Next, after an insulating film made of silicon oxide or the like is deposited on the main surface of the semiconductor substrate 1 by a CVD method or the like, the insulating film is etched back by an anisotropic dry etching method or the like. As a result, the insulating film 53 is embedded in the gaps between the adjacent word lines 34 and between the wiring portion 15c and the gate electrode 45, and one side surface of the outermost word line 34, one side surface of the gate electrode 45, and the periphery A side wall made of the insulating film 53 is formed on the side surface of the gate electrode of the MISFET of the circuit. Thereafter, by an ion implantation method, not the source ^{n +} -type semiconductor region 55 for the drain, ^{n +} -type semiconductor region for the source and drain of the n-channel type MISFET for a peripheral circuit (not selection MISFETQsn ) And p ⁺ type semiconductor regions (not shown) for the source and drain of the p-channel type MISFET are formed separately.

  Next, an insulating film 61 made of, for example, silicon oxide is deposited (formed) on the main surface of the semiconductor substrate 1 as an interlayer insulating film. After the insulating film 61 is deposited, the surface of the insulating film 61 can be planarized by performing a CMP process or the like as necessary.

  Next, the insulating films 61, 13, and 12 are dry-etched using a photoresist pattern (not shown) formed on the insulating film 61 by using a photolithography method as an etching mask, whereby contact holes (openings) 62 are formed. Form. The contact hole 62 is an opening (opening) formed in an insulating film such as the insulating films 61, 13, and 12. The contact hole 62 is disposed, for example, on the wide region 15 a of the auxiliary gate electrode 15, on the wiring part (connection part) 15 c, on the gate electrode 45, on the end of the word line 34, and the like.

  Next, a plug 63 is formed in the contact hole 62. The plug 63 is a conductor portion (third conductor portion) formed in the contact hole 62. In order to form the plug 63, for example, a barrier film (eg, titanium nitride film) 63a is formed on the insulating film 61 including the inside of the contact hole 62, and then the tungsten film 63b is contacted on the barrier film 63a by a CVD method or the like. It is formed so as to fill the hole 62. Then, the unnecessary tungsten film 63b and the barrier film 63a on the insulating film 61 are removed by a CMP method, an etch back method, or the like, and the barrier film 63a and the tungsten film 63b are left in the contact hole 62. A plug 63 composed of the buried barrier film 63a and tungsten film 63b can be formed.

  When the contact hole 62 is formed, it is ideal that no misalignment occurs. However, if the miniaturization is advanced in order to increase the capacity or the size of the nonvolatile memory, the alignment margin becomes insufficient. In particular, the alignment margin of the contact hole 62 in the wide region 15a of the auxiliary gate electrode 15 that is an island-shaped pattern tends to be insufficient. However, if the size of the wide region 15a of the auxiliary gate electrode 15 is further increased in order to ensure a sufficient alignment margin, the memory cell becomes large, which is disadvantageous for increasing the capacity and size of the nonvolatile memory. End up. For this reason, in order to reduce the size and increase the capacity of a semiconductor device having a flash memory, it is required to allow the contact hole 62 to be off to some extent.

  30 and 31, a contact hole 62 is formed on each wide region 15a. However, the contact hole 62a of the contact hole 62a is overlooked, and the upper portion (opening upper portion) of the contact hole 62a is the auxiliary gate electrode 15. The example of the state which shifted | deviated from the position right above the wide area | region 15a of this is shown typically. In this way, in the contact hole 62a in which the contact is lost, the dummy floating gate electrode 42 is exposed on the side surface of the contact hole 62a as shown in the cross-sectional views of FIGS. 34 and 35. The exposed portion functions as an etching stopper, and the region immediately below the exposed portion can be prevented from being etched. The bottom of the contact hole 62a is within the wide region 15a of the auxiliary gate electrode 15, and the wide region 15a is exposed at the bottom of the contact hole 62a. For this reason, the plug 63 formed in the contact hole 62a is connected to the wide region 15a of the auxiliary gate electrode 15 at the bottom and to the dummy floating gate electrode 42 exposed at the side surface of the contact hole 62a. By doing so, a failure when the contact hole 62 (especially, the contact hole 62 to be formed on the wide region 15a of the auxiliary gate electrode 15) is disconnected is prevented, and an allowable amount for the contact hole being disconnected. Can be increased. 30 and 31 show an example in which the two contact holes 62a are dislodged as an example, but the present invention is not limited to this, and the contact holes 62 to be formed on the wide regions 15a are not limited thereto. If at least one of them is out of focus, applying this embodiment can prevent a problem when the out of eye occurs. These will be described in more detail later with reference to FIGS.

  After the plug 63 is formed, a wiring (first layer wiring) 64 is formed on the insulating film 61 in which the plug 63 is embedded. For example, the wiring 64 can be formed by forming a tungsten (W) film on the insulating film 61 in which the plug 63 is embedded, and patterning the tungsten film using a photolithography method, a dry etching method, or the like. . At this time, a barrier film (for example, a titanium film and / or a titanium nitride film) can be formed on one or both of the upper and lower sides of the tungsten (W) film. The auxiliary gate electrode 15 is electrically connected to the wiring 64 through the plug 63.

  The wiring 64 is not limited to the tungsten wiring as described above and can be variously changed. For example, the wiring 64 can be an aluminum wiring or a copper wiring (for example, a buried copper wiring formed by a damascene method). Thereafter, an interlayer insulating film, an upper wiring layer, and the like are further formed, but the description thereof is omitted here. After the second layer wiring, aluminum wiring or copper wiring may be used.

  Next, the structure of the semiconductor device of this embodiment will be described.

  29 to 36, the semiconductor device according to the present embodiment includes a plurality of auxiliary gate electrodes 15, a plurality of word lines 34, a plurality of floating gate electrodes 41, and a plurality of floating gate electrodes 41 on the main surface of the semiconductor substrate 1. The selection MISFET Qsn is arranged, and a plurality of nonvolatile memory cells (hereinafter simply referred to as memory cells) formed from the floating gate electrode 41 and the like are arranged (in an array).

  The plurality of auxiliary gate electrodes 15 extend in the first direction X on the main surface of the semiconductor substrate 1. The auxiliary gate electrodes 15 are arranged in parallel along the second direction Y with a desired distance therebetween. The auxiliary gate electrode 15 is arranged so that most of it overlaps the active region 3 in a plane. In the memory (memory cell) region, the auxiliary gate electrode 15 is formed on the semiconductor substrate 1 via the gate insulating film 8, and the wide region 15a and the wiring portion 15c, which are regions for forming contact portions, are formed on the semiconductor substrate 1. It is formed through the gate insulating film 9. When a desired voltage is applied to the auxiliary gate electrode 15, an n-type inversion layer is formed on the main surface portion of the semiconductor substrate 1 in the active region 3 along the auxiliary gate electrode 15. This n-type inversion layer is a portion for forming a bit line (a source and a drain of the memory cell MC).

  When a desired voltage is applied to the desired auxiliary gate electrode 15, the source or drain is applied to the active region 3 located under the auxiliary gate electrode 15 via the gate insulating film (gate insulating film 8 or gate insulating film 9). Bit line (n-type inversion layer) is formed, electrically connected to a desired selection MISFET Qsn through the n-type semiconductor region 6, and further, a global bit line or a common drain wiring (wiring 64) through the selection MISFET Qsn. And electrically connected. That is, the auxiliary gate electrode 15 is provided for forming the source region and the drain region of the memory cell. Since the semiconductor region (impurity diffusion layer) for the bit line is not formed in advance, the source and drain regions (bit lines) are formed by using an inversion layer formed by applying a voltage to the auxiliary gate electrode 15. The size can be greatly reduced, and the overall size of the memory area can be greatly reduced. The auxiliary gate electrode 15 also has an isolation function between adjacent memory cells in addition to the function of forming a bit line.

  The plurality of selection MISFETs Qsn are arranged for each bit line on the bit line side serving as the drain and the bit line side serving as the source of the memory cell. That is, on the bit line side serving as a drain (one of the left and right sides in FIG. 30), each selection MISFET Qsn is arranged for each bit line serving as a drain along the second direction Y outside the wiring portion 15c. It is connected to one of the line and the common drain wiring. On the bit line side serving as the source, each selection MISFET Qsn is disposed outside the wiring portion 15c for each bit line serving as the source along the second direction Y and connected to the other of the global bit line or the common drain wiring. Has been.

The gate electrode 45 is formed on the outer side of the wiring part 15c (on the side opposite to the memory area) by the pattern of the strip-like conductor film 11 extending in the second direction Y along the wiring part 15c. A portion of the gate electrode 45 located on the strip region 3b of the active region 3 can function as a gate electrode of each selection MISFET Qsn. The gate electrode 45 is electrically connected to the upper wiring 64 through a plug 63 in a contact hole 62 formed in the upper portion thereof. The gate insulating film of each selection MISFET Qsn is formed between the gate electrode 45 and the semiconductor substrate 1 by the gate insulating film 9. One of the source / drain of each selection MISFET Qsn is formed by the n-type semiconductor region 6 for bit line connection, and the other of the source / drain is an n ⁻ -type semiconductor region formed near the end of the gate electrode 45. 51, from the end of the gate electrode 45 n ^- formed apart -type semiconductor region 51 minutes, n ^- than -type semiconductor region 51 is formed by the n ⁺ -type semiconductor region 55 of a high impurity concentration Yes. The n ⁺ -type semiconductor region 55 is electrically connected to the upper wiring 64 through a plug 63 in a contact hole 62 formed in the upper portion thereof.

  In the memory area, four auxiliary gate electrodes 15 are set as one set (one set), and a plurality of sets (a plurality of sets) are repeatedly arranged above and below in FIG. As shown in FIGS. 30 and 31, etc., a wide region 15a for connection to the upper layer wiring (wiring 64) is integrally formed at the right end of one auxiliary gate electrode 15 (G1) in each set. A wide region 15a for connection to the upper wiring (wiring 64) is integrally formed at the left end of the auxiliary gate electrode 15 (G2) adjacent to the lower side (lower side in FIGS. 30 and 31), The right end of the auxiliary gate electrode 15 (G3) adjacent to the side (lower side of FIGS. 30 and 31) is integrally connected to the wiring part 70b (15c), and the lower side (lower side of FIGS. 30 and 31). The left end of the auxiliary gate electrode 15 (G0) adjacent to is integrally connected to the wiring part 70a (15c). Of the wiring portions 15c, the wiring portion 15c located on the left side of FIGS. 30 and 31 corresponds to the wiring portion 70a, and the wiring portion 15c located on the right side of FIGS. 30 and 31 corresponds to the wiring portion 70b.

  The wiring part 15c, that is, the wiring parts 70a and 70b are formed in a strip-like pattern extending in the second direction Y, and each of them has four (one set) auxiliary gate electrode 15 (G3, G0). Are integrally formed and connected. That is, a plurality of auxiliary gate electrodes G0 are connected to the wiring portion 70a, and a plurality of auxiliary gate electrodes G3 are connected to the wiring portion 70b. The wiring portions 70a and 70b are a plurality of auxiliary gates that supply the same potential. A common wiring for the gate electrode 15 is used. The auxiliary gate electrode 15 (G0-3), the wide region 15a of the auxiliary gate electrode 15 and the wiring portion 15c (70a, 70b) are formed in the same layer made of, for example, a low-resistance polycrystalline silicon film as described above. It is formed by patterning the conductor film 11. Each auxiliary gate electrode 15 is electrically connected to the upper wiring 64 through the plug 63 in the contact hole 62 opened in the insulating films 12, 13, 61. The contact hole 62 is formed in the wide region 15a and It is formed in the upper part of the wiring part 15c (70a, 70b).

  As described above, in the present embodiment, the plurality of auxiliary gate electrodes 15 formed in a state extending in the first direction X on the main surface of the semiconductor substrate 1 have one end in the extending direction integrated with each other. The first type of auxiliary gate electrode 15, ie, the auxiliary gate electrodes G3, G0, and the second type of auxiliary gate electrode 15, ie, the auxiliary gate electrodes G1, G2, which are not connected and extend independently of each other. have. Therefore, the first type auxiliary gate electrode 15 is a comb-shaped pattern (planar pattern), and the second type auxiliary gate electrode 15 is an elongated island-shaped pattern (planar pattern). The first type auxiliary gate electrodes G3 and G0 are integrally connected by a wiring portion 15c which is a conductor portion extending in the second direction Y intersecting the first direction X. The ends of G3 and auxiliary gate electrode G0 opposite to each other in the extending direction are connected to wiring portions 70a and 70b, respectively. For this reason, the auxiliary gate electrode G3 and the auxiliary gate electrode G0 are not connected. The second type auxiliary gate electrodes G1 and G2 integrally have a wide region 15a at one end in the extending direction. However, the auxiliary gate electrode G1 and the auxiliary gate electrode G2 are mutually connected. A wide region 15a is integrally formed at the opposite end.

  A plurality of word lines 34 are formed for one block of memory cells (memory mat). Each word line 34 extends in the second direction Y. That is, the word lines 34 are arranged in parallel with each other at a desired distance along the first direction X in a state of intersecting (more preferably orthogonally) with respect to the auxiliary gate electrode 15. A portion of the word line 34 located between adjacent auxiliary gate electrodes 15 serves as a control gate electrode of the memory cell. As described above, each word line 34 includes a conductor film 32 made of, for example, low-resistance polycrystalline silicon and a conductor film 33 made of refractory metal silicide (for example, tungsten silicide) formed on the upper surface thereof. It is formed of a laminated film. Note that the outermost word lines 34 in the first direction X have a pattern that does not contribute to the memory operation, and are formed wider than the other word lines 34 in consideration of thinning during exposure. Further, as shown in the cross-sectional view of FIG. 32 and the like, in the second direction Y of each memory cell MC, the conductor film 32 under the word line 34 is embedded between the floating gate electrodes 41 via the insulating film 31. It is formed to be.

  The plurality of floating gate electrodes 41 are disposed in a state of being electrically insulated between adjacent adjacent auxiliary gate electrodes 15 and at the intersections with the word lines 34. The floating gate electrode 41 is a charge storage layer for data of a memory cell of a nonvolatile memory, that is, a floating gate electrode for charge storage. As described above, the floating gate electrode 41 is formed by the conductor film 25 made of, for example, low-resistance polycrystalline silicon. Is formed. The floating gate electrode 41 is provided on the main surface of the semiconductor substrate 1 via an insulating film 24. The insulating film 24 is an insulating film that functions as a tunnel insulating film of a memory cell. For example, silicon oxynitride (SiON) ) Etc. A sidewall insulating film 21 is formed between the floating gate electrode 41 and the auxiliary gate electrode 15, whereby the auxiliary gate electrode 15 and the floating gate electrode 41 are insulated. Further, an insulating film 53 is formed between the floating gate electrode 41 and the word line 34 adjacent to each other in the first direction X, thereby insulating between the floating gate electrode 41 adjacent to the first direction X and between the word lines 34. Has been. An insulating film 31 is formed between the floating gate electrode 41 and the control gate electrode of the word line 34. The insulating film 31 is a film that forms a capacitor between the floating gate electrode 41 and the control gate electrode, and is formed of a so-called ONO film in which, for example, silicon oxide, silicon nitride, and silicon oxide are sequentially stacked from the lower layer as described above. ing. The floating gate electrode 41 is formed in a substantially columnar shape on the semiconductor substrate 1 via the insulating film 24 in a region sandwiched between the auxiliary gate electrodes 15 and positioned below the word line 34. That is, the plurality of floating gate electrodes 41 are formed on the main surface of the semiconductor substrate 1 at positions that are adjacent to the plurality of auxiliary gate electrodes 15 and overlap the plurality of word lines 34 in a plane.

  In the floating gate electrode 41, the height of the floating gate electrode 41 (height from the main surface of the semiconductor substrate 1) is higher than the height of the auxiliary gate electrode 15 (height from the main surface of the semiconductor substrate 1). It is formed as follows. Therefore, even if the memory cell is reduced, the floating gate electrode 41 can be easily processed, which is advantageous for miniaturization of the memory cell. The capacitor of the floating gate electrode 41 and the control gate electrode is formed on the upper surface of the floating gate electrode 41 and the upper part of the side wall. That is, a capacitor is formed between the word line 34 and the floating gate electrode 41 via the insulating film 31 in the direction in which the word line 34 extends. This capacitance is calculated as the sum of capacitance values formed on the upper surface portion and the sidewall upper portion of the floating gate electrode 41. Therefore, even if the miniaturization of the memory cell is advanced, the opposing area between the floating gate electrode 41 and the control gate electrode is increased by increasing the floating gate electrode 41, so that the capacitor does not increase the area occupied by the memory cell. Therefore, the coupling ratio between the floating gate electrode 41 and the control gate electrode can be improved. Therefore, the controllability of the voltage control of the floating gate electrode 41 by the control gate electrode can be improved, so that the writing and erasing speed of the flash memory can be improved even at a low voltage, and the voltage of the flash memory can be reduced. can do. That is, both miniaturization and low voltage of the flash memory can be realized.

  In the present embodiment, as described above, in the process of forming the floating gate electrode 41 by etching the insulating film 31 and the conductor film 25, the memory region is exposed as shown in FIGS. A resist pattern RP2 is used as an etching mask so as to cover other regions (especially the wide region 15a and its vicinity). Therefore, as shown in FIG. 31 and the like, a dummy floating gate electrode (second conductor portion) 42 which is a conductor portion (second conductor portion) formed by the conductor film 25 in the same layer as the floating gate electrode 41 is provided. The auxiliary gate electrode 15 is formed around the wide region 15a. That is, the dummy floating gate electrode 42 is disposed on the main surface of the semiconductor substrate 1 so as to surround the wide region 15 a of the auxiliary gate electrode 15, and the dummy floating gate electrode 42 is formed on the auxiliary gate electrode 15 via the sidewall insulating film 21. Adjacent to the wide region 15a.

  Since the dummy floating gate electrode 42 is formed by the conductive film 25 buried between the patterns of the conductive film 11 remaining around the wide region 15a, the dummy floating gate electrode 42 is formed of the auxiliary gate electrode 15. It is formed between the wide region 15a of (G1, G2) and the wiring portion 15c or the auxiliary gate electrode 15 (G3, G0) which is the pattern of the conductor film 11 adjacent to the wide region 15a. That is, the dummy floating gate electrode 42 is provided between the wide region 15a of the second type auxiliary gate electrodes G1 and G2 (15) and the wiring portion 15c or the first type auxiliary gate electrodes G3 and G0 (15). Is formed. Here, the dummy floating gate electrode 42 formed around the wide region 15a of the auxiliary gate electrode G1 (15) is connected to the wide region 15a of the auxiliary gate electrode G1 (15) and the wiring portion 70b or the auxiliary gate electrodes G3, G0 ( 15). Further, the dummy floating gate electrode 42 formed around the wide region 15a of the auxiliary gate electrode G2 (15) includes the wide region 15a of the auxiliary gate electrode G2 (15) and the wiring portion 70a or the auxiliary gate electrodes G3, G0 (15). ).

  In particular, the dummy floating gate electrode 42 is preferably formed in a region between the wide region 15a and the wiring portion 15c of the second type auxiliary gate electrodes G1, G2 (15). Between the wide region 15a of G1, G2 (15) and the wiring part 15c, the wide region 15a of the second type auxiliary gate electrodes G1, G2 (15) and the first type auxiliary gate electrodes G3, G0 (15) It is more preferable that the dummy floating gate electrode 42 is formed in both regions between the two. Further, since the wiring portion 15c is formed integrally with the first type auxiliary gate electrodes G3, G0 (15), the dummy floating gate electrode 42 includes the wide region 15a of the auxiliary gate electrode 15 and the other auxiliary gate electrodes 15. It can also be considered that it is formed between.

  35 and 36, the dummy floating gate electrode 42 is formed on the main surface of the semiconductor substrate 1 with the element isolation region 2 and the insulating film 24a interposed therebetween. A region between the wide region 15a of the auxiliary gate electrode 15 and the wiring portion 15c is an active region 3 (3b), and an n-type inversion layer for the bit line formed by the auxiliary gate electrode 15 is selected. MISFETQsn An n-type semiconductor region 6 for electrical connection is formed. Therefore, in the region between the wide region 15a of the auxiliary gate electrode 15 and the wiring portion 15c, the dummy floating gate electrode 42 is formed not on the element isolation region 2 but on the semiconductor substrate 1 via the insulating film 24a. It is in the state. In the region between the wide region 15a of the auxiliary gate electrode 15 and the wiring portion 15c, the gate insulating film 9 is first formed, and this gate insulating film 9 is etched in an etching process for forming the sidewall insulating film 21, and thereafter The insulating film 24 is formed and becomes the insulating film 24a. Therefore, the film thickness of the insulating film 24a corresponds to the sum of the remaining film thickness of the gate insulating film 9 after the etching process for forming the sidewall insulating film 21 and the film thickness of the insulating film 24 formed. In this embodiment, since the gate insulating film 9 is thicker than the gate insulating film 8, even if the gate insulating film 8 exposed in the etching process for forming the sidewall insulating film 21 is removed, the gate insulating film 9 is exposed. It is possible to leave a part of the gate insulating film 9 to be left. For this reason, in the region between the wide region 15a of the auxiliary gate electrode 15 and the wiring portion 15c, a part of the gate insulating film 9 is left in the etching process for forming the sidewall insulating film 21, and on the remaining film. By forming the insulating film 24 to form the insulating film 24a, the thickness of the insulating film 24a can be increased. For this reason, the film thickness of the insulating film 24 a is larger than the film thickness of the insulating film 24. Further, it is more preferable that the thickness of the insulating film 24 a is larger than the thickness of the gate insulating film 8. Further, since the element isolation region 2 is made of an insulating film thicker than the insulating film 24a, the thinnest portion of the insulating film existing between the semiconductor substrate 1 and the dummy floating gate electrode 42 is the insulating film 24a.

  Next, writing, reading and erasing operations of the flash memory in the semiconductor device of this embodiment will be described.

  FIG. 37 is a principal circuit diagram at the time of data writing operation by constant charge injection, and FIG. 38 is a fragmentary sectional view of the semiconductor device at the time of data writing operation by constant charge injection.

  As shown in FIG. 37, the unit region is configured such that the selected nMISFET Qsn0 is arranged in only one stage on the common drain side, and the auxiliary gate electrode 15 has a four-system configuration (G0 to G3). A selection MISFET Qsn1 is provided for each of the global bit lines GBL0 to GBL3.

  Data writing is premised on a source-side hot electron injection system through through unselected memory cells MC, source-side selection and constant charge injection. Thus, efficient data writing can be performed at high speed with low current. In addition, multi-value data can be stored in each memory cell MC. This multi-value storage is performed by changing the amount of hot electrons injected into the floating gate electrode 41 by changing the write time while keeping the write voltage of the word line WL (corresponding to the word line 34) constant. Memory cells MC having several kinds of threshold levels can be formed. That is, four or more values such as “00” / “01” / “10” / “11” can be stored. For this reason, the function for two memory cells MC can be realized by one memory cell MC. Therefore, it is possible to reduce the size of the flash memory.

In the data write operation, for example, about 15 V is applied to the word line WL0 (34) to which the selected memory cell MC is connected, and 0 V is applied to the other word line WL1 (34), for example. For example, about 1 V is applied to the gate electrode G0 (15) for forming the source of the selected memory cell MC, and about 7 V is applied to the gate electrode G1 (15) for forming the drain of the selected memory cell MC. Thus, an n-type inversion layer 71a for forming a source is formed on the main surface portion of the semiconductor substrate 1 facing the gate electrode G0 (15), and the main surface of the semiconductor substrate 1 facing the gate electrode G1 (15). An n-type inversion layer 71b for forming a drain is formed in the portion. By applying, for example, 0 V to the other gate electrodes G2 (15) and G3 (15), an inversion layer is formed on the main surface portion of the semiconductor substrate 1 facing the gate electrodes G2 (15) and G3 (15). Isolation between selected and non-selected memory cells MC is performed so as not to be formed. In this state, the selection MISFET Qsn0 is turned on by applying a voltage of, for example, about 7V to the wiring 4LC connected to the gate electrode 45 of the selection MISFETQsn0, and the voltage of about 4V applied to the common drain wiring CD is applied to the n-type semiconductor. This is supplied to the drain of the selected memory cell MC through the region 6 and the n-type inversion layer 71b. However, as it is, the non-selected memory cell MC connected to the word line WL0 (34) is also in the same state as the selected memory cell MC, and data is also written to the non-selected memory cell MC. Therefore, for example, 0V is applied to the global bit line GBL0 to which the inversion layer 71a for forming the source of the selected memory cell MC is connected, while the n-type inversion layer for forming the source of the unselected memory cell MC is applied. For example, about 1.2 V is applied to the global bit line GBL2 to which 71a is connected. For example, 0 V is applied to the other global bit lines GBL1 and GBL3. Thus, current flows I _W write toward the drain (n-type inversion layer 71b) in the memory cell MC of the selected source (n-type inversion layer 71a). At this time, the charge accumulated in the n-type inversion layer 71a on the source side is made to flow as a certain channel current and efficiently injected into the floating gate electrode 41 through the insulating film 24 (constant charge injection method). While writing data to the memory cell MC at high speed, the drain current does not flow from the drain to the source of the non-selected memory cell MC so that the data is not written. In addition, the code | symbol F of FIG. 37 shows the floating state, and the arrow C1 of FIG. 38 has shown typically the mode of the injection | pouring of the electric charge (electron) for data.

  Next, FIG. 39 is a principal part circuit diagram at the time of data reading operation, and FIG. 40 is a principal part sectional view of the semiconductor device at the time of data reading operation.

In data read, the direction of the current I _R of the read is the write operation and reverse. That is, the current _{I R} of the read flows from the global bit lines GBL0, GBL2 to the common drain line CD. In the data read operation, for example, about 2 to 5 V is applied to the word line WL0 (34) to which the selected memory cell MC is connected, and 0 V is applied to the other word line WL1 (34), for example. Further, by applying, for example, about 5 V to the gate electrodes G0 (15) and G1 (15) for forming the source and drain of the selected memory cell MC, the main of the semiconductor substrate 1 facing the gate electrode G0 (15) is obtained. An n-type inversion layer 71a for source is formed on the surface portion, and an n-type inversion layer 71b for drain is formed on the main surface portion of the semiconductor substrate 1 facing the gate electrode G1 (15). Further, for example, 0V is applied to the other gate electrodes G2 (15) and G3 (15), so that the main surface portion of the semiconductor substrate 1 facing the gate electrodes G2 (15) and G3 (15) is inverted. Isolation is performed without forming a layer. Here, for example, about 1 V is applied to the global bit lines GBL0 and GBL2 to which the n-type inversion layer 71a for the source of the selected memory cell MC is connected, while 0 V is applied to the other global bit lines GBL1 and GBL3, for example. Apply. In this state, the selection MISFET Qsn is turned on by applying a voltage of, for example, about 3V to the wiring 4LC, and the voltage of about 0V applied to the common drain wiring CD is applied to the n-type semiconductor region 6 and the n-type inversion layer 71b. To the drain of the selected memory cell MC. In this way, data is read from the selected memory cell MC. FIG. 39 schematically shows that 1 bit is simultaneously read out of 4 bits. At this time, since the threshold voltage of the selected memory cell MC changes depending on the state of the accumulated charge in the floating gate electrode 41, the selected memory cell MC is selected in the state of the current flowing between the source and drain of the selected memory cell MC. Can be determined. For example, in the case of the two selected memory cells MC shown in FIG. 39, it is assumed that the threshold level of the left selected memory cell MC is 4V and the threshold level of the right selected memory cell MC is 5V. At this time, if the read voltage is 5 V, a current flows through both memory cells MC. However, when reading is performed at 4.5 V, no current flows in the left cell, and a current flows in the right cell. As described above, a read operation can be performed on a multi-value storage memory cell according to the state of charge stored in the memory cell MC and the read voltage.

  Next, FIG. 41 is a fragmentary cross-sectional view of the semiconductor device during the data erasing operation. In the data erasing operation, a negative voltage is applied to the word line 34 to be selected, thereby performing FN (Fowlor Nordheim) tunnel emission from the floating gate electrode 41 to the semiconductor substrate 1. That is, for example, about −16 V is applied to the word line 34 to be selected, while a positive voltage is applied to the semiconductor substrate 1 (p-type well 4). For example, 0 V is applied to the auxiliary gate electrode 15, and no n-type inversion layer is formed. As a result, the data charges stored in the floating gate electrode 41 are discharged to the semiconductor substrate 1 through the insulating film 24, and the data in the plurality of memory cells MC are erased at once. Note that an arrow C2 in FIG. 41 schematically shows a state of discharging data charges.

  Next, the effect of this embodiment will be described in more detail. 42 to 45 are principal part plan views or principal part sectional views in the manufacturing process of the semiconductor device schematically showing the vicinity of the wide area 15 a of the auxiliary gate electrode 15. 46 to 49 are principal part plan views or principal part sectional views in the manufacturing process of the semiconductor device of the comparative example schematically showing the vicinity of the wide area 15 a of the auxiliary gate electrode 15. 42 and 46 are main part plan views of the process steps after the formation of the insulating film 61 and before the formation of the contact holes 62, and FIGS. 43 and 47 are cross-sectional views of the main parts of the same process steps as those in FIGS. Corresponding to 44 and 48 correspond to the process steps after the formation of the contact hole 62 and before the formation of the plug 63, and FIGS. 45 and 49 correspond to the process steps after the formation of the plug 63 and the wiring 64. 42 to 49, the insulating film 81 is a combination of the insulating films 12 and 13, the sidewall insulating film 21, and the insulating film 61 for easy understanding. 42 and 46 show a state where the insulating film 81 is seen through. 42 to 49, the wide region 15a of the auxiliary gate electrode 15 and the dummy floating gate electrodes 42 and 142 are formed on the semiconductor substrate 1 via the insulating film 81. However, the wide region of the auxiliary gate electrode 15 is formed. The insulating film 81 below 15a corresponds to the gate insulating film 9, and the insulating film 81 below the dummy floating gate electrodes 42, 142 corresponds to the insulating film 24a or the element isolation region 2. 43 to 45 correspond to the cross sections of the GG line and the HH line of FIG. 42, for example, but in the case of the cross section of the GG line, insulation under the dummy floating gate electrode 42 is performed. The film 81 corresponds to the insulating film 24a. In the case of a cross section taken along the line H-H, the insulating film 81 under the dummy floating gate electrode 42 corresponds to the element isolation region 2. Similarly, FIG. 47 to FIG. 49 correspond to the cross sections of the GG line and the HH line of FIG. 46, for example, but in the case of the cross section of the GG line, below the dummy floating gate electrode 142, FIG. The insulating film 81 corresponds to the gate insulating film 24a, and when the section is taken along the line HH, the insulating film 81 below the dummy floating gate electrode 142 corresponds to the element isolation region 2.

  In the present embodiment, as shown in FIGS. 31 and 42, the dummy floating gate electrode 42 exists around the wide region 15 a of the auxiliary gate electrode 15.

Similar to the floating gate electrode 41, as shown in FIG. 43, the height of the upper surface 83 of the dummy floating gate electrode 42 (the height from the main surface of the semiconductor substrate 1) h ₁ or height position, the auxiliary gate electrode the height of the upper surface 84 of the wide area 15a of the 15 higher than (the height from the main surface of the semiconductor substrate 1) _{h 2} or height _{(h 1>} h 2). In addition, since the conductor film 25 is embedded in the groove 23 with the side surface 22 of the sidewall insulating film 21 having a tapered shape as described above, the side surface of the conductor film 25 also has a tapered shape. The side surface of the dummy floating gate electrode 42 formed by the conductor film 25 is also in a tapered shape. That is, the dummy floating gate electrode 42 has a tapered shape, and the upper part is larger than the lower part. Therefore, the side surface 85 of the dummy floating gate electrode 42 on the side facing the wide region 15a of the auxiliary gate electrode 15 is higher than the lower portion of the side surface 85 of the dummy floating gate electrode 42 with the wide region 15a side of the auxiliary gate electrode 15. In this way, the semiconductor substrate 1 is inclined from a direction perpendicular to the main surface. 42 and 43, in the present embodiment, the end portion (end portion on the wide region 15a side) 86 of the upper surface 83 of the dummy floating gate electrode 42 is the wide region 15a of the auxiliary gate electrode 15. It is a position that coincides with the upper portion 88 of the end portion 87 of the auxiliary gate electrode 15, or a position on the wide region 15 a side beyond the upper portion 88 of the wide portion 15 a of the auxiliary gate electrode 15. For this reason, the upper surface end (86) of the dummy floating gate electrode 42 is aligned directly above the outer periphery of the wide region 15a of the auxiliary gate electrode 15, or the dummy region is positioned near the outer periphery of the wide region 15a of the auxiliary gate electrode 15. The region near the upper end (86) of the floating gate electrode 42 is overlapped. As a result, in the vicinity of the region where the contact hole 62 is to be formed, a region in which the two do not overlap in plan is not generated between the wide region 15 a of the auxiliary gate electrode 15 and the dummy floating gate electrode 42. In other words, the end portion 86 of the upper surface 83 of the dummy floating gate electrode 42 overlaps directly above the end portion 87 of the wide region 15a of the auxiliary gate electrode 15, that is, the end of the wide region 15a of the auxiliary gate electrode 15. The dummy floating gate electrode 42 is overlapped and present at a position 88 immediately above the portion 87. Such a structure has a state in which the side surface 22 of the sidewall insulating film 21 is inclined from a direction perpendicular to the main surface of the semiconductor substrate 1, that is, as described with reference to FIGS. This can be achieved by setting

  Here, the end 87 of the wide region 15a of the auxiliary gate electrode 15 is the outermost position (the position closest to the dummy floating gate electrode 42) when the wide region 15a is viewed in plan as shown in FIG. Corresponding to Therefore, if the auxiliary gate electrode 15 including the wide region 15a has, for example, a taper shape (a shape in which the upper width is smaller than the lower width), the lower portion of the side surface of the wide region 15a of the auxiliary gate electrode 15 This corresponds to the end portion 87.

  42 to 45, the end portion 86 of the upper surface 83 of the dummy floating gate electrode 42 is in a position on the wide region 15a side beyond the portion 88 directly above the end portion 87 of the wide region 15a of the auxiliary gate electrode 15. It is shown. This is more preferable because some variation in the position of the upper surface of the dummy floating gate electrode 42 can be allowed. However, the present embodiment includes a case where the end portion 86 of the upper surface 83 of the dummy floating gate electrode 42 is positioned so as to coincide with the position 88 immediately above the end portion 87 of the wide region 15a of the auxiliary gate electrode 15. In this case, the following effects can be obtained as in the case of FIGS.

  FIG. 44 shows a state in which the contact hole 62 is formed. In order to form the contact hole 62, a resist pattern 91 having an opening 92 is formed on the insulating film 82 formed so as to cover the wide region 15a of the auxiliary gate electrode 15 and the dummy floating gate electrode 42 by photolithography or the like. Then, the insulating film 82 exposed from the opening 92 of the resist pattern 91 is dry-etched using the resist pattern 91 as an etching mask. When the opening 92 of the resist pattern 91 is arranged (formed) directly above the wide region 15a of the auxiliary gate electrode 15 without causing any dislocation, as shown in FIG. It is formed on the wide region 15 a of the auxiliary gate electrode 15, and only the wide region 15 a of the auxiliary gate electrode 15 is exposed at the bottom of the contact hole 62.

  FIG. 45 shows a state in which, after the contact hole 62 is formed, a plug 63 is formed in the contact hole 62, and a wiring 64 is formed on the insulating film 81 (61) in which the plug 63 is embedded. As shown in FIG. 44 (b), when the contact hole 62 is not loose, as shown in FIG. 45 (b), the plug 63 contacts the wide region 15a of the auxiliary gate electrode 15 at the bottom. Then, the upper part (upper surface) of the plug 63 is in contact with (connected to) the wiring 64. Thereby, the wiring 64 is electrically connected to the wide region 15 a of the auxiliary gate electrode 15 through the plug 63.

  When the contact hole 62 is formed in the upper part of the wide region 15a so as to expose the wide region 15a of the auxiliary gate electrode 15, it is ideal not to cause an unsightline. It is necessary to increase the size of the wide region 15a. When the size of the wide region 15a is increased, the interval between the auxiliary gate electrodes 15 is increased, the size of the memory cell is increased, and the area of the memory region is increased. This is disadvantageous for downsizing and increasing the capacity of a semiconductor device having a flash memory. Therefore, in order to reduce the size and increase the capacity of a semiconductor device having a flash memory, it is required to allow a certain degree of contact hole 62 to be missed.

  FIG. 44A shows a state where the contact hole 62 is formed as in FIG. 44B, but unlike FIG. 44B, the opening 92 of the resist pattern 91 is formed by the auxiliary gate electrode 15. This corresponds to the case where they are shifted (disposed) from the position just above the wide area 15a. When the opening 92 of the resist pattern 91 is missed, as shown in FIG. 44A, the insulating film 82 exposed from the missed opening 92 of the resist pattern 91 is dry using the resist pattern 91 as an etching mask. The contact hole 62a (62) is formed by etching. Note that the contact hole 62 a is a contact hole in which the contact hole 62 is missed.

  When this happens, the contact hole 62a overlaps the dummy floating gate electrode 42 in a plan view. In this case, dry etching of the insulating film 82 proceeds and a part of the dummy floating gate electrode 42 is exposed at the bottom of the contact hole 62a being formed. However, the exposed dummy floating gate electrode 42 functions as an etching stopper, and the dummy floating gate electrode 42 functions as an etching stopper. In the region immediately below the floating gate electrode 42, the dummy floating gate electrode 42 functions as an etching mask, so that the insulating film 82 is not etched. Then, dry etching of the insulating film 82 proceeds only in a region of the contact hole 62a that does not overlap the dummy floating gate electrode 42 in a plan view, and the wide region 15a of the auxiliary gate electrode 15 is exposed at the bottom of the contact hole 62a. The

  In the etching process of the insulating film 82 for forming the contact hole 62a, the etching is performed under conditions (selection ratio) such that the etching rate of the auxiliary gate electrode 15 is lower than the etching rate of the insulating film 81. Therefore, if the dummy floating gate electrode 42 (conductor film 25) and the auxiliary gate electrode 15 (conductor film 11) are formed of the same material (for example, silicon such as doped polysilicon), the contact hole 62a is formed. Therefore, the dummy floating gate electrode 42 can easily function as an etching stopper in the etching process of the insulating film 82 for this purpose.

  In the present embodiment, as shown in FIGS. 42 and 43, in the vicinity of the region where the contact hole 62 is to be formed, both are planar between the wide region 15a of the auxiliary gate electrode 15 and the dummy floating gate electrode 42. The area that does not overlap is not generated. For this reason, as shown in FIG. 44A, when a part of the dummy floating gate electrode 42 is exposed in the contact hole 62a, the insulating film 82 is not etched in the region immediately below the dummy floating gate electrode 42, and the dummy floating gate 42 is exposed. The dry etching of the insulating film 82 proceeds only in a region that does not overlap the gate electrode 42 in a planar manner, but the region where this dry etching proceeds is a region immediately above the wide region 15 a of the auxiliary gate electrode 15. Therefore, the bottom portion of the contact hole 62 a finally formed is within the range of the wide region 15 a of the auxiliary gate electrode 15. That is, only the wide region 15a of the auxiliary gate electrode 15 is exposed at the bottom of the contact hole 62a. Further, a part of the dummy floating gate electrode 42 is exposed on the side surface of the finally formed contact hole 62a. Thereafter, as shown in FIG. 45A, a plug 63 is formed in the contact hole 62a, and a wiring 64 is formed on the insulating film 81 (61) in which the plug 63 is embedded. At this time, as shown in FIG. 45A, the plug 63 contacts (connects) the wide region 15a of the auxiliary gate electrode 15 at the bottom, and the side surface of the plug 63 is exposed from the contact hole 62a. The electrode 42 contacts (connects), and the upper portion (upper surface) of the plug 63 contacts (connects) to the wiring 64. Thus, the wiring 64 is electrically connected to the wide region 15 a of the auxiliary gate electrode 15 through the plug 63 and is also electrically connected to the dummy floating gate electrode 42. The case where the contact hole 62a with such an off-line occurs in the semiconductor device is shown in FIG. 30, FIG. 31, FIG. 34 and FIG.

  In the comparative example shown in FIGS. 46 to 49, unlike the present embodiment, the dummy floating gate electrode 142 (corresponding to the dummy floating gate electrode 42 of the present embodiment) does not have a tapered shape. A side surface 185 of the floating gate electrode 142 facing the wide region 15 a of the auxiliary gate electrode 15 is perpendicular to the main surface of the semiconductor substrate 1. Therefore, in the comparative example shown in FIGS. 46 to 49, unlike the present embodiment, as shown in FIGS. 46 and 47, the auxiliary gate electrode 15 has a position immediately above the end of the wide region 15a. The dummy floating gate electrode does not exist, and a region where the two do not overlap in plan exists between the wide region 15 a of the auxiliary gate electrode 15 and the dummy floating gate electrode 142.

  In the case of such a comparative example, when the contact hole 62 is formed, if no deviation occurs, the contact hole 62 is formed on the wide region 15a of the auxiliary gate electrode 15 as shown in FIG. Only the wide region 15 a of the auxiliary gate electrode 15 is exposed at the bottom of the contact hole 62. Then, as shown in FIG. 49B, the plug 63 and the wiring 64 can be formed, and the wiring 64 can be electrically connected to the wide region 15 a of the auxiliary gate electrode 15 through the plug 63.

  However, if the opening 92 of the resist pattern 91 is missed, the insulating film 82 is dry-etched even in a region that is off from just above the wide region 15a of the auxiliary gate electrode 15, as shown in FIG. . In the comparative example, there is a region where the wide region 15a of the auxiliary gate electrode 15 and the dummy floating gate electrode 142 do not overlap in plan view, and the insulating film 81 is dry etched in this region. In order to completely expose the wide region 15a of the auxiliary gate electrode 15 at the bottom of the contact hole 62, it is necessary to dry-etch the insulating film 81 for forming the contact hole 62 in an over-etching manner. When over-etching is performed in the example, as shown in FIG. 48A, not only the insulating film 82 but also the insulating region 82 is insulated in the region between the wide region 15a of the auxiliary gate electrode 15 and the dummy floating gate electrode 142. Even the film 81 may be etched. In particular, since the insulating film 81 corresponds to the insulating film 24a in the region (cross section of the GG line) between the wide region 15a of the auxiliary gate electrode 15 and the wiring portion 15c, the insulating film 81 (24a) When removed by etching, not only the wide region 15a of the auxiliary gate electrode 15 but also the semiconductor substrate 1 (active region 3) are exposed at the bottom of the contact hole 62a. In this state, as shown in FIG. 49A, when the plug 63 and the wiring 64 are formed, the wiring 64 is not only connected to the wide region 15a of the auxiliary gate electrode 15 but also to the semiconductor substrate 1 (active) through the plug 63. It will be connected to area 3). Since such a semiconductor device is sorted and removed by a sorting test, the manufacturing yield of the semiconductor device is reduced. In order to prevent this, it is necessary to accurately control the amount of dry etching overetching of the insulating film 81 for forming the contact hole 62. However, the manufacturing process of the semiconductor device is complicated and the manufacturing yield of the semiconductor device is reduced. There is a possibility of degrading. In addition, in order to prevent the contact hole from being disconnected, it is necessary to improve the photolithography process, which increases the manufacturing cost of the semiconductor device. Further, when the dimension of the wide region 15a of the auxiliary gate electrode 15 is increased, the area of the memory region is increased, which is disadvantageous for downsizing and increasing the capacity of a semiconductor device having a flash memory.

  In contrast, in the present embodiment, in the vicinity of the region where the contact hole 62 is to be formed, there is no region between the wide region 15a of the auxiliary gate electrode 15 and the dummy floating gate electrode 42 where they do not overlap in plan view. I am doing so. For this reason, even if the contact hole 62 to be formed on the wide region 15a of the auxiliary gate electrode 15 is opened, the dummy floating gate electrode 42 is intentionally formed from the contact hole 62a where the contact has occurred. The dummy floating gate electrode 42 exposed from the contact hole 62a can be made to function as an etching stopper. For this reason, the bottom of the contact hole 62a falls within the wide region 15a of the auxiliary gate electrode 15, and the semiconductor substrate 1 around the wide region 15a of the auxiliary gate electrode 15 is prevented from being exposed at the bottom of the contact hole 62a. it can. Therefore, it is possible to prevent problems due to the contact holes being missed and to improve the manufacturing yield of the semiconductor device. In addition, since an allowable amount of contact holes can be increased, downsizing of the semiconductor device can be promoted, and the capacity of the semiconductor device having a nonvolatile memory can be increased. In addition, the manufacturing cost of the semiconductor device can be reduced. Further, even if over-etching is performed when the contact hole 62 is formed, the semiconductor substrate 1 can be prevented from being exposed, so that the contact with the plug 63 can be made more reliable, and the reliability of the contact of the semiconductor device can be improved. It can be improved further.

  Also, in the case where the disconnection occurs, as shown in FIG. 45 (a), the plug 63 embedded in the contact hole 62a is connected to the wide region 15a of the auxiliary gate electrode 15 at the bottom and on the side surface thereof. Connected to the dummy floating gate electrode 42. For this reason, the wiring 64 is electrically connected to both the wide region 15 a of the auxiliary gate electrode 15 and the dummy floating gate electrode 42 through the plug 63. However, the dummy floating gate electrode 42 is disposed on the semiconductor substrate 1 via the insulating film 81 (that is, the element isolation region 2 and the insulating film 24a), so that the contact hole 62 is not missed and the plug 63 is a dummy. When not connected to the floating gate electrode 42, the dummy floating gate electrode 42 is floating in potential (floating potential). Unlike the floating gate electrode 41, the dummy floating gate electrode 42 does not function as a charge storage layer of the nonvolatile memory. For this reason, even if the wiring 64 to be connected to the wide region 15a of the auxiliary gate electrode 15 is electrically connected not only to the wide region 15a of the auxiliary gate electrode 15 but also to the dummy floating gate electrode 42, no problem occurs.

  Further, if the thickness of the insulating film 24a existing between the dummy floating gate electrode 42 and the semiconductor substrate 1 is increased, the wiring 64 to be connected to the wide region 15a of the auxiliary gate electrode 15 becomes wider. It is possible to more appropriately prevent the influence when not only the region 15a but also the dummy floating gate electrode 42 is electrically connected. For this reason, as described above, it is preferable that the thickness of the insulating film 24a is larger than the thickness of the insulating film 24, and the thickness of the insulating film 24a is larger than the thickness of the gate insulating film 8. Is preferred.

  Further, in the present embodiment, the contact hole 62 to be formed on the wide region 15a of the auxiliary gate electrode 15 is not only in a case where all of the contact holes 62 are missed, but also the contact hole 62a in which the miss has occurred. Even in the case where the contact holes 62 in which no occurrence has occurred coexist, it is possible to obtain the effect of preventing problems due to the above-described deviation. That is, if at least one of the contact holes 62 to be formed on the wide region 15a of the auxiliary gate electrode 15 is missed, the above-described malfunction prevention (for example, the plug 63 and the semiconductor substrate 1) is prevented. It can be said that the effect of prevention of short circuit) was obtained. In other words, in the semiconductor device, if at least one of the plurality of auxiliary gate electrodes 15 on the semiconductor substrate 1 has the wide region 15a (contact portion) in the state of FIG. Thus, it can be said that the effect of preventing the trouble due to the above-described deviation (for example, prevention of short circuit between the plug 63 and the semiconductor substrate 1) is obtained.

  In the present embodiment, in the auxiliary gate electrode 15 (G1, G2) having an island-like pattern that extends independently, the contact (connecting portion with the plug 63) formation region is a wider region 15a wider than the others. . As a result, even if the contact hole 62 is largely disengaged, a part of the wide region 15 a can be exposed at the bottom of the contact hole 62. For this reason, it is possible to increase the tolerance of the contact hole 62 from being missed. Therefore, the manufacturing yield of the semiconductor device can be improved, and it is advantageous for downsizing and increasing the capacity of the semiconductor device. However, even if the wide region 15a, which is a contact formation region in the auxiliary gate electrode 15, is made the same width as the other regions of the auxiliary gate electrode 15 or thinner than other regions, the dummy floating gate electrode as in the present embodiment By providing 42, even if the contact hole 62 a is missed, the bottom of the contact hole 62 a can be accommodated in the wide region 15 a that is not wide, so that the auxiliary gate electrode 15 can be accommodated. Such a case is also included in the present embodiment.

  Further, in the present embodiment, the side surface of the contact hole 62 is in a direction perpendicular to the main surface of the semiconductor substrate 1 or the contact hole 62 is tapered (the contact hole 62 has an opening diameter from the bottom to the top). It is preferable that the contact hole 62 has a tapered shape. As a result, the dummy floating gate electrode 42 exposed at the side wall of the contact hole 62a that has been disconnected is caused to function as an etching stopper, so that the region immediately below the exposed portion of the dummy floating gate electrode 42 is not etched more reliably. be able to. For this reason, the bottom portion of the contact hole 62a that is out of the range is more securely accommodated within the wide region 15a of the auxiliary gate electrode 15, and the semiconductor substrate 1 around the wide region 15a of the auxiliary gate electrode 15 is located at the bottom portion of the contact hole 62a. It is possible to prevent exposure more accurately.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to, for example, a semiconductor device in which a wiring is connected to a gate electrode via a plug and a manufacturing method thereof.

It is a principal part top view in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 2 is a fragmentary cross-sectional view of the same semiconductor device as in FIG. 1 during the manufacturing process; FIG. 2 is a fragmentary cross-sectional view of the same semiconductor device as in FIG. 1 during the manufacturing process; FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIGS. 1 to 3; FIG. 5 is a fragmentary cross-sectional view of the same semiconductor device as in FIG. 4 during the manufacturing process; FIG. 6 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIGS. 4 and 5; FIG. 7 is an essential part plan view of the same semiconductor device as in FIG. 6 in manufacturing process. FIG. 7 is an essential part cross sectional view of the same semiconductor device as in FIG. 6 during a manufacturing step; FIG. 7 is an essential part cross sectional view of the same semiconductor device as in FIG. 6 during a manufacturing step; FIG. 10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIGS. 6 to 9; FIG. 11 is an essential part cross sectional view of the same semiconductor device as in FIG. 10 during a manufacturing step; 12 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIGS. 10 and 11; FIG. FIG. 13 is an essential part cross sectional view of the same semiconductor device as in FIG. 12 during a manufacturing step; FIG. 13 is an essential part cross sectional view of the same semiconductor device as in FIG. 12 during a manufacturing step; FIG. 15 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIGS. 12 to 14; FIG. 16 is an essential part cross sectional view of the same semiconductor device as in FIG. 15 during a manufacturing step; FIG. 16 is an essential part cross sectional view of the same semiconductor device as in FIG. 15 during a manufacturing step; FIG. 18 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIGS. 15 to 17; FIG. 19 is an essential part cross sectional view of the same semiconductor device as in FIG. 18 during a manufacturing step; FIG. 19 is an essential part cross sectional view of the same semiconductor device as in FIG. 18 during a manufacturing step; FIG. 19 is an essential part cross sectional view of the same semiconductor device as in FIG. 18 during a manufacturing step; FIG. 22 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIGS. 18 to 21; FIG. 23 is an essential part cross sectional view of the same semiconductor device as in FIG. 22 during a manufacturing step; FIG. 23 is an essential part cross sectional view of the same semiconductor device as in FIG. 22 during a manufacturing step; FIG. 25 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIG. 24; FIG. 23 is an essential part cross sectional view of the same semiconductor device as in FIG. 22 during a manufacturing step; FIG. 27 is an essential part plan view of a semiconductor device in a manufacturing process following the manufacturing process in FIGS. 22 to 26; FIG. 28 is an essential part cross sectional view of the same semiconductor device as in FIG. 27 during a manufacturing step; FIG. 29 is a fragmentary plan view of the semiconductor device during a manufacturing step following that of FIGS. 27 and 28; FIG. 30 is an essential part plan view of the same semiconductor device as in FIG. 29 in manufacturing process; FIG. 30 is an essential part plan view of the same semiconductor device as in FIG. 29 in manufacturing process; FIG. 30 is an essential part cross sectional view of the same semiconductor device as in FIG. 29 during a manufacturing step; FIG. 30 is an essential part cross sectional view of the same semiconductor device as in FIG. 29 during a manufacturing step; FIG. 30 is an essential part cross sectional view of the same semiconductor device as in FIG. 29 during a manufacturing step; FIG. 30 is an essential part cross sectional view of the same semiconductor device as in FIG. 29 during a manufacturing step; FIG. 30 is an essential part cross sectional view of the same semiconductor device as in FIG. 29 during a manufacturing step; FIG. 3 is a circuit diagram of a principal part during a data write operation of the semiconductor device according to one embodiment of the present invention; FIG. 38 is a fragmentary cross-sectional view of the semiconductor device during a data write operation of FIG. 37; It is a principal part circuit diagram at the time of the data read-out operation | movement of the semiconductor device which is one embodiment of this invention. FIG. 40 is a fragmentary cross-sectional view of the semiconductor device during a data read operation in FIG. 39; It is principal part sectional drawing of the semiconductor device at the time of data erasing operation | movement. It is a principal part top view in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 43 is an essential part cross sectional view of the same semiconductor device as in FIG. 42 during a manufacturing step; FIG. 44 is an essential part cross sectional view of the semiconductor device during a manufacturing step following the manufacturing step of FIG. 43; FIG. 45 is an essential part cross sectional view of the semiconductor device during a manufacturing step following the manufacturing step of FIG. 44; It is a principal part top view in the manufacturing process of the semiconductor device of a comparative example. FIG. 47 is an essential part cross sectional view of the same semiconductor device as in FIG. 46 during a manufacturing step; FIG. 48 is an essential part cross sectional view of the semiconductor device during a manufacturing step following the manufacturing step of FIG. 47; FIG. 49 is an essential part cross sectional view of the semiconductor device during a manufacturing step following the manufacturing step of FIG. 48;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation | separation area | region 3 Active area | region 3a Rectangular area | region 3b Strip | belt-shaped area | region 3c Connection part 4 P-type well 6 N-type semiconductor area 6a area | region 7 area | region 8, 9 Gate insulating film 11 Conductive film 12, 13 Insulating film 15, G0 G3 Auxiliary gate electrode 15a Wide region 15c Wiring part 16 Side surface 17 Groove 21 Side wall insulating film 22 Side surface 23 Groove 25 Conductive film 31 Insulating film 32, 33 Conductive film 34, WL Word line 41 Floating gate electrode 42 Dummy floating gate electrode 45 Gate electrode 51 n ⁻ type semiconductor region 53 Insulating film 55 n ⁺ type semiconductor region 61 Insulating film 62, 62 a Contact hole 63 Plug 63 a Barrier film 63 b Tungsten film 64 Wiring 81, 82 Insulating film 83, 84 Upper surface 85 Side surface 86, 87 End Portion 88 directly above 91, RP1, RP2 resist pattern 92 opening 142 dummy floating The gate electrode 185 side

Claims (18)

A semiconductor substrate;
A first conductor portion formed on the semiconductor substrate;
A second conductor formed on the semiconductor substrate and adjacent to the first conductor through an insulating film;
A first insulating film formed on the semiconductor substrate so as to cover the first and second conductor portions;
An opening formed in the first insulating film and exposing the first conductor portion at a bottom thereof;
A third conductor portion formed in the opening and connected to the first conductor portion at a bottom thereof;
A wiring formed on the first insulating film and electrically connected to the third conductor portion;
Have
The upper surface of the second conductor portion is higher than the upper surface of the first conductor portion,
The first conductor portion is located at a position where an upper surface end portion of the second conductor portion coincides with a position directly above the end portion of the first conductor portion or directly above an end portion of the first conductor portion. In the side position,
2. The semiconductor device according to claim 1, wherein the second conductor portion is a dummy conductor portion that is floating in potential . The semiconductor device according to claim 1,
The semiconductor device, wherein the second conductor portion has a tapered shape. The semiconductor device according to claim 1,
The side surface of the second conductor portion facing the first conductor portion is perpendicular to the main surface of the semiconductor substrate so that the upper portion is closer to the first conductor portion side than the lower portion. A semiconductor device characterized by being inclined. The semiconductor device according to claim 1,
The semiconductor device, wherein the second conductor portion is formed on the semiconductor substrate via a second insulating film. The semiconductor device according to claim 1,
The semiconductor device, wherein the first conductor portion is formed integrally with a first gate electrode formed on the semiconductor substrate via a first gate insulating film. The semiconductor device according to claim 5.
A second insulating film exists between the second conductor portion and the semiconductor substrate;
The semiconductor device, wherein the second insulating film is thicker than the first gate insulating film. The semiconductor device according to claim 5.
The semiconductor device, wherein the second conductor portion is disposed on the semiconductor substrate so as to surround the first conductor portion. The semiconductor device according to claim 1,
The first conductor portion is formed of a part of a gate electrode;
The semiconductor device, wherein the second conductor portion is formed between the first conductor portion and another gate electrode. The semiconductor device according to claim 1,
The semiconductor device, wherein the third conductor portion is a plug. The semiconductor device according to claim 1,
The semiconductor device, wherein the opening has a tapered shape. The semiconductor device according to claim 1,
A non-volatile memory floating gate electrode formed on the semiconductor substrate;
The semiconductor device according to claim 1, wherein the second conductor portion is formed of a conductor layer that is the same layer as the floating gate electrode. The semiconductor device according to claim 11.
The semiconductor device according to claim 1, wherein the floating gate electrode is a floating gate electrode for charge storage. The semiconductor device according to claim 11 .
There is a second insulating film between the second conductor part and the semiconductor substrate,
There is a third insulating film between the floating gate electrode and the semiconductor substrate,
The semiconductor device, wherein the second insulating film is thicker than the third insulating film. The semiconductor device according to claim 1,
A plurality of first gate electrodes formed on the semiconductor substrate in a state extending in a first direction along the main surface of the semiconductor substrate;
A semiconductor device, wherein at least one of the plurality of first gate electrodes integrally has the first conductor portion at one end in the extending direction thereof. The semiconductor device according to claim 14 .
The plurality of first gate electrodes include a first type of the first gate electrode in which one end portion in the extending direction is integrally connected to each other, and a second type of the first type of gate electrode that extends independently of each other without being connected. The first gate electrode;
The semiconductor device according to claim 1, wherein the first conductor portion is included in the second type of the first gate electrode. The semiconductor device according to claim 14 .
The plurality of first gate electrodes include a first type of the first type in which one end is integrally connected to each other by a fourth conductor portion extending in a second direction intersecting the first direction. A gate electrode and a second type of the first gate electrode extending in the first direction independently of each other without being connected;
The first gate electrode of the second type has the first conductor portion;
The semiconductor device, wherein the second conductor portion is formed between the first conductor portion and the fourth conductor portion or the first type of the first gate electrode. The semiconductor device according to claim 14 .
A plurality of second gate electrodes formed on the semiconductor substrate so as to intersect the plurality of first gate electrodes in a state extending in a second direction intersecting the first direction;
And a plurality of floating gate electrodes formed on the semiconductor substrate at positions where the plurality of second gate electrodes overlap in a plane between adjacent ones of the plurality of first gate electrodes. Semiconductor device. The semiconductor device according to claim 17.
The semiconductor device according to claim 1, wherein the second conductor portion is formed of a conductor layer that is the same layer as the floating gate electrode.

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