JP4728772B2 - Delay profile generation circuit and method thereof, and receiver and program - Google Patents

Description

  The present invention relates to a delay profile generation circuit and method, and a receiver and program using the circuit, and more particularly to a delay profile generation method suitable for use in a digital FPU (Field Pick Up) receiver in a microwave communication system.

  Conventionally, in a receiver in a CDMA (Code Division Multiple Access) communication system, when adding in-phase continuous data for accurate delay profile measurement (delayed wave path detection), the addition is performed. Different numbers are used to obtain a plurality of data, and based on the obtained data, the power value of the received signal or the ratio between the power of the received signal and the noise power is detected, and the detected power There is a technique for adaptively changing the number of data to be added in phase according to a fading frequency by comparing values or power ratio values or determining temporal changes thereof (see, for example, Patent Document 1). .

  In the case of so-called static radio propagation conditions without fading, the path detection capability improves as the number of in-phase additions increases, so that the number of power additions can be reduced, and thus the detection time is shortened. However, when there is a level fluctuation due to fading, the reception signal point changes, and thus there is a problem that the effect of the in-phase addition is reduced.

  In view of this, a technique has been proposed for level fluctuation due to fading, which improves the in-phase addition effect and improves the path detection characteristics by performing weighting before adding the correlation values in-phase (see, for example, Patent Document 2). reference).

JP 2001-274724 A JP 2005-109541 A

The conventional path search technique described above is a technique for a receiver in a CDMA mobile communication system. In a digital microwave mobile communication system, a BER (Bit Error Rate) of a demodulator due to the influence of a delayed wave is used. ) Is very large, and deterioration due to the influence of the pre-delayed wave is a serious problem. In the conventional analog communication operation mode, the antenna direction is adjusted so that the reception level is maximized. However, in the case of digital communication, the demodulator BER is not always the best depending on the size of the reception level. .

  In the above-described CDMA receiver, as disclosed in Patent Documents 1 and 2, etc., a delay profile circuit is already provided. However, a single carrier QAM (Quadrature Amplitude Modulation) digital FPU of a digital microwave mobile communication system is provided. In the receiving apparatus, no delay profile circuit is provided.

  Therefore, when the conventional delay profile circuit described above is used in a single carrier QAM digital FPU receiver, accurate delay profile calculation is required to detect an accurate path timing, which increases the circuit scale and processing. There is a drawback that the load to be heavy is also heavy.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a delay profile generation circuit that can be used effectively as a criterion for antenna direction adjustment, a method thereof, and a receiver and a program using the same.

  Another object of the present invention is to use a delay profile generation circuit, a method thereof, and a delay profile generation circuit capable of observing a stable delay profile without an increase in circuit scale or load as an application of a delay profile monitor function for a digital receiver. It is to provide a receiver and a program.

The delay profile generation circuit according to the present invention includes:
A delay profile generation circuit in a receiver,
Correlation value calculating means for calculating a correlation value between a received signal and a reference signal periodically inserted in advance;
1 frame delay means;
And weighting means forming the weighting respectively the outputs of the correlation value and the one-frame delay means,
In addition to performing in-phase addition of these weighted outputs, addition means for outputting the correlation value after the in-phase addition to the one-frame delay means;
Power generation means for calculating the power of the correlation value after the in-phase addition by the addition means and outputting as a delay profile;
The number of peaks detected in each frame of the delay profile is detected, and the output of the correlation value calculating unit and the output of the one-frame delay unit are different from each other according to the number of peaks. and correlation monitoring means forming the control weighting coefficients seen including,
The correlation monitoring means gradually increases the weighting coefficient W0 of the output of the one-frame delay means and gradually decreases the weighting coefficient W1 of the output of the correlation value calculating means as the number of detection times of the peak increases. It is characterized by.

The delay profile generation method according to the present invention includes:
A method for generating a delay profile in a receiver, comprising:
A correlation value calculating step for calculating a correlation value between the received signal and a reference signal periodically inserted in advance;
One frame delay step;
A weighting step of forming a weighting respectively the output of the one-frame delay step and said correlation value,
An addition step of performing in-phase addition of the weighted outputs and outputting the correlation value after the in-phase addition to the one-frame delay step;
A powerization step of calculating the power of the correlation value after the in-phase addition in the addition step and outputting as a delay profile;
The number of peaks detected in each frame of the delay profile is detected, and the output of the correlation value calculating step and the output of the one-frame delay step are different from each other according to the number of peaks. and correlation monitoring step which forms the control weighting coefficients seen including,
In the correlation monitoring step, the weighting coefficient W0 of the output of the one-frame delay step is gradually increased and the weighting coefficient W1 of the output of the correlation value calculating step is gradually decreased as the number of detection of the peak increases. It is characterized by.

  A receiver according to the present invention is characterized by using the delay profile generation circuit described above.

The program according to the present invention is:
A program for causing a computer to execute a delay profile generation method in a receiver,
A correlation value calculation process for calculating a correlation value between a received signal and a reference signal periodically inserted in advance;
1 frame delay processing,
A weighting processing for forming the weighting respectively the output of the one-frame delay step and said correlation value,
An addition step of performing in-phase addition of the weighted outputs and outputting the correlation value after the in-phase addition to the one-frame delay process;
Power calculation processing for calculating the correlation value after the in-phase addition by the addition processing and outputting as a delay profile, and
The number of peaks detected in each frame of the delay profile is detected, and the output of the correlation value calculation process and the output of the one-frame delay process differ from each other according to the number of peaks. look including a correlation monitoring process which forms the control weighting coefficients,
In the correlation monitoring process, the weighting coefficient W0 of the output of the one-frame delay step is gradually increased and the weighting coefficient W1 of the output of the correlation value calculating step is gradually decreased as the number of detection of the peak increases. It is characterized by.

  According to the present invention, from the delay profile data obtained by calculating the delay profile from the received signal (the signal after quadrature demodulation), the previous ghost information (delay time and There is an effect that the D / U ratio (Desired to Undesired signal Ratio) and post-ghost information (delay time and D / U ratio) can be observed at a glance.

  In addition, according to the present invention, there is an effect that stable delay profile data can be output even if there is an instantaneously large correlation value due to the influence of noise or fading fluctuation. Further, in the delay profile calculation, it is possible to realize stable delay profile data by performing adaptive control so that the delay profile calculation value is averaged according to the peak detection of the obtained delay profile data. is there.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram of a delay profile circuit of the present invention, which is applied to a single carrier QAM (quadrature amplitude modulation) type digital FPU receiver. The delay profile circuit 10 according to the present invention shown in FIG. 1 obtains delay profile data obtained by calculating a delay profile in a reception environment from a received signal a1 (I and Q signals after orthogonal demodulation). From b1, in order to observe with a video monitor, an oscilloscope, etc., it outputs to the data converter circuit which is not illustrated according to a use.

Referring to FIG. 1, the delay profile circuit 10 calculates a correlation value between the real number data (I data) and the imaginary number data (Q data) as the input signal a1 and the reference signal periodically inserted in advance on the transmission side. Correlation circuit 11 to be calculated, weighting circuit 12 for weighting the correlation value output from correlation circuit 11 and the correlation value one frame before, correlation value of I data and correlation of Q data output from weighting circuit 12 An in-phase addition circuit 13 for improving the S / N ratio by performing in-phase addition, a delay circuit 14 for delaying the correlation value output from the in-phase addition circuit 13 by 1 frame and feeding back to the weighting circuit 12; The power generation circuit 15 that calculates the power value of the correlation value output from the addition circuit 13 and the peak of the delay profile b1 output from the power conversion circuit 15 are monitored. It is constituted by a correlation monitoring circuit 16 that controls the weighting factor of the weighting circuit 12.

  Next, the operation of the delay profile circuit 10 will be described in detail with reference to FIG. The correlation circuit 11 compares the phase of the real number data (I data) and the imaginary number data (Q data) of the input digital signal a1 with the reference signal periodically inserted in advance on the transmission side in symbol units. A correlation value is calculated.

  Since the weighting circuit 12 is not affected by instantaneous noise or fading fluctuation, each correlation value of I data and Q data output from the correlation circuit 11 and I data of one frame before output from the delay circuit 14 In addition, weighting multiplication of different ratios is performed on each correlation value of Q data.

The result of this multiplication is
“The correlation value of I data and Q data of one frame before × W0
= Weighted correlation value one frame before "
When,
“Correlation values of I data and Q data output from the correlation circuit 11 × W1
= Correlation value output from weighted correlation circuit 11 "
Respectively. Here, W0 is the weighting coefficient ratio (W0 <1) of the correlation value of the previous frame, and W1 is the weighting coefficient ratio (W1 <1) of the correlation value of the output of the correlation circuit 11.

  Since the weighting circuit 12 can provide sufficiently stable delay profile data with simple weighting, the hardware processing burden can be reduced.

  In the in-phase addition circuit 13, each correlation value of the I data and Q data output from the correlation circuit 11 weighted by the weighting circuit 12 and each correlation of the I data and Q data one frame before output from the delay circuit 14 In-phase addition with each value is performed. Thereby, the S / N ratio can be improved. In the delay circuit 14, the result of the in-phase addition is delayed by one frame and fed back to the weighting circuit 12.

  In the power generation circuit 15, since the instantaneous correlation value due to the influence of noise and fading fluctuation is already reduced by the calculation processing of the weighting circuit 12 and the in-phase addition circuit 13 for each frame, here, for each symbol, Then, a simple power value calculation “I square + Q square” is performed, and the calculation result is converted into “W (watt) → dB (decibel)”, and the delay profile data b1 at each delay time is converted. Will be generated.

The delay profile data b1 indicates the power value (decibel) at each delay time. For example, in the case of a video monitor, multiplexing with a video signal, and in the case of an oscilloscope , multiplexing with a trigger signal is performed. Therefore, the data is output to a data conversion circuit (not shown).

  The correlation monitoring circuit 16 detects an effective peak while monitoring whether the power level of the delay profile data for one frame output from the power circuit 15 is greater than or less than a threshold, and according to the number of peak detections. Thus, the weighting coefficient of the weighting circuit 12 is controlled.

If no peak is detected (for example, no input signal state or low electric field state), the correlation value one frame before output from the delay circuit 14 is not detected. 11 is controlled so that only the correlation value output from the controller 11 is weighted.

  Next, when a peak is detected, the number of times the peak is detected is counted for each frame, and as the number of peak detection counts increases, the number of frames one frame before output from the delay circuit 14 increases. Since the correlation value is averaged in-phase added for each frame, it is considered that stability and reliability are increased.

  Thus, variable control of the weighting coefficients is performed on the correlation value one frame before output from the delay circuit 14 and the correlation value output from the correlation circuit 11 according to the count number. As a variable control method of the weighting coefficient, as the number of peak detection counts increases, the weighting coefficient W0 of the correlation value one frame before output from the delay circuit 14 is gradually increased, while the correlation circuit It is assumed that the weighting coefficient W1 of the 11 output correlation values is controlled to gradually decrease. For example, in the initial state and the count start time, W0 <W1, and from the point where the number of detections gradually increases and it can be determined that the stable state is set, W0> W1 is set.

  W0 is a weighting coefficient ratio of the correlation value of the previous frame, and W1 is a weighting coefficient ratio of the correlation value of the output of the correlation circuit 11. As described above, each weighting coefficient is W0 <1, W1 <1.

In addition, when there is an influence of noise or fading fluctuation, since there is no correlation between the received signal and noise, stable correlation values are rarely observed continuously. As a result, the influence on the delay profile data b1 is reduced. Therefore, the delay profile circuit 10 can generate stable delay profile data b1 even if there is an instantaneously large correlation value due to the influence of noise or fading fluctuation.

  It is obvious that the operation of each functional block described above can be configured such that the operation procedure is stored in advance in a recording medium such as a ROM and is read by a computer and executed.

It is a functional block diagram which shows embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Delay profile circuit 11 Correlation circuit 12 Weighting circuit 13 In-phase addition circuit 14 Delay circuit 15 Electric power generation circuit 16 Correlation monitoring circuit

Claims (8)

A delay profile generation circuit in a receiver,
Correlation value calculating means for calculating a correlation value between a received signal and a reference signal periodically inserted in advance;
1 frame delay means;
And weighting means forming the weighting respectively the outputs of the correlation value and the one-frame delay means,
In addition to performing in-phase addition of these weighted outputs, addition means for outputting the correlation value after the in-phase addition to the one-frame delay means;
Power generation means for calculating the power of the correlation value after the in-phase addition by the addition means and outputting as a delay profile;
The number of peaks detected in each frame of the delay profile is detected, and the output of the correlation value calculating unit and the output of the one-frame delay unit are different from each other according to the number of peaks. and correlation monitoring means forming the control weighting coefficients seen including,
The correlation monitoring means gradually increases the weighting coefficient W0 of the output of the one-frame delay means and gradually decreases the weighting coefficient W1 of the output of the correlation value calculating means as the number of detection times of the peak increases. A profile generation circuit characterized by the above. 2. The profile according to claim 1 , wherein W0 <W1 <1 is set in an initial state or the detection start time of the peak, and 1>W0> W1 is set when the number of times of detection of the peak is increased. Generation circuit. 2. The received signal is a QAM modulated signal, and the correlation value is calculated and weighted for each of I and Q data after quadrature demodulation of the QAM modulated signal. 3. The profile generation circuit according to 2. A method for generating a delay profile in a receiver, comprising:
A correlation value calculating step for calculating a correlation value between the received signal and a reference signal periodically inserted in advance;
One frame delay step;
A weighting step for respectively weighting the correlation value and the output of the one-frame delay step;
An addition step of performing in-phase addition of the weighted outputs and outputting the correlation value after the in-phase addition to the one-frame delay step;
A powerization step of calculating the power of the correlation value after the in-phase addition in the addition step and outputting as a delay profile;
The number of peaks detected in each frame of the delay profile is detected, and the output of the correlation value calculating step and the output of the one-frame delay step are different from each other according to the number of peaks. A correlation monitoring step for controlling the weighting factor,
In the correlation monitoring step, the weighting coefficient W0 of the output of the one-frame delay step is gradually increased and the weighting coefficient W1 of the output of the correlation value calculating step is gradually decreased as the number of detection of the peak increases. A profile generation method characterized by the above. 5. The profile according to claim 4, wherein W0 <W1 <1 is set in the initial state and the detection start time of the peak, and 1>W0> W1 is set when the number of times of detection of the peak is increased. Generation method. 6. The received signal is a QAM modulated signal, and the correlation value is calculated and weighted for each of the I and Q data after the QAM modulated signal is quadrature demodulated. profile generation method according to. A receiver using the profile generation circuit according to claim 1. A program for causing a computer to execute a delay profile generation method in a receiver,
A correlation value calculation process for calculating a correlation value between a received signal and a reference signal periodically inserted in advance;
1 frame delay processing,
A weighting process for respectively weighting the correlation value and the output of the one-frame delay step;
An addition step of performing in-phase addition of the weighted outputs and outputting the correlation value after the in-phase addition to the one-frame delay process;
Power calculation processing for calculating the correlation value after the in-phase addition by the addition processing and outputting as a delay profile, and
The number of peaks detected in each frame of the delay profile is detected, and the output of the correlation value calculation process and the output of the one-frame delay process differ from each other according to the number of peaks. look including a correlation monitoring process which forms the control weighting coefficients,
In the correlation monitoring process, the weighting coefficient W0 of the output of the one-frame delay step is gradually increased and the weighting coefficient W1 of the output of the correlation value calculating step is gradually decreased as the number of detection of the peak increases. A program characterized by

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