JP4726227B2 - Buffer flow control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a buffer flow controller which can reduce a processing load and power consumption accompanied by the change of a frequency. <P>SOLUTION: A sampling part 6 samples data inputted at a second frequency to a first frequency of a standard value set in advance and outputs it to a writing part 2. The writing part 2 writes the input data into a buffer memory 1. A reading part 3 reads the data from the buffer memory 1. When a data quantity of the buffer memory 1 is not within a prescribed range, a control part 5 changes the first frequency of the sampling part to a maximum value or a minimum value fixed in advance. When the first frequency is the maximum value or the minimum value, the standard value is updated so that the switching period of the frequency may become long. Consequently, the processing load and power consumption accompanied by the change of the frequency can be reduced. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a buffer flow control device, and more particularly to a technique for writing / reading data to / from a buffer memory at different frequencies.

  Patent Document 1 discloses a technique for correcting jitter caused by a clock difference between devices when data is reproduced in real time between devices operating with independent clocks. In the technique described in Patent Document 1, the frequency of reading from the data buffer is set so that the amount of data stored in the data buffer of the receiving device is between the upper threshold A and the lower threshold B. It adjusts and samples the data read from the data buffer.

Japanese Patent Laid-Open No. 2004-221951

  However, the technique described in Patent Document 1 has a problem that when the clock error between devices is large, the frequency switching period is shortened, and the processing load and power consumption due to the frequency change are increased. In addition, the technique described in Patent Document 1 only takes into consideration when the clock error between devices is about ± 0.4 KHz, and is difficult to adapt when the clocks between devices are completely different. There was a problem. In addition, since a voltage controlled crystal oscillator is usually used as a method for adjusting the frequency, there is a problem in that the cost increases and the power consumption increases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a buffer flow control device that has a small processing load and low power consumption and changes the write frequency.

  A first aspect of the buffer flow control device according to the present invention includes a buffer memory, a writing unit that writes data to the buffer memory at a first frequency, a reading unit that reads data from the buffer memory, and the first A register in which at least three set values of a first value, a second value larger than the first value, and a third value smaller than the first value are recorded in advance as frequency set values of The first frequency is changed to the third value when the data amount of the buffer memory exceeds a predetermined upper limit value, and the data amount of the buffer memory falls below a predetermined lower limit value. A control unit that changes the frequency of 1 to the second value, and when the first frequency is the third value, the control unit updates the first value to a lower value than before. To the register And, when the first frequency is the second value, the control unit records in the register to update the first value higher than the previous value.

  A second aspect of the buffer flow control device according to the present invention is the buffer flow control device according to the first aspect, wherein data input at a second frequency is sampled into data of the first frequency. A sampling unit that outputs to the writing unit; and the sampling unit adds a value corresponding to the first frequency to a counter value, and the counter value is equal to or greater than a value corresponding to the second frequency. A counter unit that subtracts a value corresponding to the second frequency from the counter value, and the counter value after the addition and before the subtraction is greater than or equal to a value corresponding to the second frequency. And an output control unit that outputs the data to the writing unit.

  A third aspect of the buffer flow control device according to the present invention is the buffer flow control device according to the first aspect, wherein data input at a second frequency is sampled into data of the first frequency. A sampling unit that outputs to the writing unit; and the sampling unit adds a value corresponding to the first frequency to a counter value, and the counter value is equal to or greater than a value corresponding to the second frequency. A counter unit that subtracts a value corresponding to the second frequency from the counter value, and the counter value after the addition and before the subtraction is greater than or equal to a value corresponding to the second frequency. An output control unit that complements the data and outputs the complemented data to the writing unit.

  A fourth aspect of the buffer flow control device according to the present invention is the buffer flow control device according to the third aspect, wherein the complement is input at the second frequency based on the counter value. It is to perform linear interpolation on the data.

  A fifth aspect of the buffer flow control device according to the present invention is the buffer flow control device according to the third aspect, wherein the counter section divides a value corresponding to the first frequency by a desired numerical value. A value is added to the counter value, and the complementing is to accumulate a value obtained by dividing a difference value between two adjacent values of the data input at the second frequency by the numerical value.

  According to the first aspect of the buffer flow control device of the present invention, when the first frequency is the third value, the first value is updated to a lower value, and the first frequency is the second value. When it is a value, the first value is updated to a higher value. Therefore, when the first frequency is the first value, it is possible to lengthen the period in which the data amount of the buffer memory is within the prescribed upper limit value and lower limit value range. Therefore, it is possible to reduce the processing load and power consumption of the buffer flow control device associated with changing the first frequency to the second or third value.

  According to the second aspect of the buffer flow control device of the present invention, even if the frequency of data input to the buffer flow control device and the frequency of the reading unit are significantly different, the sampling unit is input at the second frequency. Since the data to be processed is sampled at the first frequency, the frequency of the writing unit and the reading unit can be made substantially equal. Further, as compared with the case where a voltage controlled crystal oscillator is used for changing the frequency, an increase in cost and an increase in power consumption can be reduced.

  According to the third aspect of the buffer flow control device of the present invention, the output control unit complements the input data. Therefore, discontinuity of output data can be eliminated.

  According to the fourth aspect of the buffer flow control device of the present invention, the output control unit performs linear interpolation based on the counter value. Therefore, discontinuity of output data can be eliminated.

  According to the fifth aspect of the buffer flow control device of the present invention, data input at the second frequency can be oversampled at a frequency obtained by multiplying the second frequency by a desired numerical value. Therefore, discontinuity of output data can be eliminated.

(First embodiment)
FIG. 1 shows a schematic diagram of a data receiving unit including the buffer flow control apparatus according to the first embodiment of the present invention and a digital broadcast receiver including a reproducing unit. In FIG. 1, only the portion related to the buffer flow of audio data is schematically shown for simplicity. Actually, the receiver includes a processing unit that converts data into a desired format.

  Specifically, the buffer flow control device 101 included in the data receiving unit 100 includes a buffer memory 1, a writing unit 2, a reading unit 3, a switching unit 4, a control unit 5, and a sampling unit 6.

  The buffer memory 1 has a configuration of, for example, 1600 words × 2 banks × 2ch, and includes a memory bank 10 and a memory bank 11. As will be described later, while data is being written to one memory bank, data is read from the other memory bank.

  For example, data is input to the sampling unit 6 at a frequency of 48.000 KHz from a transmitter (not shown). The sampling unit 6 samples the data input at the frequency of 48.000 KHz, for example, at a frequency of 47.605 KHz and outputs it to the writing unit 2.

  The writing unit 2 writes the input data into the buffer memory 1 at the frequency (47.605 KHz) sampled by the sampling unit 6.

  The reading unit 3 operates at an operating frequency higher than at least the maximum value of the sampling frequency of the sampling unit 6 (the maximum value will be described later), reads data from the buffer memory 1, and transmits the data to the receiver 200. When a transmission request (transmission request will be described later) is received from the receiver 200, a flag F is output to the control unit 5.

  The switching unit 4 connects the writing unit 2 and one of the memory banks 10 and 11, and connects the reading unit 3 and one of the memory banks 10 and 11.

  The control unit 5 controls the switching unit 4 to connect the writing unit 2 and the memory bank 10 or 11 and to connect a memory bank different from the memory bank connected to the writing unit 2 and the reading unit 3. . When receiving the flag F from the reading unit 3, the control unit 5 switches the memory bank to which the writing unit 2 is connected and switches the memory bank to which the reading unit 3 is connected.

  For example, the control unit 5 connects the memory bank 10 and the writing unit 2, the memory bank 11 and the reading unit 3, and receives the flag F from the reading unit 3, and controls the switching unit 4 to write to the memory bank 11. Unit 2, memory bank 10 and readout unit 3 are connected to each other. As described above, the control unit 5 controls the switching unit 4 to alternately and alternately switch the memory bank for writing data and the memory bank for reading data.

  The control unit 5 includes a register 51. In the register 51, the standard value (first value), the maximum value (second value), and the minimum value (third value) are recorded in advance as the sampling frequency by the sampling unit 6 (= the frequency of the writing unit 2). Has been.

  When the control unit 5 receives the flag F from the reading unit 3, the control unit 5 acquires the amount of data written to the buffer memory 1 from the writing unit 2, and when the received data amount is not within the predetermined range, The control unit 5 notifies the sampling unit 6 to change the sampling frequency (= frequency of the writing unit 2) to any one of the maximum value, the standard value, and the minimum value set in the register 51. This point will be described later.

  In addition, the control unit 5 can update and record the standard value set in the register 51 with a new value. This point will be described later.

  On the other hand, the receiver 200 includes a buffer memory 20, a reading unit 23, and a control unit 25. The buffer memory 20 has a capacity equal to or larger than the capacity of the memory banks 10 and 11 and stores data transmitted from the transmitter 100. The reading unit 23 reads data from the buffer memory 20 with a frequency of 47.605 KHz, for example, and outputs the data to a processing unit (not shown). The control unit 25 transmits a transmission request to the transmitter 100 when, for example, 1600 words of free space are generated in the buffer memory 20 by the reading operation of the reading unit 23.

  Here, the frequency 47.605 KHz of the writing unit 2 is obtained by sampling data having a frequency of 48.000 KHz based on the clock of the transmitter, and the frequency 47.605 KHz of the reading unit 23 is based on the clock of the receiver. Therefore, there is a difference between the frequencies.

  Next, the operation of this system will be described. FIG. 2 is a flowchart showing the operation of the buffer flow control device provided in the transmitter, and FIG. 3 is a flowchart showing the operation of the receiver.

  First, in FIG. 2, in step S <b> 1, the sampling unit 6 samples data input at a frequency of 48.000 KHz at a frequency of 47.605 KHz and outputs it to the writing unit 2. The writing unit 2 writes the input data to the connected memory bank. Note that the writing unit 2 writes in order from the address value 0 of the memory bank.

  On the other hand, the reading unit 3 is connected to a memory bank different from the memory bank connected to the writing unit 2 by the switching unit 4 and the control unit 5, and operates at an operating frequency of 6 MHz, for example. Is transmitted to the receiver 200.

  Next, when the reading unit 3 receives a transmission request from the receiver 200 in step S <b> 2, the reading unit 3 outputs a flag F to the control unit 5.

  Next, in step S3, the control unit 5 that has received the flag F acquires the amount of data that the writing unit 2 has written to the memory bank at that time. Here, for example, as the data amount, the last address value written in the memory bank by the writing unit 2 is acquired.

  Next, in step S4, the control unit 5 determines whether the frequency of the writing unit 2 is a maximum value, a standard value, or a minimum value. Note that the maximum value and the minimum value of the frequency of the writing unit 2 are the maximum value and the minimum value of the frequency range guaranteed by the clock of the receiver, respectively.

  If the frequency of the writing unit 2 is a standard value, in step S5, the control unit 5 determines whether or not the acquired address value exceeds the first upper limit threshold value. Here, for example, the address value 1500 is set as the first upper limit threshold value. If the acquired address value exceeds 1500, the control unit 5 changes the frequency of the writing unit 2 to the minimum value (for example, 47.000 KHz) set in the register 51 in step S6. Specifically, the control unit 5 notifies the sampling unit 6 to sample at the minimum frequency. Upon receiving the notification, the sampling unit 6 samples the input data at the minimum frequency and outputs the sampled data to the writing unit 2.

  Next, in step S9, the control unit 5 controls the switching unit 4 to switch the memory bank to which the writing unit 2 and the reading unit 3 are connected.

  If the address value acquired in step S5 does not exceed the first upper limit threshold value, in step S7, the control unit 5 determines whether the acquired address value is less than the first lower limit threshold value. Judging. Here, for example, the address value is 100 as the first lower limit threshold value. If the acquired address value is less than 100, the control unit 5 changes the frequency of the writing unit 2 to the maximum value (for example, 47.609 KHz) set in the register 51 in step S8. Specifically, the control unit 5 notifies the sampling unit 6 to sample at the maximum frequency. The sampling unit 6 that has received the notification samples the input data at the maximum frequency and outputs the sampled data to the writing unit 2. Then, after step S9, step S1 is executed again.

  When the frequency of the writing unit 2 is the maximum value in step S4, in step S10, the control unit 5 determines whether or not the acquired address value exceeds the second upper limit threshold value. Note that the second upper limit threshold value is smaller than the first upper limit threshold value, and is, for example, an address value 1200 here. If the acquired address value exceeds 1200, the control unit 5 updates the standard value set in the register 51 to a higher frequency in step S11. For example, the standard value is updated from 47.605 KHz to 47.606 KHz. Here, as the update of the standard value, only the lower-order digits (the lower-order bits of the register) of the standard value may be changed, and the upper-order digits (the upper-order bits of the register) may be fixed. In this case, the capacity of the register 51 can be reduced.

  Next, in step S12, the control unit 5 changes the frequency of the writing unit 2 to the updated standard value. Specifically, the control unit 5 notifies the sampling unit 6 to perform sampling at the standard value frequency. The sampling unit 6 that has received the notification samples the input data at the frequency of the standard value and outputs the sampled data to the writing unit 2. Then, after step S9, step S1 is executed again.

  If the address value acquired in step S10 does not exceed the second upper limit threshold value, step S1 is executed again via step S9.

  When the frequency of the writing unit 2 is the minimum value in step S4, in step S13, the control unit 5 determines whether the acquired address value is below the second lower limit threshold value. Note that the second lower limit threshold value is larger than the first lower limit threshold value, and is, for example, an address value 400 here. If the acquired address value is lower than 400, the control unit 5 updates the standard value set in the register 51 to a lower frequency in step S14. For example, the standard value is updated from 47.605 KHz to 47.604 KHz.

  Next, in step S15, the control unit 5 changes the frequency of the writing unit 2 to the updated standard value. Specifically, the control unit 5 notifies the sampling unit 6 to perform sampling at the standard value frequency. The sampling unit 6 that has received the notification samples the input data at the frequency of the standard value and outputs the sampled data to the writing unit 2. Then, after step S9, step S1 is executed again.

  If the address value acquired in step S13 is not less than the second lower limit threshold value, step S1 is executed again via step S9.

  Next, the operation of the receiver 200 shown in FIG. 3 will be described. In step S21, the data transmitted from the transmitter 100 is stored in the buffer memory 20 having a capacity of 1600 words, for example. Next, in step S <b> 22, the reading unit 23 reads data from the buffer memory 20 at a frequency of 47.605 KHz. Next, in step S23, the control unit 25 determines whether or not the buffer memory 20 has a free space of 1600 words or more, for example. If there is free space of 1600 words or more in the buffer memory, the control unit 25 outputs a transmission request to the transmitter 100 in step S24. If there is no free space of 1600 words or more in the buffer memory, step S23 is executed again.

  Next, the amount of data written to the buffer memory 1 by the above operation will be described. For example, when the reading unit 3 operating at a frequency of 6 MHz reads 800 words of data written in the memory bank 11 and transmits the data to the receiver 200 (step S1), the transmitted 800 words of data is stored in the buffer memory 20. Stored (step S21), the reading unit 23 reads data from the buffer memory 20 at a frequency of 47.605 KHz (step S22). At this time, the writing unit 2 writes data in the memory bank 10 at a frequency of 47.605 KHz (step S1).

  The receiver 200 reads the 800-word data from the buffer memory 20, and when a free space of 1600 words or more is generated in the buffer memory 20, a transmission request is transmitted to the transmitter 100 (step S23, S24). In the transmitter 100 that has received the transmission request, the last address value written in the memory bank 10 by the writing unit 2 at that time is confirmed (steps S2 and S3). That is, in practice, the amount of data written to the memory bank 10 by the writing unit 2 is confirmed while the reading unit 23 reads 800 words of data written to the memory bank 11 (step S3).

  For example, when the frequency of the writing unit 2 is higher than the frequency of the reading unit 23, the writing unit 2 writes a data amount larger than 800 words into the memory bank 10, so that the address value is larger than 800. On the other hand, when the frequency of the writing unit 2 is lower than the frequency of the reading unit 23, the writing unit 2 writes a data amount smaller than 800 words into the memory bank 10, so the address value is smaller than 800.

  Here, when the reading unit 3 receives the transmission request (when the flag F is given to the control unit 5), transition of the address value written last by the writing unit 2 is illustrated in FIGS. 4 shows a case where the difference between the frequency of the writing unit 2 and the reading unit 23 is small, FIG. 5 shows a case where the frequency of the writing unit 2 is higher than the frequency of the reading unit 23, and FIG. The case where it is lower than the frequency of the part 23 is shown.

  As illustrated in FIG. 4, when the difference between the frequency of the writing unit 2 and the frequency of the reading unit 23 is small, the operation of the buffer flow control device includes steps S1 to S5, S7, and S9 in FIG. Run in order. In this case, overflow or underflow of the buffer memory 1 does not occur, and data transfer through the buffer memory 1 is executed smoothly.

  As illustrated in FIG. 5, when the frequency of the writing unit 2 is higher than the frequency of the reading unit 23, the address value increases as described above. When the address value exceeds the first upper limit threshold (time tA), the frequency of the writing unit 2 is changed to the minimum value (for example, 47.000 KHz) (step S6). Thereafter, the frequency of the writing unit 2 becomes lower than the frequency of the reading unit 23, so that the address value when the flag F is given to the control unit 5 decreases. When the address value falls below the second lower limit threshold (time tB), the standard value of the frequency of the writing unit 2 is updated to a lower value (step S14), and the frequency of the writing unit 2 is updated. It is changed to a later standard value (step S15).

  When the updated frequency of the writing unit 2 is still higher than the frequency of the reading unit 23, the address value increases again. However, since the difference in frequency between the writing unit 2 and the reading unit 23 is smaller than before the update, the period until the first upper limit threshold is exceeded again becomes longer, and the frequency switching period can be lengthened. .

  Next, as illustrated in FIG. 6, when the frequency of the writing unit 2 is lower than the frequency of the reading unit 23, the address value decreases as described above. When the address value falls below the first lower threshold (time tC), the frequency of the writing unit 2 is changed to the maximum value (for example, 47.609 KHz) (step S8). Thereafter, since the frequency of the writing unit 2 becomes higher than the frequency of the reading unit 23, the address value when the flag F is given to the control unit 5 increases. When the address value exceeds the second upper limit threshold (time tD), the standard frequency value of the writing unit 2 is updated to a higher value (step S11), and the frequency of the writing unit 2 is updated. It is changed to the later standard value (step S12).

  When the updated frequency of the writing unit 2 is still lower than the frequency of the reading unit 23, the address value decreases again. However, since the frequency difference between the writing unit 2 and the reading unit 23 is smaller than before the update of the standard value, the period until the first lower limit threshold is exceeded again becomes longer, and the frequency switching period is lengthened. be able to.

  In the case illustrated in FIG. 5, when the frequency of the writing unit 2 in the updated standard value is lower than the frequency of the reading unit 23, the address value decreases after time tB, and the address value becomes the first value. When the frequency falls below the lower threshold, the frequency of the writing unit 2 is changed to the maximum value (step S8).

  In the case illustrated in FIG. 6, when the frequency of the writing unit 2 in the updated standard value becomes higher than the frequency of the reading unit 23, the address value increases after time tD, and the address value becomes the first value. Is exceeded, the frequency of the writing unit 2 is changed to the minimum value (step S6).

  As described above, according to the buffer flow control apparatus according to the first embodiment, overflow and underflow of the buffer memory 1 due to the difference in frequency between the writing unit 2 and the reading unit 23 can be prevented. Further, when the standard value of the frequency of the writing unit 2 is higher than the frequency of the reading unit 23, the standard value is updated to be lower, and when the standard value of the frequency of the writing unit 2 is lower than the frequency of the reading unit 23 Since the standard value is updated higher, the frequency switching period can be lengthened, and the processing load and power consumption associated with the frequency change can be reduced. In addition, since sampling can be performed at an arbitrary frequency by the sampling unit 6, the present invention can be applied even if the frequency of the transmitter 100 and the frequency of the receiver 200 are greatly different.

  Also, how much the standard value is changed by updating the standard value may be determined based on the absolute value of the slope of the address value when operating with the standard value before the update. For example, when the absolute value of the slope of the address value is large, the standard value is greatly changed, and when the absolute value of the slope of the address value is small, the standard value is changed small. In this case, the frequency switching period can be lengthened efficiently.

  Further, since the clock difference between the transmitter 100 and the receiver 200 can be absorbed without receiving a reference clock from the receiver 200, the present invention is applied even to a communication system that does not have a reference clock supply function. be able to.

  In the first embodiment, the update of the standard value is executed when the second upper limit threshold is exceeded or when it falls below the second lower limit threshold. However, the present invention may be executed while the frequency is at the maximum value or the minimum value.

  In the first embodiment, the maximum value and the minimum value, which are set values of the frequency of the writing unit 2, are not updated. However, the present invention is not limited to this and may be updated. For example, the maximum value may be updated to a lower value when the absolute value of the slope of the address value when operating at the standard value is small. In this case, it is possible to lengthen the period from when the frequency is changed from the standard value to the maximum value until the frequency is changed again to the standard value. The same applies to the minimum value.

(Second Embodiment)
A buffer flow control apparatus according to a second embodiment of the present invention will be described. In the second embodiment, a specific configuration of the sampling unit 6 in the buffer flow control device according to the first embodiment is described. FIG. 7 is a schematic diagram of a system including a transmitter including a buffer flow control device according to the second embodiment and a receiver. In addition, the same code | symbol has shown the same or an equivalent part, and the description which overlaps is abbreviate | omitted.

  The sampling unit 6 includes a counter circuit 61 and an output control unit 62, and samples data input at a frequency of 48.000 KHz into data at a frequency of 47.605 KHz.

  Hereinafter, functions and operations of the counter circuit 61 and the output control unit 62 will be described. FIG. 8 is a diagram illustrating an example of the counter value K obtained by the counting operation of the counter circuit 61. Each time interval between times t0, t1,... Is a time corresponding to 48.000 KHz. That is, data is input to the sampling unit 6 at timings t0, t1, t2,.

  The counter circuit 61 adds “47605” (corresponding to the frequency of the writing unit 2) to the counter value K every time t0, t1,. When the counter value K is equal to or greater than “48000” (corresponding to the frequency of the data input to the sampling unit 6), the output control unit 62 outputs the data to the writing unit 2, and the counter value K is changed to “48000”. Is subtracted. When the counter value K is less than “48000”, the output control unit 62 deletes (thinens) the input data without outputting the data, and keeps the counter value K as it is. Here, description will be made assuming that the initial value of the counter value K is 0.

  Specifically, as shown in FIG. 8, at time t0, the counter value K becomes “47605”. At this time, since the counter value K is less than “48000”, the output control unit 62 does not output the input data and deletes it. Do (thin out). At time t1, the counter value K becomes “95210” (= 47605 + 47605). At this time, since the counter value K is “48000” or more, the output control unit 62 outputs the input data to the writing unit 2. The counter value K is “47210” (= 47605 + 47605-48000). Thereafter, the counter value K is decremented by “395” (= 48000-47605). At time t120, the counter value K becomes “205”, and at time t121, “47605” is added to the counter value K “205” to become “47810”. At this time, since the counter value K is less than “48000”, the output control unit 62 deletes (thinens out) the input data without outputting it.

  That is, out of 48000 data (frequency 48.000 KHz) per second, data is thinned out every 121 or 122 (integers before and after 48000/395), and 47605 data (frequency 47.605 KHz) per second. ) Data is output.

  Then, in any one of steps S6, S8, S12, and S15 in FIG. 2, when the frequency of the writing unit 2 is changed, a value corresponding to the changed frequency value may be added to the counter value K. For example, when the frequency of the writing unit 2 is set to the maximum value (47.609 KHz), “47609” may be added to the counter value K every time t0, t1,. Similarly, when the frequency of the writing unit 2 is set to the minimum value (47.000 KHz), it is only necessary to add “47000” to the counter value K at each time t0, t1,.

  Therefore, since the sampling unit 6 can adjust the sampling frequency without using the voltage controlled crystal oscillator, it is possible to avoid an increase in cost and power consumption compared to the case where the voltage controlled crystal oscillator is used.

(First modification)
In the sampling unit 6 in the second embodiment, 395 data are simply thinned out from 48000 data per second at approximately equal intervals, and sampling is performed to 47605 data per second. Discontinuities occur before and after the data.

  Therefore, when outputting data, the output control unit 62 outputs the data after linear interpolation based on the counter value K. FIG. 9 shows an example in which the 5-sample point data A20 to A24 input to the sampling unit 6 is reduced and corrected to 4-sample point data B20 to B23. Actually, the data of 48000 sample points is corrected to be reduced to 47605 sample points. However, for the sake of simplicity, the linear interpolation correction will be described with reference to FIG. For example, the value of the data B21 is given as the following expression (1) using the values of the data A21 and A22 and the distances x3 and x4.

  Note that the ratio of the distances x3 and x4 can be obtained based on the counter value K. This will be specifically described below. FIG. 10 shows the distance between adjacent data A and data B and the counter value K. The distance between the data A20 to A23 and the distance between the data B20 to B24 are 4k and 5k (k: ratio), respectively. That is, the adjacent distance between the data Bi and the data Ai + 1 (i = 20 to 23) decreases by 1k (= 5k-4k) when i increases by 1 (indicated by bold characters in FIG. 10).

  On the other hand, as for the counter value K, “4” (corresponding to the frequency of data B) is first added, and if the counter value is “5” (corresponding to the frequency of data A) or more, “5” (Corresponding to the frequency of data A) is subtracted. That is, the counter value K decreases by “1” (= 5-4) (indicated by bold characters in FIG. 10). That is, the ratio of the adjacent distance between the data Bi and the data Ai + 1 (i = 20 to 23) can be obtained based on the counter value K. In this case, x3 = 5k-4k = k, x4 = 3k.

  Therefore, the output control unit 62 can linearly complement the output data based on the counter value K, and simply thins out 395 data from 48000 data per second to 47605 data per second. Compared to the case of sampling, discontinuity occurring before and after the thinned data can be eliminated.

(Second modification)
In the sampling unit 6 in the second embodiment, 395 data are simply thinned out from 48000 data per second at approximately equal intervals, and sampling is performed to 47605 data per second. Discontinuities occur before and after the data.

  Therefore, the sampling unit 6 oversamples data input at a frequency of 48.000 KHz, for example, at a frequency 50 times, and samples the data to data of a frequency of 47.605 KHz.

  Specifically, the counter circuit 61 adds the counter value K by “47605/50” (corresponding to 1/50 of the frequency of the writing unit 2) at each time t0, t1,. Each time interval between times t0, t1,... Is a time corresponding to 48.000 × 50 KHz (corresponding to 50 times the frequency of the transmitter). That is, the timing of the input data is time t0, t50, t100,.

  When the counter value K exceeds “48000” (corresponding to the frequency of the data input to the sampling unit 6), the output control unit 62 outputs an accumulated value to be described later to the writing unit 2. 48000 "is subtracted. When the counter value K is “48000” or more, the output control unit 62 does not output data and keeps the counter value K as it is.

  Next, the operation of the output control unit 62 will be described. If the difference between two adjacent sample points of the input data is Δ, the output control unit 62 accumulates a value obtained by multiplying Δ by 1/50 every time t0, t1,. When the counter value K is “48000” or more, the cumulative value is output to the writing unit 2.

  Specifically, FIG. 11 shows a part of the input data and output data of the sampling unit 6. As shown by a thick line in FIG. 11, for example, when the data A28 is input to the output control unit 62 at time t1400, the output control unit 62 sets the difference Δ (= A28−A27) between the data A27 and A28 to 50 minutes. Is multiplied by 1, and thereafter, Δ / 50 is accumulated every time t1400, t1401, t1402,. In FIG. 11, the cumulative value is indicated by a one-dot chain line. The cumulative value indicated by the alternate long and short dash line is drawn so as to be proportional to the time. However, as shown in the enlarged view, in actuality, every time tj (j = 0, 1, 2,...) Since / 50 is accumulated, it is not a straight line but a step shape.

  Then, every time t1400, t1401,..., The counter circuit 61 adds “47605/50” to the counter value K, and when the counter value K becomes “48000” or more at time t1411, the output control unit 62 at time t1411. Is output to the writing unit 2. Then, “48000” is subtracted from the counter value K, and “47605/50” is added again every time t1412, t1413,.

  When the data A29 is input to the output control unit 62 at time t1450, the output control unit 62 calculates a value obtained by multiplying the difference Δ (= A29−A28) between the data A28 and A29 by 1/50. Then, Δ / 50 is added to the accumulated value, and thereafter Δ / 50 is accumulated every t1451, t1452,. When the counter value K becomes “48000” or more at time t1462, the output control unit 62 outputs the cumulative value to the writing unit 2 at time t1462.

  As described above, the output control unit 62 can correct output data by oversampling, and simply thins out 395 data from 48000 data per second and samples it to 47605 data per second. Compared to the case, discontinuities occurring before and after the thinned data can be eliminated.

  In any of steps S6, S8, S12, and S15 of FIG. 2, when the frequency of the writing unit 2 is changed, a value obtained by multiplying the value corresponding to the changed frequency by 1/50 is the counter value K. Can be added to. For example, when the frequency of the writing unit 2 is set to the maximum value (47.609 KHz), “47609/50” may be added to the counter value K every time t0, t1,. Similarly, when the frequency of the writing unit 2 is set to the minimum value (47.000 KHz), “47000/50” may be added to the counter value K at each time t0, t1,.

  In addition, a value to be added to the counter value K (for example, “47000/50”, “47605/50”, “47609/50”) is recorded in the register 51 in advance, so that the sampling unit 6 includes a division circuit. Since it becomes unnecessary, the circuit scale can be reduced and the processing load in the sampling unit 6 can be reduced.

  Note that, compared with the first modification, the output data is calculated only by addition, so that the processing load for calculating the output data is low and the circuit scale is small. On the other hand, in the first modification, the output data is calculated by linearly complementing the input data, so that the accuracy of the output data is higher than that in the second modification.

  In the present invention, the buffer flow control device is described as being provided in the transmitter. However, the present invention is not limited to this, and the buffer flow control device may be provided in the receiver. In that case, the data transmitted from the transmitter at, for example, 48.000 KHz is sampled by the sampling unit 6 at, for example, a frequency of 47.605 KHz, the writing unit 2 writes the data to the buffer memory 1, and the reading unit 3 is the clock of the receiver Data is read from the buffer memory 1 at a frequency of 47.605 kHz based on the above. When the reading unit 3 reads data from the buffer memory 1 and the amount of data written by the writing unit 2 to the buffer memory 1 is not within a predetermined range, the frequency of the writing unit 2 (the sampling frequency of the sampling unit 6). ) Should be changed. Moreover, you may provide in the relay machine which connects a transmitter and a receiver.

It is a schematic diagram of the system which consists of a transmitter provided with the buffer flow control apparatus which concerns on 1st Embodiment, and a receiver. It is a flowchart which shows operation | movement of the buffer flow control apparatus which concerns on 1st Embodiment. It is a flowchart which shows operation | movement of a receiver. It is a figure which shows transition of the address value which the writing part wrote last. It is a figure which shows transition of the address value which the writing part wrote last. It is a figure which shows transition of the address value which the writing part wrote last. It is a schematic diagram of the system which consists of a transmitter provided with the buffer flow control apparatus which concerns on 2nd Embodiment, and a receiver. It is a figure which shows transition of the counter value K. It is a figure which shows the outline | summary of a straight line complement. It is a figure which shows the outline | summary of a straight line complement. It is a figure which shows the outline | summary of oversampling.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Buffer memory 2 Writing part 3 Reading part 5 Control part 51 Register 6 Sampling part 61 Counter circuit 62 Output control part

Claims (5)

Buffer memory,
A writing unit for writing data to the buffer memory at a first frequency;
A reading unit for reading data from the buffer memory;
As the set value of the first frequency, at least three set values of a first value, a second value larger than the first value, and a third value smaller than the first value are recorded in advance. Register
When the data amount of the buffer memory exceeds a predetermined upper limit value, the first frequency is changed to the third value, and when the data amount of the buffer memory falls below a predetermined lower limit value, the first frequency is changed. And a control unit that changes the frequency to the second value,
When the first frequency is the third value, the control unit updates the first value to a lower value than before and records the first value in the register, and the first frequency is the second value. When it is a value, the control unit updates the first value to a higher value than before and records it in the register. A sampling unit that samples data input at a second frequency into data of the first frequency and outputs the sampled data to the writing unit;
The sampling unit
A value corresponding to the first frequency is added to the counter value, and if the counter value is equal to or greater than a value corresponding to the second frequency, a value corresponding to the second frequency is subtracted from the counter value. A counter section;
An output control unit that outputs the input data to the writing unit when the counter value after the addition and before the subtraction is greater than or equal to a value corresponding to the second frequency. The buffer flow control device described. A sampling unit that samples data input at a second frequency into data of the first frequency and outputs the sampled data to the writing unit;
The sampling unit
A value corresponding to the first frequency is added to the counter value, and if the counter value is equal to or greater than a value corresponding to the second frequency, a value corresponding to the second frequency is subtracted from the counter value. A counter section;
An output control unit that complements the input data and outputs the complemented data when the counter value after the addition and before the subtraction is equal to or greater than a value corresponding to the second frequency. Item 4. The buffer flow control device according to Item 1.   The buffer flow control device according to claim 3, wherein the complementing is linear complementation for the data input at the second frequency based on the counter value. The counter unit adds a value obtained by dividing a value corresponding to the first frequency by a desired numerical value to the counter value,
The buffer flow control device according to claim 3, wherein the complementing is to accumulate a value obtained by dividing a difference value between two adjacent values of the data input at the second frequency by the numerical value.

Images