JP4721529B2 - Driving method of solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a method for driving a solid-state imaging device.To the lawIn particular, the present invention relates to a driving technique for realizing an electronic shutter function of a solid-state imaging device.
[0002]
[Prior art]
  The electronic shutter function of the solid-state image pickup device is to adjust the charge accumulation time of the image pickup unit by driving and to electronically control the exposure time instead of the physical iris (iris) function. Specifically, the electronic shutter function is realized by discharging (resetting) signal charges accumulated in each pixel at a predetermined timing different from pixel signal readout.
[0003]
  One conventional solid-state imaging device is disclosed in JP-A-11-220663. This is because an imaging unit in which a plurality of pixels are arranged in a two-dimensional matrix and a plurality of registers each including a register provided for each row of the imaging unit are connected in series. A shift register that sequentially transmits each clock, and a selection circuit having the same number as the number of rows provided for each row of the imaging unit, and the pixels of the row selected according to the output of the register that constitutes the shift register. On the other hand, the solid-state imaging device includes a drive unit that executes a read operation or a reset operation.
[0004]
[Problems to be solved by the invention]
  However, in the conventional solid-state imaging device, since the clock of the selection circuit is output every horizontal scanning period, there is a problem that the accumulation time of the electronic shutter can be controlled only every horizontal scanning period.
[0005]
  For example, in the case of NTSC of a television system, one horizontal scanning period is approximately 1 / 16th of a second. In the electronic aperture function, which is the main application of the electronic shutter, control with a sense of incongruity can be performed if the control is performed in increments of about 1/50 of the accumulation time. When the accumulation time of 1 / 100th of a second or less is controlled, every 16,000th of a second is about 1 / 20th of a second, and the control range becomes large. In addition, the maximum speed of the high-speed electronic shutter is the maximum of 16,000th of a second.
[0006]
  The above problem can be solved by making the drive unit control configuration of the row selection and column selection shift registers the same, but the column selection shift register often operates at a high speed of 10 MHz or more and the design margin is small. Further, there is a problem that the circuit scale becomes large and the input pulse control of both the row / column selection shift registers becomes complicated.
[0007]
  An object of the present invention is to realize fine charge accumulation time control of one horizontal scanning period or less in the electronic shutter mode.
[0008]
[Means for Solving the Problems]
  In view of the above-described problems, the present invention provides a method for driving a solid-state imaging device, wherein a fine charge accumulation time control of one horizontal scanning period or less is performed by applying a reset signal a plurality of times within one horizontal scanning period including the video period. Therefore, it is possible to realize an ultra-high-speed electronic shutter such as 1 / 100,000 second.
[0009]
  Specifically,Claim1The solution provided by the invention is that an imaging unit in which a plurality of pixels are arranged in a two-dimensional matrix and a plurality of registers each including a register provided for each row or each column of the imaging unit are connected in series. And a shift register that sequentially transmits the supplied driving signal for each clock, and the number of selection circuits provided for each row or each column of the imaging unit. And a driving unit that executes a read operation or a reset operation on the pixels of the row or column selected according to the output of the register that constitutes the signal, and outputs a signal for each pixel according to the clock of the shift register of the column In the solid-state imaging device driving method, the reset operation is performed a plurality of times while the clock of the shift register of the row is supplied for one clock period. That.
[0010]
  Claims above1According to the invention, by applying the reset signal a plurality of times within one horizontal scanning period, the charge accumulation time control within one horizontal scanning period is realized, and an ultra-high speed electronic shutter such as 1 / 100,000 second is realized. be able to. However, if the counter in the solid-state imaging device is counted during the video period and a reset signal is output multiple times, fixed pattern noise may occur due to countdown noise or pulse logic changes, which may adversely affect the video. .Therefore, the signal processing circuit corrects the output for each pixel so as to remove noise in accordance with the timing information of the multiple reset operation.
[0011]
  Claims2The solution provided by the invention is that an imaging unit in which a plurality of pixels are arranged in a two-dimensional matrix and a plurality of registers each including a register provided for each row or each column of the imaging unit are connected in series. And a shift register that sequentially transmits the supplied driving signal for each clock, and the number of selection circuits provided for each row or each column of the imaging unit. And a driving unit that executes a read operation or a reset operation on the pixels of the row or column selected according to the output of the register that constitutes the signal, and outputs a signal for each pixel according to the clock of the shift register of the column In the driving method of the solid-state imaging device, the drive signal supplied to the shift register of the row is supplied while the clock of the shift register of the row is supplied for one clock period. In which it was decided to perform the operations of multiple reset accordance management change position.In addition, the output of each pixel is corrected by the signal processing circuit so as to remove noise according to the timing information of the multiple reset operation.For this reason, the reset pulse train can be generated by using a conventionally used driving signal, and the above-described problems can be solved without increasing the number of signal lines.
[0012]
  Claim3In the invention of the above,2In the solid-state imaging device driving method according to the invention, a logic change position of a driving signal supplied to the shift register of the row is detected using a Gray code counter, and the output of the Gray code counter is used to detect the logic change position. It was decided to execute the reset operation multiple times. Generation of noise can be suppressed by employing a Gray code counter with a uniform number of clock changes.
[0013]
  Claims4The solution provided by the invention is that an imaging unit in which a plurality of pixels are arranged in a two-dimensional matrix and a plurality of registers each including a register provided for each row or each column of the imaging unit are connected in series. And a shift register that sequentially transmits the supplied driving signal for each clock, and the number of selection circuits provided for each row or each column of the imaging unit. And a driving unit that executes a read operation or a reset operation on the pixels of the row or column selected according to the output of the register that constitutes the signal, and outputs a signal for each pixel according to the clock of the shift register of the column Input from the outside of the solid-state imaging deviceFor charge accumulation time controlAccording to the serial data, the reset operation is executed a plurality of times while the clock of the shift register in the row is supplied for one clock period.Moreover, the serial data is input from the outside of the solid-state imaging device while the signal of the imaging unit is not output.For this reason, although the number of signal lines increases, the above-described problems can be solved while preventing noise generation during the generation of the reset pulse train.
[0014]
  Claim5In the invention of the above,4In the solid-state imaging device driving method according to the invention, the reset operation is executed a plurality of times in accordance with a comparison result between the serial data input from the outside of the solid-state imaging device and the output of the Gray code counter.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0016]
  FIG. 1 is a block diagram showing a schematic configuration of a solid-state imaging device according to an embodiment of the present invention. In FIG. 1, 10 is an image pickup unit in which a plurality of pixels 1 are arranged in a two-dimensional matrix (arranged in 3 rows and 3 columns in FIG. 1), and 11 is a plurality (5 in FIG. 1) of registers (R) 11a to 11e. Are connected in series, and a row selection shift register as a shift register for sequentially transmitting the driving signal SD supplied from the control unit 31, 12 is a selection circuit 12a to 12 provided for each row of the imaging unit 10, respectively. This is a selected row driving unit as a driving unit configured to perform a reading operation or a resetting operation on the pixels 1 in the row selected according to the output of the row selection shift register 11.
[0017]
  Reference numeral 21 denotes a column selection shift register for column selection in the image pickup unit 10, and 22 is provided between the image pickup unit 10 and the column selection shift register 21, and the potential based on the signal charge accumulated in the selected pixel 1 is set to the pixel. It is a selected column driver that reads out as a signal. Since the column selection shift register 21 and the selection column driving unit 22 have the same configuration as the conventional one and do not greatly affect the configuration of the present invention, detailed description thereof is omitted in this embodiment.
[0018]
  In the row selection shift register 11, the second to fourth stage registers 11 b, 11 c, and 11 d correspond to the respective rows of the imaging unit 10. In each of the selection circuits 12a, 12b, and 12c, the driving signal SD is output from one of the registers 11a to 11e included in the shift register 11 to the pixel 1 in the corresponding row. Then, in the shift register 11, either the reading or reset operation is selectively executed according to the output of the register located in the preceding stage and the succeeding stage of one of the registers 11a to 11e. For example, the selection circuit 12a provided for the first row of the imaging unit 10 receives the first stage and the first stage when the driving signal SD is output from the second stage register 11b provided for the first row. According to the outputs of the three-stage registers 11a and 11c, either the readout or reset operation is selectively executed for the pixels 1 in the first row.
[0019]
  FIG. 2 is a diagram illustrating an example of a circuit configuration of the pixel 1, and is a diagram illustrating a circuit configuration of a MOS-type active pixel in which a photoelectric element and a detection unit are separately provided. As shown in FIG. 2, the photoelectric element 3 is connected to the detection unit 5 via the transfer gate 4, and the detection unit 5 is connected to the signal output line 8 via the selection unit 6 including two transistors 6a and 6b. It is connected. The detection unit 5 is connected to the power supply VDD via the reset gate 7.
[0020]
  FIG. 3 is a circuit diagram showing an example of a specific configuration of the shift register 11 and the selected row driving unit 12. As shown in FIG. 3, each selection circuit 12a, 12b, 12c includes one 3-input NOR gate 13, three 2-input NAND gates 14a, 14b, 14c, and four inverters 15a, 15b, 15c, 15d. Note that SIN is a start pulse signal and CLK is a clock, both of which are supplied from the control unit 31. The control unit 31 sets the start pulse signal SIN to “H” at the rising edge of the clock CLK, thereby supplying the logic level “H” to the shift register 11 as the drive signal SD.
[0021]
  Each of the selection circuits 12a, 12b, and 12c outputs a selection signal SLi, a transfer signal TRi, and a reset signal RSi (i represents a row number, i = 1 to 3 in this embodiment) to the pixels 1 of the corresponding row. Then, a read operation and a reset operation are executed. During the read operation, each of the selection circuits 12a to 12c sets the selection signal SLi and the transfer signal TRi to “H”. When the transfer signal TRi becomes “H”, the signal charge accumulated in the photoelectric element 3 in the pixel 1 moves to the detection unit 5 through the transfer gate 4, and the selection signal SLi is “H”, so the potential of the detection unit 5 is selected. The signal is output to the signal output line 8 via the unit 6. Thereafter, the reset signal RSi is set to “H” to remove the signal charges accumulated in the detection unit 5. On the other hand, during the reset operation, the reset signal RSi is set to “H” while the selection signal SLi is set to “L”, and the signal charges accumulated in the detection unit 5 are removed.
[0022]
  The circuit configuration and operation of each of the selection circuits 12a, 12b, and 12c illustrated in FIG. 3 will be described using the selection circuit 12b provided for the second row of the imaging unit 10 as an example.
[0023]
  In the selection circuit 12b, the three-input NOR gate 13 receives the output SG2 of the third stage register 11c inverted by the inverter 15d and the outputs SG1 and SG3 of the second and fourth stage registers 11b and 11d. That is, as for the output of the 3-input NOR gate 13, the output SG2 of the third stage register 11c provided for the second row of the imaging unit 10 is “H” (that is, the driving signal SD from the third stage register 11c). And the outputs SG1 and SG3 of the second and fourth stage registers 11b and 11d located in the preceding stage and the subsequent stage of the third stage register 11c in the shift register 11 are both "L" (that is, the second stage). When the driving signal SD is not output from the stage and fourth stage registers 11b and 11d), it becomes “H”, otherwise it becomes “L”.
[0024]
  The 2-input NAND gate 14a receives the output of the 3-input NOR gate 13 and the selection synchronization signal CSL, and the output is output as the selection signal SL2 via the inverter 15a. Therefore, when the output of the 3-input NOR gate 13 is “H”, that is, the output SG2 of the third stage register 11c is “H”, and the outputs SG1 of the second and fourth stage registers 11b and 11d and When both SG3 are “L”, the selection signal SL2 becomes “H” in synchronization with the selection synchronization signal CSL.
[0025]
  On the other hand, the 2-input NAND gate 14b receives the output SG2 of the third-stage register 11c and the transfer synchronization signal CTR, and the output is output as the transfer signal TR2 via the inverter 15b. The 2-input NAND gate 14c receives the output SG2 of the third-stage register 11c and the reset synchronization signal CRS, and the output is output as the reset signal RS2 through the inverter 15c. Therefore, the transfer signal TR2 becomes “H” in synchronization with the transfer synchronization signal CTR when the output SG2 of the third stage register 11c is “H”, and the reset signal RS2 is also output SG2 of the third stage register 11c. Is “H” in synchronization with the reset synchronization signal CRS.
[0026]
  The selection circuits 12a and 12c operate in the same manner as the selection circuit 12b. That is, in the selection circuit 12a corresponding to the first row, the output SG1 of the second stage register 11b provided for the first row is “H”, and the shift register 11 has a stage before the second stage register 11b. When the outputs SGS and SG2 of the first and third stage registers 11a and 11c located at the subsequent stage are both “L”, the selection signal SL1 is set to “H” in synchronization with the selection synchronization signal CSL, and the second When the output SG1 of the stage register 11b is “H”, the transfer signal TR1 is set to “H” in synchronization with the transfer synchronization signal CTR, and the reset signal RS1 is set to “H” in synchronization with the reset synchronization signal CRS.
[0027]
  Similarly, in the selection circuit 12c corresponding to the third row, the output SG3 of the fourth stage register 11d provided for the third row is “H” and the shift register 11 includes the output of the fourth stage register 11d. When the outputs SG2 and SGE of the third and fifth stage registers 11c and 11e located at the previous stage and the subsequent stage are both "L", the selection signal SL3 is set to "H" in synchronization with the selection synchronization signal CSL. When the output SG3 of the fourth stage register 11d is “H”, the transfer signal TR3 is set to “H” in synchronization with the transfer synchronization signal CTR, and the reset signal RS3 is set to “H” in synchronization with the reset synchronization signal CRS. To do.
[0028]
  FIG. 4 is a timing chart showing the operation of the shift register 11 and the selected row driving unit 12 shown in FIG.
[0029]
  In the normal mode shown in FIG. 4, the control unit 31 sets the start pulse signal SIN so that the drive signal SD, that is, the signal “H” is input to the shift register 11 only for one clock period. The shift register 11 sequentially transmits a signal “H” in synchronization with the clock CLK, whereby the outputs SGS, SG1, SG2, SG3, SGE of the respective registers 11a to 11e rise in order, and each of them outputs “H” for one clock period. "become.
[0030]
  In this case, as shown in (a1), when the output SG1 of the second stage register 11b is “H”, the outputs SGS and SG2 of the first and third stage registers 11a and 11b are “L”. Therefore, the selection signal SL1 becomes “H” at the timing of the selection synchronization signal CSL. At the same time, the transfer signal TR1 also becomes “H” at the timing of the transfer synchronization signal CTR. When the selection signal SL1 and the transfer signal TR1 are both “H”, the reading operation is performed on the pixels 1 in the first row. Thereafter, the reset signal RS1 becomes “H” at the timing of the reset synchronization signal CRS, and the signal charge is removed from the pixels 1 in the first row.
[0031]
  Similarly, as shown in (a2), when the output SG2 of the third stage register 11c is “H”, the outputs SG1 and SG3 of the second and fourth stage registers 11b and 11d in the preceding stage and the subsequent stage are both “L”. Therefore, the selection signal SL2 becomes “H” at the timing of the selection synchronization signal CSL, and the transfer signal TR2 also becomes “H” at the timing of the transfer synchronization signal CTR. Further, as shown in (a3), when the output SG3 of the fourth stage register 11d is “H”, the outputs SG2 and SG4 of the third stage and the fifth stage registers 11c and 11e in the preceding stage and the subsequent stage are both “L”. Therefore, the selection signal SL3 becomes “H” at the timing of the selection synchronization signal CSL, and the transfer signal TR3 also becomes “H” at the timing of the transfer synchronization signal CTR. With such an operation, a reading operation is performed on the imaging unit 10 for each row.
[0032]
  FIG. 5 is a timing chart showing operations in the electronic shutter mode of the shift register 11 and the selected row driving unit 12 shown in FIG. FIG. 6 is an enlarged view of a portion to which an electronic shutter reset pulse (reset synchronization signal) CRS is applied.
[0033]
  In the electronic shutter mode shown in FIGS. 5 and 6, the control unit 31 sets the start pulse signal SIN so that the driving signal SD, that is, the signal “H” is continuously input to the shift register 11 for two clock periods. . As a result, the outputs SGS, SG1, SG2, SG3, SGE of the respective registers 11a to 11e sequentially rise and become “H” for two clock periods. That is, when the output of one of the registers 11a to 11e is "H", the output of either the preceding stage or the subsequent stage is "H".
[0034]
  In this case, as shown in (b1), when the output SG1 of the second stage register 11b is “H”, the output SGS of the first stage register 11a of the preceding stage is “H” in the first half, and the latter stage is the latter stage. Since the output SG2 of the third stage register 11c is “H”, the selection signal SL1 does not become “H” but remains “L”. On the other hand, both the transfer signal TR1 and the reset signal RS1 become “H”. At this time, since a plurality of pulses are applied to the reset synchronization signal CRS in one horizontal scanning period, the reset signal RS1 becomes “H” four times in total. When the transfer signal TR1 and the reset signal RS1 become “H” while the selection signal SL1 does not become “H” but remains “L”, the reset operation is performed four times for the pixels 1 in the first row.
[0035]
  Similarly, as shown in (b2), when the output SG2 of the third stage register 11c is “H”, any one of the outputs SG1 and SG3 of the second stage and the fourth stage registers 11b and 11d in the preceding stage and the subsequent stage is selected. Since it is “H”, the selection signal SL2 does not become “H” but remains “L”, the transfer signal TR2 becomes “H” twice, and the reset signal RS2 becomes “H” four times. As shown in (b3), when the output SG3 of the fourth stage register 11d is “H”, any of the outputs SG2 and SG4 of the third stage and the fifth stage registers 11c and 11e in the preceding stage and the subsequent stage is “ Since it is H, the selection signal SL3 remains “L” instead of “H”, the transfer signal TR3 becomes “H” twice, and the reset signal RS2 becomes “H” four times. With such an operation, the imaging unit 10 is reset four times for each row, and the accumulation time starts from the time when the row was reset last. Therefore, it is possible to control the storage time shorter than one horizontal scanning period, and to realize a high-speed electronic shutter function.
[0036]
  Note that the configuration in which signal reading and resetting are performed using the same shift register has been described, but reading and resetting (electronic shutter) may be different from each other.
[0037]
  Here, a method of generating the electronic shutter reset pulse (reset synchronization signal) CRS in FIGS. 5 and 6 will be described.
[0038]
  FIG. 7 shows an example in which the falling edge of the start pulse signal SIN is used to generate the second CRS pulse during one horizontal scanning period. According to FIG. 7, the falling position of the start pulse signal SIN is detected by the counter with an accuracy of 1/16 horizontal scanning period. Timing data representing the detected falling position is held, and this data is used for each cycle of the clock CLK to generate a second CRS pulse. The first CRS pulse uses the reset synchronization signal CRS in the normal mode.
[0039]
  FIG. 8 shows a configuration example of the control unit 31 for realizing the CRS pulse train generation method of FIG. In FIG. 8, 41 is a falling edge detector, 42 is a counter, 43 is a data holding circuit, and 44 is an OR circuit. According to FIG. 8, the falling position of the start pulse signal SIN is detected by the detector 41 and the counter 42, the timing data in one horizontal scanning period is held in the data holding circuit 43, and is output in every horizontal scanning period. . Then, the OR circuit 44 calculates the logical sum of the held data and the normal CRS pulse, and applies a CRS pulse train representing the result to the selection circuit 12.
[0040]
  FIG. 9 shows another configuration example of the control unit 31 for realizing the CRS pulse train generation method of FIG. In the example of FIG. 9, one horizontal scanning period is equally divided in advance using the Gray code counter 45 in which the countdown noise becomes uniform, the falling position of the start pulse signal SIN is detected, and the CRS pulse train is output. It is like that. When the control unit 31 is configured on the same substrate as the imaging unit 10, in the configuration of FIG. 8, there is a possibility that the video signal is affected by vertical stripes due to the countdown noise of the counter 42. However, in the configuration of FIG. 9, the counter is operated for one horizontal scanning period using a counter with uniform countdown noise (a ring counter or the like may be used instead of the Gray code counter 45), and 1 / 16th as shown in FIG. This problem can be avoided by detecting the falling edge of the start pulse signal SIN every horizontal scanning period.
[0041]
  FIG. 10 does not control the accumulation time of one horizontal scanning period or less by the start pulse signal SIN, but matches the serial data input from the outside of the solid-state imaging device and the counter output that equally divides one horizontal scanning period. Accordingly, an example in which the second CRS pulse in one horizontal scanning period is generated is shown.
[0042]
  FIG. 11 shows a configuration example of the control unit 31 for realizing the CRS pulse train generation method of FIG. In FIG. 11, 51 is a serial data decoder, 52 is a Gray code counter, 53 is a data holding circuit, and 54 is an OR circuit. Serial data DATA synchronized with the data clock DCLK is supplied to the serial data decoder 51. According to FIG. 11, the control unit 31 is provided with a serial communication function, and for the accumulation time control of one horizontal scanning period or less, the output value of the gray code counter 52 that counts the decode value of the serial data DATA and one horizontal scanning period. And, if they match, the CRS pulse is output during the horizontal scanning period. Thereby, even when the imaging unit 10 and the control unit 31 are configured on the same substrate, the image is not affected. Further, by performing serial communication within the vertical or horizontal blanking interval, adverse effects on the video can be avoided.
[0043]
  FIG. 12 is a block diagram of a camera using the solid-state imaging device of the present invention. In FIG. 12, 61 is a CMOS sensor, 62 is a preprocessing IC, and 63 is a signal processing IC. In this camera, the position in the video where the vertical streak may be generated is specified according to the timing information of the CRS pulse train, and the output of the CMOS sensor 61 is corrected in the signal processing IC 63. As a correction method, dark data is temporarily stored in a memory or the like as scratch data, and the scratch data is subtracted from the video signal. For example, in the configurations of FIGS. 7 to 9, the falling position information of the start pulse signal SIN can be used as timing information of the CRS pulse train.
[0044]
  Although the present embodiment has been described on the assumption that the MOS type active pixel as shown in FIG. 2 is used, the present invention can be easily applied to other types of pixels.
[0045]
  In the present embodiment, the electronic shutter method in which the reset pulse is applied twice in one horizontal scanning period and four times in a total of two horizontal scanning periods has been described. However, the reset pulse applied in one horizontal scanning period is: It does not matter even if it is 3 times or more. Further, the applied period may be three horizontal scanning periods or more.
[0046]
  In the present embodiment, the imaging unit 10 is configured such that the pixels 1 are arranged in 3 rows and 3 columns, but the present invention can be easily applied to an imaging unit having any number of rows and columns. Is possible. For example, for an imaging unit of n rows (n is a positive integer), a row selection shift register including (n + 2) registers including n registers corresponding to each row and n pieces corresponding to each row The selection circuit may be provided with the output of the register corresponding to the row and the output of the register located in the preceding and succeeding stages as inputs.
[0047]
  In addition, although logical operations (logical sums) described in the positive logic appear in the description, any logic circuit that realizes an equivalent function such as controlling with negative logic may be used.
[0048]
  Furthermore, in the solid-state imaging device according to the present embodiment, the rows and columns of the imaging unit 10 may be interchanged.
[0049]
  In the present embodiment, the selection circuit selects the output of the registers located in the preceding stage and the succeeding stage of one register among the registers 11a to 11e corresponding to the row in order to select the operation of reading or resetting. Although the present invention is used, the present invention is not limited to this, and either read or reset operation may be selected in accordance with the output of the register that is a predetermined number of stages away from the one register.
[0050]
  The normal mode and the electronic shutter mode are switched, and in the normal mode, the driving signal is continuously supplied to the shift register for two clock periods, and in the electronic shutter mode, the driving signal is supplied to the shift register for only one clock period. As you can see, you can control it. In this case, the configuration of each selection circuit needs to be changed. For example, the output of the NOR gate 13 may be inverted.
[0051]
【The invention's effect】
  As described above, according to the present invention, it is possible to control the accumulation time in one horizontal scanning period or less in the electronic shutter mode. Therefore, in the solid-state imaging device, a fine accumulation time control of one horizontal scanning period or less can be performed with the electronic aperture function, and a high-speed electronic shutter such as 1 / 100,000 second can be realized in the electronic shutter mode.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a schematic configuration of a solid-state imaging apparatus according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating an example of a specific configuration of a pixel in FIG.
FIG. 3 is a circuit diagram showing an example of a specific configuration of a row selection shift register and a selected row driver in FIG. 1;
4 is a timing chart showing the operation of the circuit of FIG. 3 in the normal mode.
5 is a timing chart showing the operation of the circuit of FIG. 3 in the electronic shutter mode.
6 is a partially enlarged view of FIG. 5;
7 is a diagram illustrating an example of a method for generating a CRS pulse train in FIGS. 5 and 6. FIG.
8 is a block diagram illustrating a configuration example of a control unit for realizing the CRS pulse train generation method of FIG.
9 is a block diagram showing another configuration example of a control unit for realizing the CRS pulse train generation method of FIG. 7. FIG.
FIG. 10 is a diagram illustrating another example of a method for generating a CRS pulse train in FIGS. 5 and 6;
11 is a block diagram illustrating a configuration example of a control unit for realizing the CRS pulse train generation method of FIG.
FIG. 12 is a configuration diagram of a camera using the solid-state image sensor driving method of the present invention.
[Explanation of symbols]
  1 pixel
  10 Imaging unit
  11 Shift register for row selection
  11a to 11e registers
  12 Selected row drive unit
  12a to 12c selection circuit
  13 3-input NOR gate
  31 Control unit
  41 Falling edge detector
  42 counter
  43, 53 Data holding circuit
  44, 54 OR circuit
  45,52 Gray code counter
  51 Serial data decoder
  61 Solid-state imaging device (CMOS sensor)
  62 Pretreatment IC
  63 Signal processing IC

Claims (5)

An imaging unit in which a plurality of pixels are arranged in a two-dimensional matrix;
A plurality of registers each including a register provided for each row or each column of the imaging unit are connected in series, and a shift register that sequentially transmits the supplied driving signal for each clock;
Each of the imaging units is composed of the same number of selection circuits as the number of rows or columns provided for each row or each column of the imaging unit, and the pixels of the row or column selected according to the output of the register constituting the shift register, A drive unit that performs a read operation or a reset operation, and
A driving method of a solid-state imaging device in which a signal for each pixel is output according to a clock of a shift register of the column,
While the clock of the shift register of the row is supplied for one clock period, a reset operation is performed a plurality of times ,
A driving method of a solid-state imaging device , wherein the output of each pixel is corrected by a signal processing circuit so as to remove noise in accordance with timing information of the multiple reset operation . An imaging unit in which a plurality of pixels are arranged in a two-dimensional matrix;
A plurality of registers each including a register provided for each row or each column of the imaging unit are connected in series, and a shift register that sequentially transmits the supplied driving signal for each clock;
Each of the imaging units is composed of the same number of selection circuits as the number of rows or columns provided for each row or each column of the imaging unit, and the pixels of the row or column selected according to the output of the register constituting the shift register, A drive unit that performs a read operation or a reset operation, and
A driving method of a solid-state imaging device in which a signal for each pixel is output according to a clock of a shift register of the column,
While the clock of the shift register of the row is supplied for one clock period, the reset operation is executed a plurality of times according to the logic change position of the driving signal supplied to the shift register of the row ,
A driving method of a solid-state imaging device , wherein the output of each pixel is corrected by a signal processing circuit so as to remove noise in accordance with timing information of the multiple reset operation . The driving method of the solid-state imaging device according to claim 2 ,
A logic change position of a driving signal supplied to the shift register of the row is detected using a Gray code counter, and the reset operation is executed a plurality of times using an output of the Gray code counter. For driving a solid-state imaging device. An imaging unit in which a plurality of pixels are arranged in a two-dimensional matrix;
A plurality of registers each including a register provided for each row or each column of the imaging unit are connected in series, and a shift register that sequentially transmits the supplied driving signal for each clock;
Each of the imaging units is composed of the same number of selection circuits as the number of rows or columns provided for each row or each column of the imaging unit, and the pixels of the row or column selected according to the output of the register constituting the shift register, A drive unit that performs a read operation or a reset operation, and
A driving method of a solid-state imaging device in which a signal for each pixel is output according to a clock of a shift register of the column,
While the signal of the imaging unit is not output, serial data for charge accumulation time control is input from the outside of the solid-state imaging device,
In accordance with the foregoing solid-state imaging device serial data input from the outside, while the clock of the shift register of the row is one clock period supply, the driving method of the solid-state imaging apparatus characterized by performing the operations of multiple reset. The solid-state imaging device driving method according to claim 4 ,
A driving method of a solid-state imaging device, wherein the reset operation is executed a plurality of times according to a comparison result between the serial data input from outside the solid-state imaging device and an output of a Gray code counter.

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