JP4712668B2 - Display driving integrated circuit and wiring arrangement determining method for display driving integrated circuit - Google Patents

Description

  The present invention provides a gradation display reference voltage generation circuit that generates a gradation display reference voltage of a gray scale level (hereinafter referred to as gradation level), and a DA that converts analog display data based on the gradation display reference voltage. The present invention relates to a display driving integrated circuit including a conversion circuit and a reference voltage wiring for supplying the gradation display reference voltage to the DA conversion circuit, and a wiring arrangement determining method for the display driving integrated circuit.

  Conventionally, in an active matrix type liquid crystal display device, a gradation display reference voltage generation circuit for driving a liquid crystal element with an intermediate voltage obtained by resistance division is known (see, for example, Patent Document 1).

  In the gradation display reference voltage generation circuit, the resistance dividing resistor has a resistance ratio called γ correction, and the optical characteristics of the liquid crystal element are corrected in accordance with the ratio of the resistance ratio, thereby providing a more natural gradation. Display is realized.

  The following is a configuration of a liquid crystal display device including the gradation display reference voltage generation circuit, a configuration of a TFT (thin film transistor) type liquid crystal panel in the liquid crystal display device, a liquid crystal driving waveform, and a configuration of a source driver thereof. Will be explained.

  FIG. 13 is a block diagram illustrating a conventional technique and illustrating a configuration of a main part of a liquid crystal display device 901. FIG. 14 is a circuit diagram showing a main configuration of a liquid crystal panel 902 provided in the liquid crystal display device 901. The liquid crystal display device 901 is a TFT (thin film transistor) type liquid crystal display device which is a typical example of a conventional active matrix type. The liquid crystal display device 901 includes a liquid crystal display unit 934 and a liquid crystal driving circuit (liquid crystal driving unit) 935 that drives the liquid crystal display unit 934. The liquid crystal display unit 934 includes a TFT liquid crystal panel 902. In the liquid crystal panel 902, a liquid crystal display element 912 (FIG. 14) and a counter electrode (common electrode) 903 described in detail later are provided.

  On the other hand, a source driver unit 904 and a gate driver unit 906 made of an IC (integrated circuit), a controller 908, and a liquid crystal driving power source 909 are mounted on the liquid crystal driving circuit 935. The controller 908 supplies the display data D and the control signal S1 to the source driver unit 904, and supplies the control signal S2 to the gate driver unit 906.

  The liquid crystal panel 902 includes a plurality of gate signal lines 910 provided in parallel to each other with a predetermined interval, and a plurality of gate signal lines 910 provided in parallel to each other in a direction orthogonal to the gate signal line 910 with a predetermined interval. Source signal lines 911 are arranged. A liquid crystal display element 912 is provided at each intersection of the gate signal line 910 and the source signal line 911. Each liquid crystal display element 912 includes a pixel electrode 913, a pixel capacitor 914, and a TFT 915. One end of the pixel capacitor 914 is coupled to the pixel electrode 913, and the other end of the pixel electrode is coupled to the counter electrode 903. The TFT 915 performs on / off control of voltage application to the pixel electrode 913. The source of TFT 915 is coupled to source signal line 911, its gate is coupled to gate signal line 910, and its drain is coupled to pixel electrode 913.

  In the liquid crystal display device 901 having the above configuration, display data input from the outside is input to the source driver unit 904 through the controller 908 as display data D that is a digital signal. Then, the source driver unit 904 time-divides the input display data D and latches it in the plurality of source drivers 905, and then performs D / A (digital / analog) conversion. Then, an analog voltage for gradation display obtained by D / A conversion of the time-division display data D (hereinafter referred to as “gradation display voltage”) is supplied via a source signal line 911. The data is output to the corresponding liquid crystal display element 912 in the liquid crystal panel 902.

  The grayscale display voltage corresponding to the brightness of the display target pixel is applied to the source signal line 911 from the source driver unit 904 shown in FIG. On the other hand, the gate signal line 910 is supplied with a scanning signal for sequentially turning on the TFTs 915 arranged in the column direction from the gate driver unit 906. Then, a gradation display voltage is applied through the source signal line 911 to the pixel electrode 913 connected to the drain of the TFT 915 through the TFT 915 in the on state, and the pixel capacitance 914 between the counter electrode 903 and the TFT 915 is applied. The charge is accumulated in the. Thus, the light transmittance of the liquid crystal changes according to the gradation display voltage, and pixel display is performed.

  FIG. 15 is a waveform diagram showing a liquid crystal drive waveform when the applied voltage of the liquid crystal display device 901 is high, and FIG. 16 is a waveform diagram showing a liquid crystal drive waveform when the applied voltage is low. The source driver drive voltages 925a and 925b are waveforms representing drive voltages by the source driver 905. The gate driver drive voltages 926a and 926b are waveforms representing drive voltages by the gate driver 907. The counter electrode potentials 927a and 927b represent potential waveforms of the counter electrode 903. Pixel electrode voltages 928a and 928b represent voltage waveforms of the pixel electrode 913. Here, the voltage applied to the liquid crystal material is represented by a potential difference between the pixel electrode 913 and the counter electrode 903, and is indicated by hatching in FIGS.

  For example, in the case of FIG. 15, the TFT 915 (FIG. 14) is turned on only during the period when the level of the gate driver drive voltage 926a of the gate driver unit 906 (FIG. 13) is “high”, and the source driver unit 904 (FIG. 13) A voltage representing the difference between the source driver driving voltage 925 a and the counter electrode potential 927 a of the counter electrode 903 is applied to the pixel electrode 914. After that, the level of the gate driver driving voltage 926a of the gate driver unit 906 becomes “low level”, and the TFT 915 is turned off. In that case, since the pixel capacitance 914 exists in the pixel, the above-described voltage is maintained.

  The same applies to the case of FIG. However, FIG. 15 and FIG. 16 show the case where the voltage applied to the liquid crystal material is different, and the applied voltage is higher in the case of FIG. 15 than in the case of FIG. In this way, by changing the voltage applied to the liquid crystal material as an analog voltage, the light transmittance of the liquid crystal is changed in an analog manner to realize multi-gradation display. Note that the number of gradations that can be displayed is determined by the number of analog voltage options applied to the liquid crystal material.

  FIG. 17 is a block diagram showing a schematic configuration of the source driver 905, and FIG. 18 is a block diagram showing a detailed configuration thereof. The source driver 905 includes a shift register 916. The shift register 916 performs a shift operation based on the control signal S1 including the start pulse SP and the clock CK received from the controller 908. Terminal S is a cascade output terminal.

  The source driver 905 is provided with an input latch circuit 917. The input latch circuit 917 latches display data D of a digital signal having display data (DR, DG, and DB) of R (red), G (green), and B (blue). The display data latched by the input latch circuit 917 is stored in the 64 sampling memories 918 by time division according to the shift operation of the shift register 916, respectively.

  Thereafter, the display data stored in each sampling memory 918 is collectively transferred to the hold memory 919 based on a signal (not shown) generated in synchronization with the horizontal synchronization signal from the controller 908.

  The source driver 905 includes a gradation display reference voltage generation circuit 923. The gradation display reference voltage generation circuit 923 generates a gradation display reference voltage of 64 gradations based on the voltage VR supplied from the external reference voltage generation circuit (corresponding to the liquid crystal driving power source 909 in FIG. 13).

  The display data collectively transferred to each hold memory 919 is sent to a D / A conversion circuit (digital / analog conversion circuit) 921 via a level shifter circuit 920, and the level of each level from the gradation display reference voltage generation circuit 923 is sent. It is converted into an analog voltage signal based on the tone display reference voltage. The output circuits 922 output the grayscale display voltages from the liquid crystal drive voltage output terminals 929 to the source signal lines 911 coupled to the liquid crystal display elements 912 (FIG. 14). That is, the number of levels of the gradation display reference voltage generated by the gradation display reference voltage generation circuit 923 is the number of displayable gradations.

  FIG. 19 is a block diagram showing a configuration of the gradation display reference voltage generation circuit 923. The gradation display reference voltage generation circuit 923 generates a plurality of gradation display reference voltages as described above to generate an intermediate voltage. The gradation display reference voltage generation circuit 923 shown in FIG. 19 generates 64 gradation display reference voltages.

  The gradation display reference voltage generation circuit 923 includes terminals for inputting nine reference voltages (half-tone voltages) VI0, VI8, VI16, VI24, VI32, VI40, VI48, VI56, VI63, and γ correction. Eight resistance elements R0 to R7 having a resistance ratio are provided, and 64 kinds of voltages are respectively provided from a part obtained by dividing the resistance element R0 into seven equal parts and a part obtained by dividing each of the resistance elements R1 to R7 into eight equal parts. Signals V0 to V63 are output.

  As described above, a resistance ratio called γ correction is incorporated in the gradation display reference voltage generation circuit 923 provided in the source driver 905 of the source driver unit 904, and is used as a liquid crystal drive output voltage for conversion to the gradation display voltage. The polygonal line characteristic is given by the resistance ratio of γ correction. Therefore, by correcting the optical characteristics of the liquid crystal material based on the ratio of the resistance ratios, natural gradation display can be performed in accordance with the optical characteristics of the liquid crystal material.

  FIG. 20 is a graph showing characteristics relating to the gradation display data of the liquid crystal drive output voltage in the gradation display reference voltage generation circuit 923. The horizontal axis represents gradation display data (digital input), and the vertical axis represents liquid crystal drive output voltage (analog voltage). As shown in FIG. 20, a polygonal line characteristic due to the resistance ratio of γ correction appears. By correcting the optical characteristic of the liquid crystal material based on this polygonal line characteristic, a natural gradation matched to the optical characteristic of the liquid crystal material is obtained. Display can be made.

  Each of the D / A conversion circuits 921 is based on the display data transferred to the hold memory 919, out of the 64 gradation display reference voltages (V0 to V63) generated by the gradation display reference voltage generation circuit 923. One is selected and an analog level signal of the reference voltage is transmitted to the output circuit 922, and the output circuit 922 converts the impedance of the received signal and outputs it from the liquid crystal drive voltage output terminal 929.

  21 is a circuit diagram showing the configuration of the DA conversion circuit 921, FIG. 22A is a diagram for explaining the configuration of the analog switch 930 provided in the DA conversion circuit 921, and FIG. 6 is a diagram for explaining the operation of an analog switch 930. FIG. FIG. 23 is a truth table showing the operation of the DA conversion circuit 921.

  Reference voltage lines for supplying 64 gradation display reference voltages V0 to V63 are arranged in the order of gradation display reference voltages V0, V1, V2,... V62, V63. Each analog switch 930 has a gate G, a source A, and a drain B as shown in FIGS. 22A and 22B, and is turned on when the gate G is “H (high level)”. This is an analog switch that becomes high impedance (Z) when the source A and the drain B are conductive and the gate G is “L (low level)”. The signals D0B, D1B, D2B, D3B, D4B, and D5B are inverted signals of the signals D0, D1, D2, D3, D4, and D5, respectively. The DA conversion circuit 921 outputs one of the 64 gradation display reference voltages V0 to V63 to the output terminal OUT according to the truth table shown in FIG.

17 and 18 has only one circuit in the source driver 905, whereas the D / A converter circuit 921 exists for each output of the source driver 905. The number of circuits is equal to the number of outputs, and there are 20 liquid crystal drive voltage output terminals 929 in the example shown in FIG. Therefore, in order to supply the gradation display reference voltage generated by the gradation display reference voltage generation circuit 923 to each DA conversion circuit 921, each of the gradation display reference voltage generation circuit 923 to each D / A conversion circuit 921 is provided. It is necessary to wire.
Patent No. 3472473 (published Oct. 8, 1999 (1999.10.8)) Yokogawa Electric Corporation Tester Division, “TS6700 Handbook”, manual attached to Yokogawa Electric Tester TS6700, Yokogawa Electric Corporation, June 2001, page 359

  In recent years, multi-gradation and multi-output (for example, 256 gradations, 480 outputs, etc.) of liquid crystal drivers have been developed. In the test of the source driver 5 which is such a multi-gradation, multi-output liquid crystal driver, each DA It is necessary to test whether or not all the gradation voltage values output from the conversion circuit 921 are output as voltage values correctly converted corresponding to the digital image data of each level.

  This is because the source driver 5 is an integrated circuit in which a minute circuit is integrated on silicon, and a minute foreign matter generated in the manufacturing process causes a malfunction of the integrated circuit because the wiring becomes minute.

  As shown in FIG. 18, each reference voltage wiring constituting the reference voltage wiring group 924 has substantially the same length as the long side of the source driver, and the number of reference voltage wirings increases as the number of gradations progresses. The area occupied by the chip increases. For this reason, many defects due to minute foreign matter also occur.

  FIG. 24 is a diagram for explaining the voltage fluctuation of each reference voltage wiring when the foreign object 936 is sandwiched between the adjacent reference voltage wirings. 25A and 25B are diagrams for explaining the influence of the resistance value of the foreign material 936 on the output voltage from the DA converter circuit 921 in the state of FIG.

  FIG. 24 shows an example in which a foreign object 936 is sandwiched between a reference voltage wiring that supplies the gradation display reference voltage V16 and a reference voltage wiring that supplies the gradation display reference voltage V17. The potential difference between both reference voltage wirings is a potential difference for one gradation.

  As shown in FIG. 25A, in the gradation display reference voltage generation circuit 923 that divides 0V to 5V using 63 equal resistors to create 64 gradations, the entire resistance value is 20 kΩ (20, 000Ω), the resistance value for generating one gradation is about 317.46Ω (20 kΩ ÷ 63≈317.46Ω), so the voltage of one gradation is about 79.37 mV (5V × 317.46Ω ÷ 20 kΩ). ≈ 0.07937V).

  When a foreign object 936 having a resistance value of 1 kΩ (1000Ω) is sandwiched between gradations, the combined resistance of the sandwiched gradation is that the resistance of 31.46Ω for one gradation and the resistance of the foreign substance are connected in parallel. Therefore, it becomes approximately 240.96 Ω (1 / ((1 / 317.46) + (1/1 kΩ)) ≈240.96 Ω), and the resistance value of one original gradation from 317.46 Ω to 76.5 Ω. fluctuate. For this reason, the entire resistance value varies from 20 kΩ to 19.9235 kΩ (about 19,924 Ω). At this time, the voltage at the corresponding location is approximately 60.47 mV (5 V × 240.96Ω ÷ 19.9235 kΩ≈0.0605), and the variation from the original voltage 79.37 mV due to the foreign object 936 being caught is 18. 9 mV (79.37-60.47 = 18.9).

  Since the voltage resolution of the measurement tester is about 1 mV (for example, according to the handbook of Non-Patent Document 1 of Tester TS6700 manufactured by Yokogawa Electric Corporation, it is 977 μV in the measurement range of −8V to + 8V), The fluctuation voltage of 18.9 mV can be detected, and the source driver 5 can be determined to be defective.

  On the other hand, when a foreign substance 936 having a resistance value of 100 kΩ (100,000Ω) is sandwiched between gradations as shown in FIG. 25B, the combined resistance of the sandwiched gradation is the resistance for one gradation. Since 317.5Ω and the resistance of the foreign material 936 are considered to be connected in parallel, it is about 316.46Ω (1 / ((1 / 317.46) + (1 / 100k)) ≈316.46). The original resistance value of one gradation varies from 31.46Ω to 1Ω. Therefore, the overall resistance value varies from 20 kΩ to 19.999 kΩ (19999Ω). The voltage at the corresponding location is about 79.12 mV (5 V × 316.46Ω ÷ 19.999 kΩ≈0.07912), and the variation from the original voltage 79.37 mV is 0.25 mV (79.37−79.12 = 0). .25). Therefore, depending on the voltage resolution of 1 mV of the measurement tester described above, the fluctuation voltage due to the foreign object 936 being caught cannot be detected, and thus there is a problem that the foreign object 936 cannot be detected. Such a voltage fluctuation of 1 mV or less does not affect the display on the liquid crystal panel, but it is necessary to detect foreign matter in order to improve the quality of the source driver.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to reliably detect a foreign substance having a large resistance value sandwiched between reference voltage wirings adjacent to each other. An object of the present invention is to provide a display driving integrated circuit and a wiring arrangement determining method for the display driving integrated circuit capable of improving the quality of the circuit.

  In order to solve the above problems, a display drive integrated circuit according to the present invention generates a gray scale display reference voltage generation circuit that generates a gray scale display reference voltage of n gray scales (n is an integer of 2 or more), and the n A DA conversion circuit that converts display data into analog based on a gradation display reference voltage of gradation, and a DA conversion of each of the n gradation display reference voltages generated by the gradation display reference voltage generation circuit N reference voltage wirings provided in parallel to each other for supplying to the circuit, and the n reference voltage wirings so that two reference voltage wirings adjacent to each other have a potential difference of two or more gradations. It is characterized by being arranged in.

  According to the above feature, n reference voltage wirings provided in parallel with each other to supply each of the n gray scale display reference voltages to the DA converter circuit are adjacent to each other. Are arranged so as to have a potential difference of two gradations or more, the potential difference between two reference voltage wirings adjacent to each other becomes large. For this reason, even if a foreign object having a large resistance value is sandwiched between adjacent reference voltage wires, the variation value of the potential difference between the reference voltage wires due to the sandwiched foreign material can be made larger than the resolution of the measuring instrument. Therefore, a foreign substance having a large resistance value sandwiched between adjacent reference voltage wirings can be reliably detected, and the quality of the display driving integrated circuit can be improved.

  As means for realizing the above arrangement, in the display driving integrated circuit according to the present invention, the n reference voltage wirings (n is an integer of 2 or more and an even number) are represented by the formula = n / 2 + 1 gradation, 1 Gradation, n / 2 + 2 gradation, 2 gradations ... n / 2 + (n / 2-1) gradation, n / 2-1 gradation, n / 2 + n / 2 gradation, n / 2 gradation, It is preferable that they are arranged in the order determined by.

  According to the above configuration, the reference voltage wiring from 1 gradation to n / 2 gradation and the reference voltage wiring from n / 2 + 1 gradation to n / 2 + n / 2 gradation can be alternately arranged. The n reference voltage wirings can be easily arranged so that two adjacent reference voltage wirings have a potential difference of two gradations or more.

  It should be noted that the present invention can also be applied to some gradations of the entire n gradations.

  When the present invention is expressed including a part of the n gradations, the following expression is obtained.

  Formula = intermediate gradation + 1, first gradation, intermediate gradation + 2, first gradation + 1, intermediate gradation + 3, first gradation + 2,... Intermediate gradation + number of gradations / 2-2, intermediate floor Tone-2, intermediate gradation + number of gradations / 2-1, intermediate gradation-1, intermediate gradation + number of gradations / 2, intermediate gradation.

here,
The first gradation is an integer greater than or equal to 1 and is the first gradation in the even gradation range represented by the continuous integer among the 1 gradation to the n gradation represented by the continuous integer. Yes,
The last gradation is an integer of 2 or more, and is the last gradation in the gradation range;
1 ≦ first gradation <last gradation ≦ n gradation,
Number of gradations = last gradation−first gradation + 1 (however, the number of gradations is even)
Intermediate gradation = first gradation + number of gradations / 2-1
It is.

  In order to solve the above problems, the wiring arrangement determination method for the display driving integrated circuit according to the present invention is arranged in parallel to supply each of the gradation display reference voltages of n gradations (n is an integer of 2 or more). The arrangement of the n reference voltage wirings provided in is determined so that two reference voltage wirings adjacent to each other have a potential difference of two gradations or more.

  According to the above feature, the arrangement of the n reference voltage wirings provided in parallel to each other to supply each of the n gray scale display reference voltages is such that the two reference voltage wirings adjacent to each other are arranged on the second floor. Since it is determined to have a potential difference equal to or higher than the key, the potential difference between two reference voltage wirings adjacent to each other increases. For this reason, even if a foreign object having a large resistance value is sandwiched between adjacent reference voltage wires, the variation value of the potential difference between the reference voltage wires due to the sandwiched foreign material can be made larger than the resolution of the measuring instrument. Therefore, a foreign substance having a large resistance value sandwiched between adjacent reference voltage wirings can be reliably detected, and the quality of the display driving integrated circuit can be improved.

  In the display drive integrated circuit according to the present invention, the gray scale display reference voltage generation circuit may include a test circuit provided to provide a potential difference corresponding to the drive voltage between two adjacent reference voltage lines. preferable.

  In the display drive integrated circuit according to the present invention, the test circuit includes a first switch group provided to apply a first voltage to each of the odd-numbered reference voltage wirings among the n reference voltage wirings; A second switch group provided to apply a second voltage to each of the even-numbered reference voltage wirings, and a potential difference between the first voltage and the second voltage is a potential difference corresponding to the driving voltage. Preferably there is.

  As described above, the display driving integrated circuit according to the present invention includes n reference voltage wirings provided in parallel to each other to supply each of the n gradation display reference voltages to the DA converter circuit. Since the two adjacent reference voltage wirings are arranged so as to have a potential difference of two or more gradations, it is possible to reliably detect defects in the reference voltage wirings adjacent to each other, and the quality of the display driving integrated circuit. The effect that can be improved.

  As described above, the wiring arrangement determining method for the display driving integrated circuit according to the present invention is an arrangement of n reference voltage wirings provided in parallel to each other to supply each of the n gradation display reference voltages. Is determined so that two reference voltage wirings adjacent to each other have a potential difference of two or more gradations. Therefore, the above-described wiring arrangement can be easily realized by applying to automatic placement wiring and the like. A defect in the voltage wiring can be reliably detected, and the quality of the display drive integrated circuit can be improved.

  An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows an embodiment of the present invention, and is a block diagram showing a main configuration of a liquid crystal display device 1. FIG. 2 is a circuit diagram showing a main configuration of the liquid crystal panel 2 provided in the liquid crystal display device 1.

  The liquid crystal display device 1 is a TFT (thin film transistor) type liquid crystal display device which is a typical example of an active matrix type. The liquid crystal display device 1 includes a liquid crystal display unit 34 and a liquid crystal drive circuit (liquid crystal drive unit) 35 that drives the liquid crystal display unit 34. The liquid crystal display unit 34 includes the TFT type liquid crystal panel 2. In the liquid crystal panel 2, a liquid crystal display element 12 (FIG. 2) and a counter electrode (common electrode) 3 which will be described in detail later are provided.

  On the other hand, the liquid crystal driving circuit 35 includes a source driver unit 4 and a gate driver unit 6, which are made of an IC (integrated circuit), a controller 8, and a liquid crystal driving power source 9. The controller 8 supplies the display data D and the control signal S1 to the source driver unit 4 and supplies the control signal S2 to the gate driver unit 6.

  The liquid crystal panel 2 includes a plurality of gate signal lines 10 provided parallel to each other with a predetermined interval, and a plurality of gate signal lines 10 provided parallel to each other in a direction orthogonal to the gate signal line 10 with a predetermined interval. Source signal lines 11 are arranged. A liquid crystal display element 12 is provided at each intersection of the gate signal line 10 and the source signal line 11. Each liquid crystal display element 12 includes a pixel electrode 13, a pixel capacitor 14, and a TFT 15. One end of the pixel capacitor 14 is coupled to the pixel electrode 13, and the other end of the pixel electrode is coupled to the counter electrode 3. The TFT 15 performs on / off control of voltage application to the pixel electrode 13. The source of the TFT 15 is coupled to the source signal line 11, its gate is coupled to the gate signal line 10, and its drain is coupled to the pixel electrode 13.

  In the liquid crystal display device 1 having the above configuration, display data input from the outside is input to the source driver unit 4 as display data D that is a digital signal via the controller 8. Then, the source driver unit 4 time-divides the input display data D and latches it in the plurality of source drivers 5, and then performs D / A (digital / analog) conversion. Then, an analog voltage for gradation display obtained by D / A conversion of the time-division display data D (hereinafter referred to as “gradation display voltage”) is supplied via the source signal line 11. The data is output to the corresponding liquid crystal display element 12 in the liquid crystal panel 2.

  The grayscale display voltage corresponding to the brightness of the display target pixel is applied to the source signal line 11 from the source driver unit 4 shown in FIG. On the other hand, the gate signal line 10 is supplied with a scanning signal for sequentially turning on the TFTs 15 arranged in the column direction from the gate driver unit 6. Then, a gradation display voltage is applied through the source signal line 11 to the pixel electrode 13 connected to the drain of the TFT 15 through the TFT 15 in the on state, and the pixel capacitance 14 between the counter electrode 3 and the TFT 15 is applied. The charge is accumulated in the. Thus, the light transmittance of the liquid crystal changes according to the gradation display voltage, and pixel display is performed.

  3 is a waveform diagram showing a liquid crystal driving waveform when the applied voltage of the liquid crystal display device 1 is high, and FIG. 4 is a waveform diagram showing a liquid crystal driving waveform when the applied voltage is low. The source driver drive voltages 25a and 25b are waveforms representing drive voltages by the source driver 5. The gate driver drive voltages 26a and 26b are waveforms representing the drive voltage by the gate driver 7. The counter electrode potentials 27a and 27b represent potential waveforms of the counter electrode 3. The pixel electrode voltages 28 a and 28 b represent the voltage waveform of the pixel electrode 3. Here, the voltage applied to the liquid crystal material is represented by a potential difference between the pixel electrode 13 and the counter electrode 3, and is indicated by hatching in FIGS.

  For example, in the case of FIG. 3, the TFT 15 (FIG. 2) is turned on only during the period when the level of the gate driver drive voltage 26a of the gate driver unit 6 (FIG. 1) is “high”, and the source driver unit 4 (FIG. 1) A voltage representing the difference between the source driver drive voltage 25 a and the counter electrode potential 27 a of the counter electrode 3 is applied to the pixel electrode 14. Thereafter, the level of the gate driver driving voltage 26a of the gate driver unit 6 becomes “low level”, and the TFT 15 is turned off. In that case, since the pixel capacitance 14 exists in the pixel, the above-described voltage is maintained.

  The same applies to the case of FIG. However, FIG. 3 and FIG. 4 show a case where the voltage applied to the liquid crystal material is different. In FIG. 3, the applied voltage is higher than that in FIG. In this way, by changing the voltage applied to the liquid crystal material as an analog voltage, the light transmittance of the liquid crystal is changed in an analog manner to realize multi-gradation display. Note that the number of gradations that can be displayed is determined by the number of analog voltage options applied to the liquid crystal material.

  FIG. 5 is a block diagram showing a schematic configuration of the source driver 5, and FIG. 6 is a block diagram showing a detailed configuration of the source driver 5. The source driver 5 includes a shift register 16. The shift register 16 performs a shift operation based on the control signal S1 including the start pulse SP and the clock CK received from the controller 8. Terminal S is a cascade output terminal.

  The source driver 5 is provided with an input latch circuit 17. The input latch circuit 17 latches display data D of a digital signal having display data (DR, DG, and DB) of R (red), G (green), and B (blue). The display data latched by the input latch circuit 17 is stored in the 64 sampling memories 18 by time division in accordance with the shift operation of the shift register 16.

  Thereafter, the display data stored in each sampling memory 18 is collectively transferred to the hold memory 19 based on a signal (not shown) generated in synchronization with the horizontal synchronizing signal from the controller 8.

  The source driver 5 includes a gradation display reference voltage generation circuit 23. The gradation display reference voltage generation circuit 23 generates a gradation display reference voltage of 64 gradations based on a voltage VR supplied from an external reference voltage generation circuit (corresponding to the liquid crystal drive power supply 9 in FIG. 1).

  The display data collectively transferred to each hold memory 19 is sent to a D / A conversion circuit (digital / analog conversion circuit) 21 through a level shifter circuit 20, and each level supplied from the gradation display reference voltage generation circuit 23. Is converted into an analog voltage signal based on the gradation display reference voltage. Each output circuit 22 outputs the gradation display voltage from each liquid crystal driving voltage output terminal 29 to the source signal line 911 coupled to each liquid crystal display element 12 (FIG. 2). That is, the number of gradation display reference voltages generated by the gradation display reference voltage generation circuit 23 (for example, 64 levels) is the number of displayable gradations (for example, 64 gradations).

  FIG. 7 is a block diagram showing a configuration of the gradation display reference voltage generation circuit 23 provided in the source driver 5. The gradation display reference voltage generation circuit 23 generates a plurality of gradation display reference voltages as described above to generate an intermediate voltage. The gradation display reference voltage generation circuit 23 shown in FIG. 7 generates 64 gradation display reference voltages.

  The gradation display reference voltage generation circuit 23 has nine reference voltages (half-tone voltages) VI0, VI8, VI16, VI24, VI32, VI40, VI48, VI56, and VI63, respectively, and γ correction. The resistance elements R0, R1, R2, R3, R4, R5, R6, and R7 are connected in series with each other, and the resistance element R0 is divided into seven equal parts. 64 types of voltage signals (gradation display reference voltages V0, V1, V2,..., V61, V62, and V63) are output from each of R1 to R7 divided into eight equal parts.

  As described above, the gradation display reference voltage generation circuit 23 provided in the source driver 5 incorporates a resistance element connected in series with a resistance ratio called γ correction, and converts it into the gradation display voltage. The liquid crystal driving output voltage is given a polygonal line characteristic by a resistance ratio of γ correction. Therefore, by correcting the optical characteristics of the liquid crystal material based on the ratio of the resistance ratios, natural gradation display can be performed in accordance with the optical characteristics of the liquid crystal material.

  Each D / A conversion circuit 21 is one of 64 gradation display reference voltages V0 to V63 generated by the gradation display reference voltage generation circuit 23 based on the display data transferred to the hold memory 19. The analog signal of the selected gradation display reference voltage is transmitted to the output circuit 22, and the output circuit 22 converts the impedance of the received signal and outputs it from the liquid crystal drive voltage output terminal 29.

  FIG. 8 is a circuit diagram for explaining the configuration of the DA conversion circuit 21 provided in the source driver 5, and FIG. 9A is a diagram for explaining the configuration of the analog switch 30 provided in the DA conversion circuit 21. FIG. 9B is a diagram for explaining the operation of the analog switch 30. FIG. 10 is a truth table showing the operation of the DA converter circuit 21.

  The DA converter circuit 21 is coupled with 64 reference voltage lines for supplying 64 gradation display reference voltages V0 to V63 from the gradation display reference voltage generation circuit 23, respectively. The gradation display reference voltage Vk (0 ≦ k ≦ 63) is a gradation display reference voltage of (k + 1) gradation. Therefore, for example, the gradation display reference voltage V0 is a gradation display reference voltage for one gradation, the gradation display reference voltage V1 is a gradation display reference voltage for two gradations, and the gradation display reference voltage V2 is 3 This is a gradation display reference voltage for gradation. The gradation display reference voltage V31 is a gradation display reference voltage of 32 gradations, and the gradation display reference voltage V32 is a gradation display reference voltage of 33 gradations. The gradation display reference voltage V62 is a gradation display reference voltage of 63 gradations, and the gradation display reference voltage V63 is a gradation display reference voltage of 64 gradations.

  The 64 reference voltage wirings are arranged in parallel to each other from the gradation display reference voltage generation circuit 23 toward the DA conversion circuit 21, and each reference voltage wiring is connected to the DA display circuit from the gradation display reference voltage generation circuit 23. The gradation of the gradation display reference voltage supplied to 21 is “n / 2 + 1 gradation, 1 gradation, n / 2 + 2 gradation, 2 gradations,... N / 2 + (n / 2-1) gradation, They are arranged in the order of “n / 2-1 gradation, n / 2 + n / 2 gradation, n / 2 gradation”.

  In the example shown in FIG. 8, since n = 64, “33 gradations (gradation display reference voltage V32), 1 gradation (gradation display reference voltage V0), 34 gradations (gradation display reference voltage V33). 2 gradations (gradation display reference voltage V1) ... 63 gradations (gradation display reference voltage V62), 31 gradations (gradation display reference voltage V30), 64 gradations (gradation display reference voltage V63) , 32 gradations (gradation display reference voltage V31) ”.

  Therefore, the potential difference between two reference voltage wirings adjacent to each other is a potential difference of 32 gradations or a potential difference of 33 gradations. Therefore, the potential difference between two reference voltage wirings adjacent to each other is more than 32 gradations. have.

  Here, between two reference voltage wirings having a potential difference of 32 gradations (for example, between the reference voltage wiring of the gradation display reference voltage V32 and the reference voltage wiring of the gradation display reference voltage V0), 100 kΩ. Consider a case where a foreign object having a large resistance value is caught.

  When there is no foreign matter, the potential difference for 32 gradations between the reference voltage wiring of the gradation display reference voltage V32 and the reference voltage wiring of the gradation display reference voltage V0 is 2539.84 mV (79.37 mV × 32). Become. The value of the combined resistance between the reference voltage wiring of the gradation display reference voltage V32 and the reference voltage wiring of the gradation display reference voltage V0 when a foreign object having a large resistance value of 100 kΩ is sandwiched is about 9090Ω (1 /((1/(317.46×32))+(1/100k))≈9090). Therefore, the resistance value of 10258.72Ω (= 317.46Ω × 32) of the original 32 gradations varies by 1068.72Ω.

  Therefore, the overall resistance value varies from 20 kΩ to 18.931 kΩ. Accordingly, the voltage between the reference voltage wiring of the gradation display reference voltage V32 and the reference voltage wiring of the gradation display reference voltage V0 at the corresponding portion is about 2400 mV (5 V × 9.090 kΩ ÷ 18.931 kΩ≈2400 mV). Therefore, the variation from the original voltage 2539.84 mV is 239.84 mV (2539.84 mV−2400 mV = 239.84 mV), which is much larger than the resolution of 1 mV of the measuring instrument. Therefore, a foreign substance having a large resistance value of 100 kΩ can be detected.

  As shown in FIG. 9A, each analog switch 30 has a gate G, a source A, and a drain B, and is turned on when the gate G is “H (high level)”. This is an analog switch that conducts to the drain B and becomes high impedance (Z) when the gate G is “L (low level)”. The signals D0B, D1B, D2B, D3B, D4B, and D5B are inverted signals of the signals D0, D1, D2, D3, D4, and D5, respectively. The DA conversion circuit 21 outputs one of the 64 gradation display reference voltages V0 to V63 to the output terminal OUT according to the truth table shown in FIG.

  Here, a case where a netlist (transistor wiring information) is extracted from the circuit diagram of the present embodiment shown in FIG. 8 and the conventional circuit diagram of FIG. 21 will be considered. Since the order of the gradation display reference voltages V0 to V63 is not considered in the net list, the net list of the circuit diagram of the present embodiment and the net list of the conventional circuit diagram are exactly the same. Therefore, when the layout for increasing the gradation voltage difference, which is the object of the present invention, is performed from the circuit diagram of FIG. 8, the wiring information of the transistor, which is netlist information from the circuit diagram of FIG. It is necessary to extract together with the order information of the voltages V0 to V63. The above-described wiring arrangement determination method (development method) can create this order information.

  That is, with respect to the conventional circuit diagram of FIG. 21, by performing the placement and wiring in which the above expansion method is incorporated in the algorithm, the reference voltage wiring placement and the layout for increasing the difference between adjacent gradation display reference voltages are performed. Therefore, it is possible to easily obtain a transistor arrangement convenient for the above. This technique is particularly important when performing automatic placement and routing using a computer, but can also be employed when performing layout manually.

  FIG. 11 is a circuit diagram showing another configuration of the DA conversion circuit 21 provided in the source driver 5, and FIG. 12 is a truth table showing the operation of the other configuration of the DA conversion circuit 21.

  In the example shown in FIG. 11 and FIG. 12, the wiring arrangement determination method described above with reference to FIGS. 8 to 10 is performed using 16 types of gradation display reference voltages V0 to V15 obtained by dividing 64 gradations into four, gradation display reference. In this example, the voltages V16 to V31, the gradation display reference voltages V32 to V47, and the gradation display reference voltages V48 to V63 are implemented. Development (rearrangement) is performed on the reference voltage wirings for 8 gradations corresponding to the signals D0, D1, D2, and D3.

  This development (rearrangement) will be explained by the following formula expressed as a general formula.

Formula = intermediate gradation + 1, first gradation, intermediate gradation + 2, first gradation + 1, intermediate gradation + 3, first gradation + 2,... Intermediate gradation + number of gradations / 2-2, intermediate floor Tone-2, intermediate gradation + number of gradations / 2-1, intermediate gradation-1, intermediate gradation + number of gradations / 2, number of gradations / 2,
here,
The first gradation is an integer greater than or equal to 1 and is the first gradation in a gradation range represented by a continuous integer to which the invention is applied, among 1 to n gradations represented by a continuous integer. Suppose that the last gradation is an integer greater than or equal to 2 and is the last gradation in the gradation range, and the relationship of the respective sizes is 1 ≦ first gradation <last gradation ≦ When n gradations are used,
Number of gradations = last gradation−first gradation + 1 (however, the number of gradations is an even number),
Intermediate gradation = first gradation + number of gradations / 2-1
And

  When the above formula is applied from 1 to 16 gradations (V0 to V15), the first gradation is 1 (V0) and the last gradation is 15 (V16). The number of gradations is 16-1 + 1 = 16, and intermediate gradation = 1 + 16 / 2-1 = 8.

When calculating the arrangement order of gradations by applying the above formula (the calculated value of the number of gradations is indicated in parentheses),
Expression = intermediate gradation + 1 (9), first gradation (1), intermediate gradation + 2 (10), first gradation + 1 (2), intermediate gradation + 3 (11), first gradation + 2 (3 )... Intermediate gradation + number of gradations / 2-2 (14), intermediate gradation-2 (6), intermediate gradation + number of gradations / 2-1 (15), intermediate gradation-1 (7) ), Intermediate gradation + number of gradations / 2 (16), intermediate gradation (8),
It becomes.

The result of this development is expressed as a gradation signal
V8, V0, V9, V1, V10, V2... V13, V5, V14, V6, V15, V7, and the arrangement order of V0 to V15 shown in FIG.

Similarly, when the above formula is applied from 17 gradations to 32 gradations, the first gradation is 17 (V16) and the last gradation is 32 (V31). The number of gradations is 32-17 + 1 = 16, intermediate gradation = 17 + 16 / 2-1 = 24, and the result is
25 (V24), 17 (V16), 26 (V25), 18 (V17), 27 (V26), 19 (V18) ......... 30 (V29), 22 (V21), 31 (V30), 23 (V22) ), 32 (V31), 24 (V23),
Thus, the arrangement order is from V16 to V31 shown in FIG.

  The same calculation can be performed for V32 to V47 and V48 to V63.

  As shown in FIG. 11, it is possible to carry out the development for a part of the gradations, not the entire n gradations. In this configuration, two reference voltage wirings adjacent to each other have a potential difference of 8 gradations or more.

  For the convenience of explanation, the above expansion method has been described using a 64-gradation D / A conversion circuit, but the present invention is not limited to this. The development method described above is also effective for a D / A conversion circuit (for example, 256 gradations) having more gradations than 64 gradations and a D / A conversion circuit (for example, 8 gradations) having few gradations.

  In addition, an example in which two reference voltage wirings adjacent to each other have a potential difference of 32 gradations or more and an example of a potential difference of 8 gradations or more has been described, but the present invention is not limited to this. Not. For example, in the case of the state shown in FIG. 25B, two reference voltage wirings adjacent to each other need only have a potential difference of two gradations or more.

  In the state shown in FIG. 25B, the wiring order is changed to 3 gradations, 1 gradation, 4 gradations, 2 so that there is a reference voltage wiring having a potential difference of 2 gradations. In terms of gradation, the potential difference between the 3 gradation wiring and the 1 gradation wiring and the potential difference between the 4 gradation wiring and the 2 gradation wiring are two gradations. In this case, for example, when there is no foreign matter, the potential difference for two gradations between the three gradation wiring and the one gradation wiring adjacent to each other is 158.74 mV (79.37 mV × 2). The value of the combined resistance between the three-level wiring and the one-level wiring adjacent to each other when a foreign object is sandwiched is about 630.005 Ω (1 / ((1 / (317.46 × 2) ) + (1 / 100k)) ≈630.005). Then, the resistance value of the original two gradations varies from 4.94.92 (= 317.46 Ω × 2) to 4.915 Ω.

  Therefore, the overall resistance value varies from 20 kΩ to 19.995 kΩ. Therefore, the voltage between the three-level wiring and the one-level wiring at the corresponding location is approximately 157.54 mV (5 V × 630.005 Ω ÷ 19.9995 kΩ≈0.15754). Therefore, the fluctuation from the original voltage of 158.74 mV is 1.20 mV (158.74 mV−157.54 mV = 1.20 mV), which is larger than the resolution of the measuring instrument, 1 mV. Therefore, a foreign object can be detected.

  The foreign matter detected by the gradation wiring method can be detected only when the wiring is already short-circuited. Even if foreign matter exists between the wirings, it is difficult to detect by a normal test if there is a thin insulating film between the foreign matter and the wirings. Such a foreign substance may cause a short circuit due to the foreign substance due to destruction of the insulating film during use of the device. For this reason, usually, screening is performed by a technique called a stress test in which voltage fluctuation is applied to a part that is likely to be destroyed during use, and the part is first broken and is not shipped to the market.

  However, according to the above-described gradation wiring arrangement method, the voltage difference between the gradation voltage wirings is larger than that of the conventional wiring arrangement, but when the maximum voltage of the gradation voltage is the same as the drive voltage (VCC) of the device, The maximum voltage difference applied between the gradation voltage wirings is VCC / 2. This leaves room for improvement in efficiency for the stress test.

  Therefore, a test circuit shown in FIG. 26 is provided in order to further improve the foreign substance detection capability of the circuit according to the present embodiment. FIG. 26 is a diagram showing the gradation display reference voltage generation circuit 23a. A test circuit 101 for improving the foreign matter detection capability is added to the gradation display reference voltage generation circuit 23 described above with reference to FIG. Note that reference numeral 110 in FIG. 26 denotes a wiring conversion area, which is also provided in the gradation display reference voltage generation circuit 23 in FIG. 7 and is rearranged in the same manner, but is not shown in FIG. . In the wiring conversion area 110, the voltages V0 to V63 created by resistance division are rearranged in the order shown in FIG. The voltages V0 to V63 are rearranged by the wiring conversion area 110 and wired toward the D / A conversion circuits 21. That is, the lines after the wiring conversion area 110 shown in FIG. 26 have the same arrangement order of the wirings V0 to V63 of the actual device. However, in FIG. 8, the voltage V32 is shown on the uppermost side and the voltage V31 is shown on the lowermost side. However, in FIG. 26, on the contrary, the voltage V31 is shown on the uppermost side and the voltage V32 is Shown at the bottom.

  The test circuit 101 includes a switch group 102 that cuts off the voltage generated by R0 to R7 in the test mode, and a switch group 103 (first switch) provided to give a signal to the generated voltage 24 from V0 to V63 in the test mode. Group) and a switch group 104 (second switch group), and inverters 105 and 106 which receive a signal STRESS for determining the value of the generated voltage 24 in the test mode. The configuration of each switch in the switch groups 104 and 103 is the same as the configuration shown in FIG.

  In the test mode, the signal TEST becomes “H” and TESTB becomes “L”. For this reason, the gradation voltage generated by the resistors R0 to R7 when the switch group 102 is turned off is not reflected in the generated voltage 24. The signal STRESS is a signal given from the outside of the gradation display reference voltage generation circuit 23a in the test mode, and the “H” level corresponds to the operating voltage of the gradation display reference voltage generation circuit 23a, and the “L” level is the reference. This corresponds to the GND level of the voltage generation circuit 23a. The signal STRESS is inverted by the inverter 105 and supplied to the odd-numbered line from the top in FIG. 26 by the switch group 103 that is turned on in the test mode. The signal STRESS further inverted by the inverter 106 is supplied to the even-numbered line from the top in FIG. 26 by the switch group 104 which is turned on in the test mode.

  That is, when the STRESS signal is at “H” level, the voltage of the odd-numbered gradation line supplied by the switch group 103 is “L” level (first voltage), and the even-numbered gradation supplied by the switch group 104. The voltage of the line becomes “H” level (second voltage). Conversely, when the STRESS signal is at “L” level, the odd-numbered gradation lines supplied by the switch group 103 are “H” level, and the even-numbered gradation lines supplied by the switch group 104 are “L” level. Become.

  As described above, in the test mode, the voltage difference between adjacent gradation lines becomes the GND level from the operating voltage of the device, and is the maximum voltage difference in the device. By switching the STRESS signal between “H” and “L”, stress is applied at the maximum voltage between the gradation lines, and the screening efficiency is improved.

  In this way, by combining the gradation wiring method and the stress test method, the sensitivity for detecting foreign matter in the gradation wiring part can be further improved.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

  The present invention relates to a gradation display reference voltage generation circuit that generates a gradation display reference voltage at a gradation level, a DA conversion circuit that converts display data into analog based on the gradation display reference voltage, and the gradation display reference. The present invention can be applied to a display driving integrated circuit having a reference voltage wiring for supplying a voltage to a DA converter circuit and a wiring arrangement determining method for the display driving integrated circuit.

1, showing an embodiment of the present invention, is a block diagram illustrating a main configuration of a liquid crystal display device. FIG. It is a circuit diagram which shows the principal part structure of the liquid crystal panel provided in the said liquid crystal display device. It is a wave form diagram which shows a liquid crystal drive waveform when the applied voltage of the said liquid crystal display device is high. It is a wave form diagram which shows a liquid crystal drive waveform when the applied voltage of the said liquid crystal display device is low. It is a block diagram which shows schematic structure of the source driver provided in the said liquid crystal display device. It is a block diagram which shows the detailed structure of the said source driver. It is a block diagram which shows the structure of the gradation display reference voltage generation circuit provided in the said source driver. It is a circuit diagram which shows the structure of the DA converter circuit provided in the said source driver. (A) is a figure for demonstrating the structure of the analog switch provided in the said DA converter circuit, (b) is a figure for demonstrating operation | movement of the said analog switch. It is a truth table which shows operation | movement of the said DA converter circuit. It is a circuit diagram which shows the other structure of the DA converter circuit provided in the said source driver. It is a truth table which shows operation | movement of the other structure of the said DA converter circuit. It is a block diagram which shows a prior art and shows the principal part structure of a liquid crystal display device. It is a circuit diagram which shows the principal part structure of the liquid crystal panel provided in the said liquid crystal display device. It is a wave form diagram which shows a liquid crystal drive waveform when the applied voltage of the said liquid crystal display device is high. It is a wave form diagram which shows a liquid crystal drive waveform when the applied voltage of the said liquid crystal display device is low. It is a block diagram which shows schematic structure of the source driver provided in the said liquid crystal display device. It is a block diagram which shows the detailed structure of the said source driver. It is a block diagram which shows the structure of the gradation display reference voltage generation circuit provided in the said source driver. It is a graph which shows the characteristic regarding the gradation display data of the liquid crystal drive output voltage in the said gradation display reference voltage generation circuit. It is a circuit diagram which shows the structure of the DA converter circuit provided in the said source driver. (A) is a figure for demonstrating the structure of the analog switch provided in the said DA converter circuit, (b) is a figure for demonstrating operation | movement of the said analog switch. It is a truth table which shows operation | movement of the said DA converter circuit. It is a figure for demonstrating the foreign material pinched | interposed between mutually adjacent reference voltage wiring. (A) And (b) is a figure for demonstrating the influence which the foreign material pinched | interposed between mutually adjacent reference voltage wiring has on the output voltage from a DA converter circuit. It is a block diagram which shows the other structure of the said gradation display reference voltage generation circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 2 Liquid crystal panel 3 Counter electrode 4 Source driver part (Display drive integrated circuit)
DESCRIPTION OF SYMBOLS 5 Source driver 6 Gate driver part 7 Gate driver 8 Controller 9 Liquid crystal drive power supply 21 DA converter circuit 23 Gradation display reference voltage generation circuit 24 Reference voltage wiring group 101 Test circuit 103 Switch group (1st switch group)
104 Switch group (second switch group)

Claims (3)

a gradation display reference voltage generation circuit for generating gradation display reference voltages of n gradations (n is an even number of 8 or more);
A DA conversion circuit for analog conversion of display data based on the n gradation display reference voltage;
N reference voltage wirings provided in parallel to each other to supply each of the n gradation display reference voltages generated by the gradation display reference voltage generation circuit to the DA converter circuit,
The n reference voltage wirings are integers of 1 or more, and are represented by continuous integers from 1 gradation to n gradations represented by successive integers, and a gradation range having an even number of gradations Divided into two or more groups comprising
The first tone in each divided group, and the gradation represented by the smallest integer prior SL tone range,
The final gradation is an integer greater than or equal to 2 and represented by the largest integer in the gradation range,
1 ≦ first gradation <last gradation ≦ n gradation,
Number of gradations = last gradation−first gradation + 1 (however, the number of gradations is even)
Intermediate gradation = first gradation + number of gradations / 2-1
And when
Reference voltage wirings for even gradations represented by successive integers included in the n gradations are as follows:
Formula = intermediate gradation + 1, first gradation, intermediate gradation + 2, first gradation + 1, intermediate gradation + 3, first gradation + 2,... Intermediate gradation + number of gradations / 2-2, intermediate floor Tone-2, intermediate gradation + number of gradations / 2-1, intermediate gradation-1, intermediate gradation + number of gradations / 2, intermediate gradation,
The n reference voltage lines are arranged in the order determined in accordance with the above, so that the difference in the gradation value of the gradation display reference voltage supplied to each of the two adjacent reference voltage lines is different. An integrated circuit for display driving characterized by having two or more gradations .   2. The display drive integrated circuit according to claim 1, wherein the gradation display reference voltage generation circuit includes a test circuit provided to give a potential difference corresponding to the drive voltage between two adjacent reference voltage lines. The test circuit includes a first switch group provided to apply a first voltage to each of odd-numbered reference voltage wirings among the n reference voltage wirings;
A second switch group provided for applying a second voltage to each of the even-numbered reference voltage wirings;
3. The display driving integrated circuit according to claim 2 , wherein the potential difference between the first voltage and the second voltage is a potential difference corresponding to the driving voltage.

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