JP4710158B2 - Driving method and driving apparatus for memory cholesteric liquid crystal display device - Google Patents

Description

【００９６】
【化２】

【００９７】
【化３】

【００９８】
空セルに液晶Ａを真空注入法で注入し、注入孔を紫外線硬化材で封止して液晶パネルを作製した。電極数は、行電極２４０ライン、列電極３２０ラインであり、解像度は約１００ｄｐｉである。この液晶パネルの片方の基板を艶消し用の黒色塗料をスプレーすることで均一に塗装した。
【００９９】
次に、この液晶パネルの行と列各１本ずつの電極を選び、その交点に４０Ｖの電圧を２０ｍｓｅｃ間印加したところ、印加後に黒塗装していない基板側から見ると交点部分は緑色の反射色を呈した。次に、２０Ｖの電圧を２０ｍｓ印加したところ、印加後に黒塗装していない基板側から見ると交点部分がほぼ黒色を呈した。
【０１００】
液晶パネル１０の全画面を初期化するために、表示シーケンスの開始時に、パネル全体に４０Ｖの電圧を１３．２ｍｓ間印加した。それに続いて、液晶パネル１０に印加される電圧が０になる無印加時間を１ｍｓ設けた。その後、ＦＣ状態にするための電圧条件として２３Ｖの電圧を３．３ｍｓ間全画素に印加した。そして、線順次駆動を実施した。
【０１０１】
具体的な駆動手順について図９（Ａ）のタイミング図を用いて説明する。例えば、行ドライバ１２が全行電極にＶ_ｒを印加し、列ドライバ１３が全列電極にＶ_ｃを印加する状態にする。たとえば、Ｖ_ｒは３５Ｖ、Ｖ_ｃは−５Ｖである。すると、液晶パネル１０の全画素に４０Ｖの電圧が印加される。図９（Ａ）において、４０Ｖの電圧が印加される期間がリセット部として示されている。また、リセット部は第１の期間に相当する。
【０１０２】
その後、印加電圧が０Ｖになる無印加状態を１ｍｓ続けた後、２３Ｖの電圧が３．３ｍｓｅｃ間全画素に印加されるようにする。具体的には、行ドライバ１２および列ドライバ１３によってＶ_ｒ−Ｖ_ｃの電圧を印加する。図９（Ａ）において、それらの期間が無印加部およびフォーカルコニック部として示されている。無印加部は第２の期間に相当し、フォーカルコニック部は第３の期間に相当する。
【０１０３】
続いて、表示データの書き込みすなわち線順次駆動が始まる。線順次駆動では、選択行が順番に入れ替わり、それに同期して列電極に表示データに応じた列電圧が出力される。駆動電圧波形は適当な周期で極性反転され交流化される。線順次駆動期間において、選択時にはオン表示（ＰＬ状態）ではＶ_ｒ＋Ｖ_ｃの電圧が印加され、オフ表示（ＦＣ状態）ではＶ_ｒ−Ｖ_ｃの電圧振幅が印加される。
【０１０４】
この例では、Ｖ_ｒを３５Ｖ、Ｖ_ｃを５Ｖとした。また１回あたり行電極が選択される期間を３．３ｍｓとした。図９（Ａ）において、線順次駆動期間はアドレッシング部として示されている。フォーカルコニック部とアドレッシング部との間には無印加部を設けても設けなくてもよく、図９（Ａ）には、無印加部を設けた場合が例示されている。
【０１０５】
表示データを書き込む前の一連の電圧処理によって、ＣＬ−ＬＣＤ１００が若干の残留反射が残るＦＣ状態になったことが確かめられた。また、引き続き線順次駆動によって表示書き込みを行うことによって、以上の条件でテストパターンを表示したところ、残像もなく、高コントラスト比の表示が得られた。
【０１０６】
（例１−２）例１−１の駆動条件のうち、ＣＬ−ＬＣＤ１００の全体に４０Ｖの電圧を１３．２ｍｓ間印加し、それに続いて、印加電圧が０Ｖである無印加時間を１ｍｓ設けた。次の電圧処理期間すなわちフォーカルコニック部において印加電圧を２４Ｖとして２．０ｍｓ間印加し、線順次駆動を開始しテストパターンを表示するようにした。
【０１０７】
すると、線順次駆動が開始される前の配向状態が、ＦＣ状態とＰＬ状態の混在状態であるにも関わらず、線順次駆動による表示状態は、残像もなく、例１−１よりやや劣るがコントラストの高い表示状態であった。また、表示シーケンスに要する時間を例１−１に比べて短縮できた。
【０１０８】
以上のように、以前に書込まれた表示状態を完全に消去するには全画素を一旦垂直配向にする必要がある。そのために、例えば４０Ｖの電圧をＣＬ−ＬＣＤ１００の全画素に所定期間（図９（Ａ）におけるリセット部）印加する。ただし、実用上は、印加電圧を低減するために印加時間をより長く設定することもあり得る。
【０１０９】
本例の結果から、第３の段階であるフォーカルコニック部を短縮しても、コントラスト比が比較的高い表示状態が得られることがわかる。フォーカルコニック部を短縮すると、線順次駆動が開始される前の配向状態がＰＬ状態の選択反射が残留する不充分なＦＣ状態、すなわち、ＦＣ状態とＰＬ状態の混在状態になっている。しかし、線順次駆動時にオフ表示としてＦＣ状態が書き込まれるので、比較的高いコントラスト比が得られる。
【０１１０】
したがって、ＨＯ状態にするための電圧条件をＶ_１（リセット部の電圧値）およびτ_１（リセット部の期間）、ＦＣ状態に書き込むための電圧条件をＶ_３（フォーカルコニック部の電圧値）およびτ_３（フォーカルコニック部の期間）とすると、Ｖ_１＞Ｖ_３かつτ_１＞τ_３であってもよい。
【０１１１】
（比較例１−１）例１−１の駆動条件において、無印加部の時間を０〜０．３ｍｓの間で変化させたところ、線順次駆動の駆動条件をどのように変えても、例１−１と同様のコントラスト比の表示を得ることができなかった。
【０１１２】
（比較例１−２）τ_２がτ_Ｈの４０倍である２０ｍｓの場合、リセット時にちらつきが発生した。また、初期化（リセット）の所要時間が相対的に長くなる。この程度の所要時間は１表示シーケンスの構成に大きな影響を与えることになる。
【０１１３】
（例１−３）例１−１の駆動条件において、線順次駆動による表示データの書き込み時に、選択期間に対して列電極の印加時間を均等に１０分割し、分割された各期間に階調データに応じたオンとオフに相当する電圧を列電極に印加した。そして、そのような電圧印加方法によってテストパターンを表示したところ、表示データに応じた均一な階調表示が得られた。
【０１１４】
（比較例１−３）例１−１の駆動条件において、列電極の印加電圧をオンのときにＶ_ｃ、オフのときに−Ｖ_ｃとし、階調データに応じてｎ・Ｖ_ｃ（−１＜ｎ＜１）の電圧値を列電極に印加した。電圧値を変えることによって１０階調表示を行った。様々なテストパターンを表示させたところ、列電極に平行な表示むらが発生し不均一な階調表示になった。
【０１１５】
したがって、中間調表示を行う場合、パルス幅変調を使用すれば良好な階調表示を得ることができるが、振幅変調を使用した場合には良好な階調表示を得ることができないことがわかった。
【０１１６】
次に、ＣＬ−ＬＣＤを駆動する駆動回路について説明する。単純マトリックス型ＳＴＮ液晶表示素子の基本的な駆動方式である線順次選択法（例えば、ＡＰＴ：Alto Pleshko Techniqueやそれを改良したＩＡＰＴ：Improved APT）を実現する駆動ドライバが専用ＩＣとして広く用いられている。
【０１１７】
単純マトリックス型ＳＴＮ液晶表示素子を駆動するためのＩＡＰＴ駆動ドライバは、一つの行電極ずつにしか選択電圧を印加できない。したがって、それを用いてＣＬ−ＬＣＤの全面の初期状態をＦＣ状態に揃えるには、ＨＯ状態への遷移に少なくとも１フレーム期間がかかる。さらに、ＦＣ状態への遷移に少なくとも１フレーム期間がかかる。ただし、ＨＯ状態への遷移を１フレーム期間で行うには、アドレッシング時の１選択時間で行わなければならないので、オン電圧よりも高い電圧を印加する必要が生ずる。
【０１１８】
それを実現するには高耐圧のドライバが必要となり、困難である。逆に、オン電圧と等しい印加電圧で十分な垂直配向を得ようとすると、１選択時間を長くしなければならず、初期化に要する時間が書き込み時間よりも長くなる。
【０１１９】
すなわち、ＩＡＰＴ駆動ドライバをＣＬ−ＬＣＤにそのまま適用しようとすると、上述した電圧印加処理（第１の段階〜第３の段階）を実現できず、初期化に要する時間が１画面を選択する時間の数倍程度になってしまう。すなわち、初期化を含めた１画面の書き換えに必要な時間が長くなってしまう。そこで、利用しやすいＩＡＰＴ駆動ドライバを用いた本発明の駆動装置を提案する。
【０１２０】
図１０および図１１は、ＩＡＰＴ駆動ドライバの機能を説明するための説明図である。図１０に示すように、列ドライバ（ＣＯＬ−ＤＲＶ）と行ドライバ（ＲＯＷ−ＤＲＶ）はそれぞれ４レベルの液晶駆動電圧を必要とするが、システム全体では６レベルの電圧が必要になる。ここで、Ｖ_ｒは選択時に行電極に印加される電圧であり、Ｖ_ｃは行電極に印加されるオン電圧とオフ電圧の差の１／２である。
【０１２１】
図１１に示すように、出力電圧はレベル信号である極性反転信号（Ｍ信号）と非表示指示信号（／ＤＯＦＦ信号）に応じて、行ドライバおよび列ドライバでそれぞれ決定される。ただし、／ＤＯＦＦ信号がローレベルである場合には行ドライバおよび列ドライバの全出力は、他の入力信号に関わらずＶ_０レベルを出力する。
【０１２２】
図１２は、駆動装置の実施の形態１−Ａを示すブロック図である。この場合、図８に示す一般的な駆動回路に対して、信号変換回路１４がさらに設けられている。信号変換回路１４は、コントローラ１１と行ドライバ１２および列ドライバ１３との間に設置され、コントローラ１１からの各信号にもとづいて、上述した第１段階（リセット部）、第２の段階（無印加部）および第３の段階（フォーカルコニック部）を作成するための信号を作成し、行ドライバ１２および列ドライバ１３に供給する。
【０１２３】
なお、ここでは、信号変換回路１４は信号制御回路１１と独立したものとして説明を進めるが、それらは一体化されていてもよい。一体化されている場合には、信号のタイミングを最適化できるので、初期化に要する時間を短くすることができる。
【０１２４】
また、Ｍ信号は信号変換回路１４が作成した極性反転信号であり、ＤＡＴＡは信号変換回路１４が作成した表示データである。ＤＡＴＡは、アドレッシング部では信号制御回路１１が出力する表示データと同じになる。／ＤＯＦＦ１信号は信号変換回路１４が作成し、列ドライバ１３に供給される／ＤＯＦＦ信号であり、／ＤＯＦＦ２信号は信号変換回路１４が作成し行ドライバ１２に供給される／ＤＯＦＦ信号である。
【０１２５】
メモリ性のＣＬ−ＬＣＤは一度データが書き込まれると、その表示状態を保持するのでフレーム周期毎に書き込みを行う必要はないが、データの書き換えを必要とするタイミングを外部から指示する必要がある。そのための信号が図１２に示すスタート信号（ＳＴＡＲＴ）である。ＳＴＡＲＴ信号はタイマによって生成した、ある一定期間毎に有効になる信号でもよいし、表示データの発生源であるＭＰＵや外部スイッチからの表示書き換え指示信号であってもよい。図１２には、ＭＰＵから出力される例が示されている。
【０１２６】
図１３は、実施の形態１−Ａにおける信号変換回路１４の構成例を示すブロック図である。図１３に示す信号変換回路１４において、０．５ライン検出回路２１は、ＬＰ信号をトリガとして選択期間の１／２のタイミングを決定し、そのタイミングでレベルが反転するような信号を論理和回路２２に出力する。ダウンカウンタ２４は、ＦＲ信号が入力されたら、（Ｎ−１）をプリセットし、ＬＰ信号の入力に応じてカウント値を１減ずるカウンタである。ここで、Ｎは表示行数である。第１〜第５の比較器（以下、比較器という。）２５，２６，２７，２８，２９は、それぞれ、ダウンカウンタ２４のカウント値を所定値と比較する。
【０１２７】
論理和回路２２は、ＤＯＦＦ制御回路３１からのマスク信号がローレベル状態であれば、０．５ライン検出回路２１の出力信号をＭ信号として行ドライバ１２および列ドライバ１３に出力し、マスク信号がハイレベル状態であれば、ハイレベルのＭ信号を行ドライバ１２および列ドライバ１３に出力する。
【０１２８】
また、セレクタ２３は、選択信号の状態に応じて、ＤＡＴＡ信号として、信号制御回路１１からの表示データ、ハイレベルのデータまたはローレベルのデータのいずれかを列ドライバ１３に出力する。
【０１２９】
スタートフラグ回路３０は、ＳＴＡＲＴ信号をＦＲ信号で同期化し、スタートフラグをセットする。スタートフラグがセットされたことはＤＯＦＦ制御回路３１に通知される。また、スタートフラグは、ＤＯＦＦ制御回路３１の指示に応じてリセットされる。ＤＯＦＦ制御回路３１は、スタートフラグがセットされている状態において機能する。そして、比較器２５，２６，２７，２８，２９の出力の状況に応じて、列ドライバ１３に／ＤＯＦＦ１信号を与えるとともに、行ドライバ１２に／ＤＯＦＦ２信号を与える。また、論理和回路２２に対してマスク信号を与え、セレクタ２３に対して選択信号を与える。
【０１３０】
次に、図１４のタイミングチャートを参照して動作を説明する。比較器２５，２６，２７，２９は、リセット部（第１の段階）の時間長をＡ、無印加部（第２の段階）の時間長をＢ、フォーカルコニック部（第３の段階）の時間長をＣに設定するために設けられている。各比較器２５〜２９は、ＬＰ信号をダウンカウントするダウンカウンタ２４のカウント値を導入して、カウント値と所定値とを比較し、それらが一致したら一致信号を出力する。
【０１３１】
なお、この実施の形態では、リセット部の時間長Ａを設定するための第１の期間設定手段は、ダウンカウンタ２４および比較器２５，２６で実現される。無印加部の時間長Ｂを設定するための第２の期間設定手段は、ダウンカウンタ２４および比較器２６，２７で実現される。フォーカルコニック部の時間長Ｃを設定するための第３の期間設定手段は、ダウンカウンタ２４および比較器２７，２９で実現される。第１〜第３の段階において所定電圧を印加する電圧印加手段は、論理和回路２２、セレクタ２３およびＤＯＦＦ制御回路３１で実現される。
【０１３２】
比較器２５の比較のための所定値は（Ａ＋Ｂ＋Ｃ）であり、比較器２６の比較のための所定値は（Ａ＋Ｂ）である。また、比較器２７の比較のための所定値はＢであり、比較器２８の比較のための所定値は１である。そして、比較器２９の比較のための所定値は０である。なお、Ａ＋Ｂ＋Ｃ＜Ｎ（Ｎは表示行数）である。
【０１３３】
スタートフラグがセットされていない状態では、ＤＯＦＦ制御回路３１は、全ての列電極および行電極が電位Ｖ_０である無印加状態になるように、列ドライバ１３および行ドライバ１２に対する非表示指示信号（／ＤＯＦＦ１信号および／ＤＯＦＦ２信号）をローレベルに固定する。
【０１３４】
よって、ＣＬ−ＬＣＤ１００は、信号制御回路１１からの信号状態に関わらず、電圧無印加状態となる。また、Ｍ信号およびＤＡＴＡ信号をハイレベルを固定するために、論理和回路２２へのマスク信号をハイレベルに固定し、セレクタ２３への選択信号をハイレベル（”１”）が選択されるように設定する。ＳＴＡＲＴ信号が入力された後、ＦＲ信号が入力されると、スタートフラグ回路３０において、スタートフラグがセットされる。ＦＲ信号はフレーム周期毎に入力される。
【０１３５】
ＦＲ信号が入力されるとダウンカウンタ２４に（Ｎ−１）がプリセットされる。以後、ダウンカウンタ２４は、行切替信号（ＬＰ信号）をトリガにしてダウンカウントする。比較器２５は、ダウンカウンタ２４のカウント値が（Ａ＋Ｂ＋Ｃ）に一致するとＤＯＦＦ制御回路３１に一致信号を出力する。ＤＯＦＦ制御回路３１は、／ＤＯＦＦ１信号および／ＤＯＦＦ２信号がともにローレベルである状態のときに比較器２５からの一致信号を受け、さらに、ＬＰ信号が入力されると、列ドライバ１３への／ＤＯＦＦ１信号をハイレベルに固定する。
【０１３６】
この結果、図１１に示す関係にもとづいて、全ての列電極の電圧レベルがＶ_５（Ｖ_ｒ＋Ｖ_ｃ）となる。また、全ての行電極の電圧レベルはＶ_０であるから、全ての画素に対する液晶印加電圧はＶ_ｒ＋Ｖ_ｃとなる。例えば、Ｖ_ｒ＝３５Ｖ，Ｖ_ｃ＝５Ｖであれば、液晶印加電圧は４０Ｖである。
【０１３７】
比較器２６は、ダウンカウンタ２４のカウント値が（Ｂ＋Ｃ）に一致するとＤＯＦＦ制御回路３１に一致信号を出力する。ＤＯＦＦ制御回路３１は、／ＤＯＦＦ１信号がハイレベルで、かつ、／ＤＯＦＦ２信号がローレベルである状態のときに比較器２６からの一致信号を受ける。さらに、ＬＰ信号が入力されると、列ドライバ１３への／ＤＯＦＦ１信号をローレベルに固定する。この結果、図１１に示す関係にもとづいて、ＣＬ−ＬＣＤ１００は電圧無印加状態になる。
【０１３８】
また、このとき、ＤＯＦＦ制御回路３１は、セレクタ２３への選択信号をローレベル（”０”）が選択されるように設定する。
【０１３９】
液晶印加電圧がＶ_ｒ＋Ｖ_ｃに変化した時点から電圧無印加状態になるまでの期間は、ダウンカウンタ２４のカウント値が「Ａ」進む間の期間であり、図１４に示すように、この期間がリセット部となる。
【０１４０】
比較器２７は、ダウンカウンタ２４のカウント値がＣに一致するとＤＯＦＦ制御回路３１に一致信号を出力する。ＤＯＦＦ制御回路３１は、／ＤＯＦＦ１信号および／ＤＯＦＦ２信号がともにローレベルである状態のときに比較器２７からの一致信号を受ける。
【０１４１】
さらに、ＬＰ信号が入力されると、列ドライバ１３への／ＤＯＦＦ１信号をハイレベルに固定する。この結果、図１１に示す関係にもとづいて、全ての列電極の電圧レベルはＶ_３（Ｖ_ｒ−Ｖ_ｃ）となる。また、全ての行電極の電圧レベルはＶ_０であるから、全ての画素に対する液晶印加電圧はＶ_ｒ−Ｖ_ｃとなる。例えば、Ｖ_ｒ＝３５Ｖ，Ｖ_ｃ＝５Ｖであれば、液晶印加電圧は３０Ｖである。
【０１４２】
液晶印加電圧が電圧無印加状態に変化した時点からＶ_ｒ−Ｖ_ｃになるまでの期間は、ダウンカウンタ２４のカウント値が「Ｂ」進む間の期間であり、図１４に示すように、この期間が無印加部となる。
【０１４３】
比較器２８は、ダウンカウンタ２４のカウント値が１に一致するとＤＯＦＦ制御回路３１に一致信号を出力する。ＤＯＦＦ制御回路３１は、／ＤＯＦＦ１信号がハイレベルで、かつ、／ＤＯＦＦ２信号がローレベルである状態のときに比較器２８からの一致信号を受ける。さらに、ＬＰ信号が入力されると、セレクタ２３への選択信号を、ＤＡＴＡ信号として表示データを選択させるように変化させる。
【０１４４】
比較器２９は、ダウンカウンタ２４のカウント値が０に一致するとＤＯＦＦ制御回路３１に一致信号を出力する。ＤＯＦＦ制御回路３１は、／ＤＯＦＦ１信号がハイレベルで、かつ、／ＤＯＦＦ２信号がローレベルである状態のときに比較器２９からの一致信号を受け、さらに、ＬＰ信号が入力されると、列ドライバ１３および行ドライバ１２への／ＤＯＦＦ１信号および／ＤＯＦＦ２信号をハイレベルに固定する。
【０１４５】
また、論理和回路２２へのマスク信号をローレベルに固定し、０．５ライン検出回路２１の出力がＭ信号となるようにする。従って、線順次駆動によってＤＡＴＡ信号とＭ信号に応じた表示がなされるアドレッシング部が開始される。このとき、オン電圧はＶ_ｒ＋Ｖ_ｃ、オフ電圧はＶ_ｒ−Ｖ_ｃとなる。
【０１４６】
液晶印加電圧がＶ_ｒ−Ｖ_ｃに変化した時点からオン／オフに応じた電圧になるまでの期間は、ダウンカウンタ２４のカウント値が「Ｃ」進む間の期間であり、図１４に示すように、この期間がフォーカルコニック部となる。
【０１４７】
さらに、列ドライバ１３と行ドライバ１２への非表示指示信号である／ＤＯＦＦ１信号と／ＤＯＦＦ２信号とがともにハイレベルである状態で、比較器２９から一致信号が出力されると、ＤＯＦＦ制御回路３１は、スタートフラグをリセットするとともに、／ＤＯＦＦ１信号と／ＤＯＦＦ２信号とをともにローレベルに固定して全画素に対する液晶印加電圧を０Ｖにする。
【０１４８】
よって、ＣＬ−ＬＣＤは書き込み状態を記憶したままの状態になる。また、論理和回路２２へのマスク信号をハイレベルに固定するとともに、セレクタ２３の出力がハイレベルに固定されるように選択信号を切り替える。そして、次にＳＴＡＲＴ信号が入力されるまでその状態を保持する。
【０１４９】
このように、実施の形態１−Ａでは、従来の駆動装置が取り扱うことができるＭ信号と／ＤＯＦＦ信号とを利用することによって、第１の段階〜第３の段階、すなわち、リセット部、無印加部（または待機部）およびフォーカルコニック部を作成する。したがって、ＩＡＰＴ駆動ドライバを本発明に適用できる。
【０１５０】
次に、実施の形態１−Ｂの構成を図１５に示す。実施の形態１−Ｂでは信号変換回路１４は、電圧切替指示信号であるＳＥＬ信号も出力する。また、電源装置１５およびスイッチ回路１６が設けられている。電源装置１５は、液晶表示パネルを駆動するための通常の電圧であるＶＬＣＤ１の他に、任意の電圧レベルであるＶＬＣＤ２を供給可能である。この実施の形態１−Ｂでは、電源装置１５およびスイッチ回路１６も、第１〜第３の段階において所定電圧を印加する電圧印加手段の一部である。
【０１５１】
なお、ＶＬＣＤ１は通常の書き込み時におけるオン電圧Ｖ_５（Ｖ_ｒ＋Ｖ_ｃ）に相当する電圧である。ＶＬＣＤ２も同様にＶ_５（Ｖ_ｒ＋Ｖ_ｃ）に相当する電圧であるが、ＶＬＣＤ１と異なる値である。たとえば、ＶＬＣＤ１が４０Ｖである場合にＶＬＣＤ２が２４Ｖとなるような電圧値である。スイッチ回路１６は、信号変換回路１４からのＳＥＬ信号に応じて、ＶＬＣＤ１とＶＬＣＤ２のうちのいずれかを行ドライバ１２および列ドライバ１３に必要な電圧レベルを分圧することによって供給する。
【０１５２】
図１６は実施の形態１−Ｂにおける信号変換回路１４の構成例を示すブロック図である。図１６に示す信号変換回路１４において、０．５ライン検出回路２１、論理和回路２２、ダウンカウンタ２４、比較器２５〜２９およびスタートフラグ回路３０は、実施の形態１−Ａのものと同様に動作する。ＤＯＦＦ制御回路３１において電源電圧の切替を指示するＳＥＬ信号の制御が追加される。また、実施の形態１−Ａで用いたセレクタ２３を変更し、論理和回路２３Ａが設けられている。
【０１５３】
次に、図１７のタイミング図を参照して動作について説明する。スタートフラグがセットされていない状態では、ＤＯＦＦ制御回路３１は、全ての列電極および行電極が電位Ｖ_０である無印加状態になるように、列ドライバ１３および行ドライバ１２に対する非表示指示信号（／ＤＯＦＦ１信号および／ＤＯＦＦ２信号）をローレベルに固定する。
【０１５４】
よって、ＣＬ−ＬＣＤ１０は、信号制御回路１１からの信号状態に関わらず電圧無印加状態となる。また、Ｍ信号およびＤＡＴＡ信号をハイレベルを固定するために、論理和回路２２へのマスク信号および論理和回路２３Ａへのマスク信号をハイレベルに固定する。ＳＴＡＲＴ信号が入力された後、ＦＲ信号が入力されると、スタートフラグ回路３０において、スタートフラグがセットされる。ＦＲ信号はフレーム周期毎に入力される。
【０１５５】
ＦＲ信号が入力されるとダウンカウンタ２４に（Ｎ−１）がプリセットされる。以後、ダウンカウンタ２４は、行切替信号（ＬＰ信号）をダウンカウントする。比較器２５は、ダウンカウンタ２４のカウント値が（Ａ＋Ｂ＋Ｃ）に一致するとＤＯＦＦ制御回路３１に一致信号を出力する。
【０１５６】
ＤＯＦＦ制御回路３１は、／ＤＯＦＦ１信号および／ＤＯＦＦ２信号がともにローレベルである状態のときに比較器２５からの一致信号を受け、さらに、ＬＰ信号が入力されると、列ドライバ１３への／ＤＯＦＦ１信号をハイレベルに固定する。
【０１５７】
この結果、図１１に示す関係にもとづいて、全ての列電極の電圧レベルがＶ_５（Ｖ_ｒ＋Ｖ_ｃ）となる。また、全ての行電極の電圧レベルはＶ_０であるから、全ての画素に対する液晶印加電圧はＶ_ｒ＋Ｖ_ｃとなる。例えば、Ｖ_ｒ＝３５Ｖ，Ｖ_ｃ＝５Ｖであれば、液晶印加電圧は４０Ｖである。
【０１５８】
比較器２６は、ダウンカウンタ２４のカウント値が（Ｂ＋Ｃ）に一致するとＤＯＦＦ制御回路３１に一致信号を出力する。ＤＯＦＦ制御回路３１は、／ＤＯＦＦ１信号がハイレベルで、かつ、／ＤＯＦＦ２信号がローレベルである状態のときに比較器２６からの一致信号を受ける。
【０１５９】
さらに、ＬＰ信号が入力されると、列ドライバ１３への／ＤＯＦＦ１信号をローレベルに固定する。この結果、図１１に示す関係にもとづいて、ＣＬ−ＬＣＤ１０は電圧無印加状態になる。
【０１６０】
液晶印加電圧がＶ_ｒ＋Ｖ_ｃに変化してから電圧無印加状態になるまでの期間は、ダウンカウンタ２４のカウント値が「Ａ」進む間の期間であり、図１７に示すように、この期間がリセット部となる。
【０１６１】
比較器２７は、ダウンカウンタ２４のカウント値がＣに一致するとＤＯＦＦ制御回路３１に一致信号を出力する。ＤＯＦＦ制御回路３１は、／ＤＯＦＦ１信号および／ＤＯＦＦ２信号がともにローレベルである状態のときに比較器２７からの一致信号を受け、さらに、ＬＰ信号が入力されると、列ドライバ１３への／ＤＯＦＦ１信号をハイレベルに固定する。
【０１６２】
また、ＳＥＬ信号をハイレベルに固定する。図１５に示すスイッチ回路１６は、ＳＥＬ信号がハイレベルになったことに応じて、電源装置１５からのＶＬＣＤ２を選択して行ドライバ１２および列ドライバ１３に供給する状態になる。
【０１６３】
この結果、図１１に示す関係にもとづいて、全ての列電極の電圧レベルはＶ_５（Ｖ_ｒ＋Ｖ_ｃ）となる。また、全ての行電極の電圧レベルはＶ_０であるから、全ての画素に対する液晶印加電圧はＶ_ｒ＋Ｖ_ｃとなる。しかし、この段階では、ＳＥＬ信号がハイレベルであるから液晶印加電圧はＶＬＣＤ２であり、リセット部および線順次駆動で用いられる通常のＶ_ｒ＋Ｖ_ｃ（＝ＶＬＣＤ１）とは異なる。例えば、Ｖ_ｒ＋Ｖ_ｃ＝２４Ｖである。
【０１６４】
液晶印加電圧が電圧無印加状態に変化した時点からＶＬＣＤ２が供給開始されるまでの期間は、ダウンカウンタ２４のカウント値が「Ｂ」進む間の期間であり、図１７に示すように、この期間が無印加部となる。
【０１６５】
比較器２８は、ダウンカウンタ２４のカウント値が１に一致するとＤＯＦＦ制御回路３１に一致信号を出力する。ＤＯＦＦ制御回路３１は、／ＤＯＦＦ１信号がハイレベルで、かつ、／ＤＯＦＦ２信号がローレベルである状態のときに比較器２８からの一致信号を受け、さらに、ＬＰ信号が入力されると、論理和回路２３Ａへのマスク信号をローレベルに固定して、ＤＡＴＡ信号として表示データを出力させる。
【０１６６】
比較器２９は、ダウンカウンタ２４のカウント値が０に一致するとＤＯＦＦ制御回路３１に一致信号を出力する。ＤＯＦＦ制御回路３１は、／ＤＯＦＦ１信号がハイレベルで、かつ、／ＤＯＦＦ２信号がローレベルである状態のときに比較器２９からの一致信号を受ける。
【０１６７】
さらに、ＬＰ信号が入力されると、列ドライバ１３および行ドライバ１２への／ＤＯＦＦ１信号および／ＤＯＦＦ２信号をハイレベルに固定する。そして、ＳＥＬ信号をローレベルに戻す。この結果、行ドライバ１２および列ドライバ１３には、電源装置１５からＶＬＣＤ１が供給される状態に戻る。また、論理和回路２２へのマスク信号をローレベルに固定し、０．５ライン検出回路２１の出力がＭ信号となるようにする。したがって、線順次駆動によってＤＡＴＡ信号とＭ信号に応じた表示がなされるアドレッシング部が開始される。このとき、オン電圧はＶ_ｒ＋Ｖ_ｃ、オフ電圧はＶ_ｒ−Ｖ_ｃとなる。
【０１６８】
液晶印加電圧がＶＬＣＤ２にもとづく電圧に変化した時点から通常のオン／オフに応じた電圧になるまでの期間は、ダウンカウンタ２４のカウント値が「Ｃ」進む間の期間であり、図１７に示すように、この期間がフォーカルコニック部となる。
【０１６９】
さらに、列ドライバ１３と行ドライバ１２への非表示指示信号である／ＤＯＦＦ１信号と／ＤＯＦＦ２信号とがともにハイレベルである状態で、比較器２９から一致信号が出力されると、ＤＯＦＦ制御回路３１は、スタートフラグをリセットするとともに、／ＤＯＦＦ１信号と／ＤＯＦＦ２信号とをともにローレベルに固定して全画素に対する液晶印加電圧を０Ｖにする。よって、ＣＬ−ＬＣＤは書き込み状態を記憶したままの状態になる。
【０１７０】
また、論理和回路２２へのマスク信号と論理和回路２３Ａへのマスク信号とをハイレベルに固定し、Ｍ信号およびＤＡＴＡ信号をハイレベルに固定する。そして、次にＳＴＡＲＴ信号が入力されるまでその状態を保持する。
【０１７１】
以上、説明したように、実施の形態１−Ｂでも、従来の駆動装置が取り扱うことができるＭ信号と／ＤＯＦＦ信号とを利用することによって、リセット部、無印加部およびフォーカルコニック部を作成できる。したがって、ＩＡＰＴ駆動ドライバを本発明に適用できる。
【０１７２】
しかも、実施の形態１−Ｂでは、フォーカルコニック部における電圧の振幅を任意に設定できるので、フォーカルコニック部に求められる最適の電圧値を使用できる。なお、リセット部における電圧の振幅も任意の値に設定できるように構成してもよい。
【０１７３】
なお、上記の各実施の形態では、ＬＰ信号を用いて第１〜第３の段階の長さを設定したが、ＬＰ信号以外のクロック信号にもとづいて第１〜第３の段階の長さを設定してもよい。その場合、より高周波のクロック信号を用いると、初期化の所要時間をより短縮できる。
【０１７４】
また、上記の各実施の形態では、第１の段階（リセット部）および第３の段階（フォーカルコニック部）において、ＣＬ−ＬＣに対して正のパルス電圧を印加したが、それぞれの段階において、電圧振幅の絶対値が等しい正のパルスと負のパルスとを印加するようにしてもよい。
【０１７５】
（実施の形態２）次に、パルス幅変調方式を用いた実施の形態２−Ａについて説明する。図１９は、その実験結果を示す説明図である。印加時間１ｍｓでは、約５回の電圧印加で、ＣＬ−ＬＣをほぼ完全なＦＣ状態にすることができる。ところが、１回のみの電圧印加で同様な状態を実現するには、１０ｍｓの印加時間が必要になる。以上のように、１回の電圧印加でＦＣ状態を実現するよりも、短い印加時間で電圧を何度も印加する方がＦＣ状態を実現するための合計の時間を小さくすることができることがわかる。
【０１７６】
すなわち、表示データを書き込むための準備期間では、ＣＬ−ＬＣに対して一旦、ＨＯ状態にする電圧を印加してそれ以前の表示状態をリセットした後、電圧を印加しない状態すなわち電位差０Ｖの期間を設ける。さらに、ＣＬ−ＬＣをＦＣ状態とＰＬ状態の混在状態にするような電圧パルスを短い印加時間で断続的に印加する。この方法によって、ＣＬ−ＬＣを選択反射の残留がほとんどないＦＣ状態またはＦＣ状態とＰＬ状態の混在状態とし、その状態で表示データに対応する電圧書き込みを行うのがよい。
【０１７７】
このような駆動法によれば、一連の画像を更新するシーケンスに要する時間をさらに短縮できる。また、電位差０Ｖの期間で、ＣＬ−ＬＣはＨＧ状態またはＨＧ状態とＰＬ状態の混在状態に移行するので、効率的にリセット時間の短縮を図ることができる。
【０１７８】
さらには、初期状態がＦＣ状態またはＦＣ状態とＰＬ状態の混在状態に設定されることから、ＰＬ状態で全画素が一時反射表示状態となるためにリセット時にちらつきが発生するということもない。
【０１７９】
また、図５〜図７に示すように、印加時間を短くするとＦＣ状態が書き込まれる最適電圧は上昇していく。従って、垂直配向にするための印加電圧をＶ_１、印加時間τ_１とし、ＦＣ状態またはＦＣ状態とＰＬ状態との混在状態を書き込むための１回あたりの印加電圧をＶ_３、印加時間をτ_３としたときに、Ｖ_３およびτ_３を適切に選択すれば、τ_１＞τ_３という条件下で、Ｖ_１とＶ_３を共通化することができる。よって、駆動ドライバの回路構成を簡略化できる。
【０１８０】
図２０は実施の形態２−Ａのコントローラ１１の構成例を示すブロック図である。発振器３３は所定周波数のクロック信号（ＣＬＫ）を発生する。基準カウンタ３４は、ＣＬＫを入力してカウントする。ラインカウンタ３５は、基準カウンタ３４のカウント値が所定値になると、その値を＋１する。比較器３６は、基準カウンタ３４のカウント値（ＤＯＴ）、ラインカウンタ３５のカウント値（ＬＩＮＥ）および設定レジスタ３７の設定値（Ｎ_１〜Ｎ_５）を入力し、ＣＰ信号、Ｍ信号、ＬＰ信号、／ＤＯＦＦ１信号、／ＤＯＦＦ２信号およびＳＥＬ信号を作成する。ＳＥＬ信号はセレクタ３９に出力される。
【０１８１】
メモリ３８には、ＭＰＵ２０からの表示データが格納されている。セレクタ３９は、ＳＥＬ信号に応じて、メモリ３８内のデータ、”１”固定信号および”０”固定信号のうちのいずれかを選択し、選択したデータをＤＡＴＡ信号としてＣＬ−ＬＣＤに出力する。
【０１８２】
設定レジスタ３７には、ＭＰＵ２０から電圧印加時間の設定のための設定値が書き込まれる。各時間は、発振器３３から出力されるクロック数で換算された値である。ここでは、垂直配向のための高電圧印加時間（第１の段階の期間）をＮ_１、無印加部の時間（第２の段階の期間）をＮ_２、ＦＣ状態への転移のための電圧印加時間（第３の段階の期間）をＮ_３、Ｎ_２とＮ_３との繰り返し回数をＮ_４、線順次駆動における１選択時間をＮ_５とする。
【０１８３】
ＣＬ−ＬＣＤは一度データが書き込まれると、その表示状態を保持するのでフレーム周期毎に書き込みを行う必要はないが、データの書き換えを必要とするタイミングを外部から通知する必要がある。そのために、ＭＰＵから設定レジスタ３７に表示書き換えの指示がなされる。設定レジスタ３７に表示書き換え指示が設定されると、比較器３６にＳＴＡＲＴ信号が出力される。
【０１８４】
なお、この実施の形態２−Ａでは、垂直配向のための高電圧印加期間を設定するための第１の期間設定手段、無印加部の時間を設定するための第２の期間設定手段およびＦＣ状態への遷移のための電圧印加時間を設定するための第３の期間設定手段は、ともに、基準カウンタ３４、ラインカウンタ３５、設定レジスタ３７および比較器３６で実現される。第１〜第３の段階において所定電圧を印加する電圧印加手段は、メモリ３８、セレクタ３９および比較器３６で実現される。また、第２の段階と第３の段階とを繰り返す回数制御手段は、設定レジスタ３７および比較器３６で実現される。
【０１８５】
次に、図２１のタイミング図を参照して動作の説明をする。ここでは、Ｎ_４＝２とし、線順次駆動におけるオン電圧をＶ_ｒ＋Ｖ_ｃ、オフ電圧をＶ_ｒ−Ｖ_ｃとする。
【０１８６】
コントローラ１１は、ＭＰＵ２０から表示開始が指示されるまで初期状態とする。すなわち、ＣＰ信号をローレベルに、ＬＰ信号をローレベルに、Ｍ信号をハイレベルに、ＤＡＴＡをハイレベルに、／ＤＯＦＦ１信号および／ＤＯＦＦ２信号をローレベルに維持する。／ＤＯＦＦ１信号と／ＤＯＦＦ２信号とがともにローレベルであるので、すべての行電極および列電極が電位Ｖ_０である液晶無印加状態となる。また、基準カウンタ３４およびラインカウンタ３５はともに０を保持する。
【０１８７】
ＭＰＵ２０から表示開始が指示されると、設定レジスタ３７においてＳＴＡＲＴフラグがセットされ、ＳＴＡＲＴ信号がハイレベルになる。ＳＴＡＲＴ信号がハイレベルになと、比較器３６は、基準カウンタ３４を動作状態にする。基準カウンタ３４は、発振器３３からのクロック（ＣＬＫ）に応じてカウント値を１ずつ増やす。ラインカウンタ３５の値が０の場合には、基準カウンタ３４は、その値がＮ_５と一致するまでカウントアップする。
【０１８８】
比較器３６は、基準カウンタ３４のカウント値が偶数の場合にＣＰ信号をハイレベルにし、奇数の場合にはローレベルにして、表示素子のドット数に適合したパルス数分だけＣＰ信号を出力する。この間、ＤＡＴＡはハイレベルであるから、列ドライバ１３の内部レジスタの値は、全てハイレベルになる。
【０１８９】
基準カウンタ３４のカウント値がＮ_５と一致すると、比較器３６は、ＣＮＴ信号を１クロック期間ハイレベルにする。このＣＮＴ信号に応じて、基準カウンタ３４は値を０に戻し、ラインカウンタ３５は値を＋１する。また、このとき、ＬＰ信号を１クロック期間ハイレベルにする。よって、列ドライバ１３の内部レジスタの値が列ドライバ１３の出力に反映される。
【０１９０】
ラインカウンタ３５の値が１になると、比較器３６は、／ＤＯＦＦ２信号をハイレベルにする。図１１に示す関係から、全ての列電極の電圧レベルがＶ_５（Ｖ_ｒ＋Ｖ_ｃ）となる。また、全ての行電極の電圧レベルはＶ_０であるから、全ての画素に対する液晶印加電圧はＶ_ｒ＋Ｖ_ｃとなる。すなわち、液晶の垂直配向に必要な電圧が表示面の全面に印加される。
【０１９１】
また、比較器３６は、ＤＡＴＡをローレベルに固定するようなＳＥＬ信号を出力する。セレクタ３９は、そのようなＳＥＬ信号に応じて”０”を選択する。そして、比較器３６は、ＣＰ信号を順次出力して、列ドライバ１３の内部レジスタの値を全てローレベルにする。基準カウンタ３４は、カウント値がＮ_１と一致するまでカウントアップし、カウント値がＮ_１と一致するとカウント値を０に戻す。このとき、ラインカウンタ３５の値が＋１されて２になる。
【０１９２】
ラインカウンタ３５の値が２ｎ（１≦ｎ≦Ｎ_４）になると、比較器３６は、／ＤＯＦＦ２信号をローレベルにして、列ドライバ１３の出力電位をすべてＶ_０にする。よって、液晶印加電圧は０Ｖとなる。基準カウンタ３４は、カウント値がＮ_２と一致するまでカウントアップする。そして、カウント値がＮ_２と一致すると、基準カウンタ３４のカウント値を０に戻し、ラインカウンタ３５の値を＋１する。ラインカウンタ３５の値が２から３に変化する場合に、比較器３６は、ＬＰ信号を１クロック期間ハイレベルにする。その結果、列ドライバ１３の内部レジスタの値が列ドライバ１３の出力に反映される。
【０１９３】
ラインカウンタ３５の値が２ｎ＋１（１≦ｎ≦Ｎ_４）のときには、比較器３６は、／ＤＯＦＦ２信号をハイレベルにする。このとき、Ｍ信号はハイレベルであり、列ドライバ１３にラッチされているＤＡＴＡはローレベルであるから、図１１に示す関係にもとづいて全ての列電極に対する印加電圧はＶ_３となり、全ての画素に対する液晶印加電圧はＶ_３（Ｖ_ｒ−Ｖ_ｃ）となる。よって、ＦＣ状態を形成するのに必要な電圧が全面に印加される。基準カウンタ３４は、カウント値がＮ_３と一致するまでカウントアップし、カウント値がＮ_３と一致すると基準カウンタ３４のカウント値が０に戻り、ラインカウンタ３５の値が＋１される。
【０１９４】
ラインカウンタ３５の値が２ｎ＋１の場合に、その値が（２・Ｎ_４＋１）であるときには、比較器３６は、ＤＡＴＡとしてメモリ３８からの表示データを選択ようなＳＥＬ信号を出力する。セレクタ３９は、そのようなＳＥＬ信号に応じてメモリ３８からの表示データを選択する状態になる。そして、比較器３６は、ＣＰ信号を順次出力して、列ドライバ１３の内部レジスタに表示データを入れる。
【０１９５】
基準カウンタ３４は、カウント値がＮ_３と一致するまでカウントアップし、カウント値がＮ_３と一致すると基準カウンタ３４のカウント値が０に戻り、ラインカウンタ３５の値が＋１される。この例では、この段階のラインカウンタ３５の値は６である。比較器３６は、ＬＰ信号を１クロック期間ハイレベルにして、列ドライバ１３の内部レジスタの値を列ドライバ１３の出力に反映させる。また、ＬＰ信号のパルスを包含するようにＦＲ信号を一定期間ハイレベルにし、行ドライバ１２に先頭行からの走査を指示する。
【０１９６】
ラインカウンタの値が（２・Ｎ_４＋１）を越えている場合には、比較器３６は、／ＤＯＦＦ１信号および／ＤＯＦＦ２信号をハイレベルに固定する。よって、列ドライバ１２および行ドライバ１３の出力として線順次駆動に必要な電圧が出力される。図１０では、この期間がアドレッシング部として示されている。
【０１９７】
比較器３６は、アドレッシング部において、基準カウンタ３４のカウント値が（Ｎ_５／２）より小さい場合はＭ信号をローレベルにし、（Ｎ_５／２）以上であればハイレベルにして、線順次駆動時の液晶印加電圧を交流化させる。また、次の選択行のためにＤＡＴＡとしてメモリ３８の表示データを出力する。ＤＡＴＡは、ＣＰ信号によって列ドライバ１３の内部レジスタに取り込まれる。
【０１９８】
基準カウンタ３４はカウント値がＮ_５と一致するまでカウントアップし、Ｎ_５と一致すると基準カウンタ３４のカウント値が０に戻され、ラインカウンタ３５の値が＋１される。比較器３６は、ラインカウンタ３５の値が＋１される毎に、ＬＰ信号をパルス出力して、行ドライバ１２に対して次の行の走査を指示するとともに、列ドライバ１３に対して次の表示データの出力を指示する。
【０１９９】
ラインカウンタ３５の値が（２・Ｎ_４＋１＋表示行数）になると、比較器３６は、ＣＰ信号およびＬＰ信号をローレベルにし、ＳＥＬ信号でセレクタ３９に対して「１」のＤＡＴＡを出力するように指示し、Ｍ信号をハイレベルに固定するそして、基準カウンタ３４のカウント値がＮ_５と一致したら、ＣＬＲ信号を１クロック期間ハイレベルにして、基準カウンタ３４およびラインカウンタ３５を０クリアする。また、／ＤＯＦＦ１信号および／ＤＯＦＦ２信号をローレベルにして液晶印加電圧を０Ｖにし、ＳＴＡＲＴフラグをクリアして初期状態に戻る。
【０２００】
以上、説明したように、例２−１では、Ｍ信号と／ＤＯＦＦ信号とを利用することによって、第１の段階〜第３の段階、すなわち、リセット部、無印加部およびフォーカルコニック促進部（ＦＣ状態への転移を促進する状態）を作成する。したがって、ＩＡＰＴ駆動ドライバを本発明に適用できる。
【０２０１】
そして、無印加部およびフォーカルコニック促進部を複数回（Ｎ_４回）繰り返す。したがって、１パルスでＦＣ状態を実現する場合に比べて短時間で、ＣＬ−ＬＣＤ１０を十分なＦＣ状態に初期化することができる。なお、ここでは、Ｎ_４＝２としたが、図２０に示す構成で、Ｎ_４の値を任意の値にして初期化を行うことができる。
【０２０２】
次に、発明の実施の形態２−Ｂについて、図２２のタイミング図を参照して説明する。なお、コントローラ１１の構成は図２０に示された構成（実施の形態２−Ａ）と同じでよい。
【０２０３】
実施の形態２−Ｂでは、ラインカウンタ３５の値が１になると、比較器３６は、／ＤＯＦＦ２信号をハイレベルし、比較器３６は、ＤＡＴＡをローレベルに固定するようなＳＥＬ信号を出力する。しかし、比較器３６はＣＰ信号を出力しない。よって、列ドライバ１３の内部レジスタの値はハイレベルのままである。基準カウンタ３４は、カウント値がＮ_１と一致するまでカウントアップし、カウント値がＮ_１と一致するとカウント値を０に戻す。このとき、ラインカウンタ３５の値が＋１されて２になる。
【０２０４】
実施の形態２−Ｂでは、ラインカウンタ３５の値が２ｎ＋１（１≦ｎ≦Ｎ_４）のときには、比較器３６は、／ＤＯＦＦ２信号をハイレベルにするのであるが、このとき、Ｍ信号はハイレベルであり、列ドライバ１３にラッチされているＤＡＴＡは全てハイレベルであるから、図１１に示す関係にもとづいて列ドライバ１３の出力電位は全てＶ_５となり、液晶印加電圧はＶ_５（Ｖ_ｒ＋Ｖ_ｃ）となる。
【０２０５】
その他の段階での動作は実施の形態２−Ａの動作と同じである。実施の形態２−Ｂでは、第１の段階および第３の段階で同じ電圧がＣＬ−ＬＣＤ１０に印加される。すなわち、ＣＬ−ＬＣをＨＯ状態に配向させるための印加電圧値と、ＦＣ状態にするための印加電圧値を共通化できた。
【０２０６】
（例２−１）例１−１と同様にして液晶パネルを形成した。次に、この液晶パネルの行、列各１本ずつの電極を選び、その交点に４０Ｖの電圧を２０ｍｓ間印加したところ、印加後に黒塗装していない基板側から見ると交点部分は緑色の反射色を呈した。次に、２０Ｖの電圧を２０ｍｓ印加したところ、印加後に黒塗装していない基板側から見ると交点部分がほぼ黒色を呈した。
【０２０７】
液晶パネルの全画面を初期化するために、表示面の全体に４５Ｖの電圧を５ｍｓ印加した。それに続いて、液晶パネルに印加される電圧が０Ｖになる無印加部を０．３ｍｓを設けた。その後、ＦＣ状態にするための電圧として３３Ｖの電圧を１ｍｓ間印加した。無印加部とＦＣ状態にするための電圧印加期間とを計５回繰り返した後、線順次駆動を実施した。
【０２０８】
行電極が選択される期間をそれぞれ０．１ｍｓとした。なお、０．３ｍｓの電圧無印加部では、ＣＬ−ＬＣはＨＧ状態またはＨＧ状態とＰＬ状態の混在状態に移行するので、効率的にリセット時間の短縮を図ることができる。
【０２０９】
すると、表示データを書き込む前の一連の電圧処理によって十分ＦＣ状態が書き込まれ、コントラスト比の高い表示が得られた。すなわち、テストパターンを表示したところ、残像もなく、高コントラスト比の表示が得られた。なお、一連の表示書き込み動作に要する時間は１７．５ｍｓであった。
【０２１０】
（比較例２−１）例２−１の場合と同様に、全画面を初期化するために、パネル全体に４５Ｖの電圧を５ｍｓ印加した。それに続いて、液晶パネルに印加される電圧が０Ｖになる無印加部を０．３ｍｓを設けた。その後、ＦＣ状態にするための電圧として２３Ｖの電圧を１０ｍｓ間印加し、その後、線順次駆動を実施した。行電極が選択される期間をそれぞれ０．１ｍｓとした。
【０２１１】
テストパターンを表示したところ、残像もなく、高コントラストの表示が得られたが、一連の表示書き込み動作に要する時間は、２１．３ｍｓと例２−１の場合に比べて長くかかった。
【０２１２】
（例２−２）例２−１の場合と同様に、全画面を初期化するために、パネル全体に４５Ｖの電圧を５ｍｓ印加した。それに続いて、液晶パネルに印加される電圧が０Ｖになる無印加部を０．３ｍｓを設けた。その後、ＦＣ状態にするための電圧として４５Ｖの電圧を０．３ｍｓ間印加した。無印加部とＦＣ状態とするための電圧印加期間とを計８回繰り返した後、線順次駆動を実施した。行電極が選択される期間をそれぞれ０．１ｍｓとした。
【０２１３】
テストパターンを表示したところ、残像もなく、高コントラスト比の表示が得られたが、また一連の表示書き込み動作に要する時間は１５．８ｍｓとなり、さらに所要時間を改善できた。また全画面を初期化するための工程のうち、垂直配向にするための電圧条件、すなわち、４５Ｖ，５ｍｓを共通化できた。
【０２１４】
このことは、電源回路の電圧レベルを削減することができるので、駆動回路の実用化の際に有利となる。また、無印加部とＦＣ状態にするための電圧印加期間との繰り返し回数は１０回程度以下であることが好ましい。
【０２１５】
（比較例２−２）例２−２の場合と同様に、全画面を初期化するために、パネル全体に４５Ｖの電圧を５ｍｓ印加した。それに続いて、液晶パネルに印加される電圧が０Ｖになる無印加部を０．３ｍｓを設けた。その後、ＦＣ状態にするための電圧として４５Ｖの電圧を１０ｍｓ間印加し、その後、線順次駆動を実施した。
【０２１６】
行電極が選択される期間をそれぞれ０．１ｍｓとした。テストパターンを表示したところ、残像もなく、高コントラスト比の表示が得られたが、一連の表示書き込み動作に要する時間は、２１．３ｍｓと例２−２の場合に比べて長くかかった。
【０２１７】
（例２−３）例２−１の駆動条件において、線順次駆動による表示データの書き込み時に、選択期間に対して列電極の印加時間を均等に１０分割し、分割された各期間に階調データに応じたオンとオフに相当する電圧を列電極に印加する。そして、そのような電圧印加方法によってテストパターンを表示したところ、表示データに応じた均一な階調表示が得られた。
【０２１８】
（比較例２−３）例２−１の駆動条件において、列電極の印加電圧をオンのときにＶ_ｃ、オフのときに−Ｖ_ｃとし、階調データに応じてｎ・Ｖ_ｃ（−１＜ｎ＜１）の電圧値を列電極に印加した。電圧値を変えることによって１０階調表示を行った。様々なテストパターンを表示させたところ、列電極に平行な表示むらが発生し、不均一な階調表示になった。
【０２１９】
また、中間調表示を行う場合、パルス幅変調を使用すれば良好な階調表示を得ることができる。しかし、振幅変調を使用した場合には良好な階調表示を得ることができない。
【０２２０】
（実施の形態３）次に、より広い温度範囲で駆動を行うことのできる、本発明の実施の形態３について説明する。図２３は駆動装置の実施の一形態を示すブロック図である。コントローラ１１から制御信号としてＦＲ信号、ＬＰ信号、Ｍ信号および／ＤＯＦＦ１信号が行ドライバ１２に入力される。列ドライバ１３には、コントローラ１１からＬＰ信号、ＣＰ信号、Ｍ信号および／ＤＯＦＦ２信号と表示データ（ＤＡＴＡ）とが入力される。／ＤＯＦＦ１信号はコントローラ１１が作成し、列ドライバ１３に供給される／ＤＯＦＦ信号であり、／ＤＯＦＦ２信号は制御装置１１が作成し、行ドライバ１２に供給される／ＤＯＦＦ信号である。また、行ドライバ１２および列ドライバ１３には、電源装置１４から必要な電圧が供給される。
【０２２１】
行ドライバ１２は、ＦＲ信号がハイレベルになると先頭行を選択する。ＬＰ信号は選択行を１行ずつシフトすることを示す信号に相当する。Ｍ信号は、交流化のための信号である。ＣＰ信号は、コントローラ１１から表示データを列ドライバ１３に転送するためのクロックとして用いられる。／ＤＯＦＦ信号がローレベルになると、行ドライバ１２および列ドライバ１３は、液晶パネル１０に印加する電圧レベルをそれぞれ所定のレベル（消去時のレベルＶ_０）にする。／ＤＯＦＦ信号がハイレベルになっているときは通常書き込みの状態である。
【０２２２】
データの書き換えのタイミングを指示するのがＳＴＡＲＴ信号である。ＳＴＡＲＴ信号はタイマによるある一定期間毎に有効になる信号でもよいし、表示データの発生源であるＭＰＵや外部スイッチからの表示書き換え指示信号であってもよい。図２３では、ＭＰＵ２０から出力される例が示されている。
【０２２３】
さらに、液晶パネル１０の近傍には温度センサ８１が設けられ、温度センサ８１の検出出力は温度補償回路４０に入力する。温度補償回路４０は、温度センサ８１の検出出力に応じた印加時間指示信号をコントローラ１１に与える。
【０２２４】
図２４はコントローラ１１の構成例を示すブロック図である。発振器３３は、所定周波数のクロック信号（ＣＬＫ）を発生する。基準カウンタ３４は、ＣＬＫを入力してカウントする。ラインカウンタ３５は、基準カウンタ３４のカウント値が所定値になると、その値を＋１する。比較器３６は、基準カウンタ３４のカウント値（ＤＯＴ）、ラインカウンタ３５のカウント値（ＬＩＮＥ）および設定レジスタ３７の設定値（Ｎ_１〜Ｎ_４）を入力し、ＣＰ信号、Ｍ信号、ＬＰ信号、／ＤＯＦＦ１信号、／ＤＯＦＦ２信号およびＳＥＬ信号を作成する。ＳＥＬ信号はセレクタ３９に出力される。
【０２２５】
メモリ３８には、ＭＰＵ２０からの表示データが格納されている。セレクタ３９は、ＳＥＬ信号に応じて、メモリ３８内のデータ、”１”固定信号および”０”固定信号のうちのいずれかを選択し、選択したデータをＤＡＴＡ信号としてＣＬ−ＬＣＤ１０に出力する。
【０２２６】
設定レジスタ３７には、温度補償回路４０から電圧印加時間の設定のための印加時間指示信号（設定値）が書き込まれる。この実施の形態では、設定値は、発振器３３から出力されるクロック数で換算された値であるとする。ここでは、垂直配向のための高電圧印加時間（第１の段階の期間）をＮ_１、無印加部の時間（第２の段階の期間）をＮ_２、ＦＣ状態への遷移のための電圧印加時間（第３の段階の期間）をＮ_３、線順次駆動における１選択時間をＮ_４とする。
【０２２７】
データの書き換えを必要とする場合には、ＭＰＵから設定レジスタ３７に表示書き換えの指示がなされる。設定レジスタ３７に表示書き換え指示が設定されると、比較器３６にＳＴＡＲＴ信号が出力される。
【０２２８】
図２５は温度補償回路４０の一構成例を示すブロック図である。温度センサ８１の検出出力は、Ａ−Ｄ変換器４１でディジタル信号に変換され、アドレス変換器４２に与えられる。レジスタ５５には、各温度に対応した第１の段階の期間および第３の段階の期間に関する温度係数が格納されている。また、レジスタ５６には、各温度に対応した第２の段階の期間に関する温度係数が格納されている。そして、レジスタ５７には、各温度に対応したアドレッシング部の期間に関する温度係数が格納されている。各温度係数格納領域は、検出温度に対応したアドレスになっている。
【０２２９】
例えば、検出温度が６５℃を越えて７５℃であれば、アドレス変換器４２は、レジスタ５５，５６，５７における７０℃に対応した温度係数ｎ_１、ｎ_２、ｍが格納されているアドレスを出力する。図２５において、７０℃に対応した温度係数ｎ_１、ｎ_２、ｍは、ｎ_１（７０）、ｎ_２（７０）、ｍ（７０）として示されている。
【０２３０】
ここで、ｎ_２≧ｎ_１であり、ｎ_２≧ｍである。そして、各レジスタ５５，５６，５７において、温度が低い方の値がより大きな値である。この実施の形態では、最も高い温度に対応した温度係数を「１」としているので、レジスタ５５，５６，５７に格納されている各値は、１以上の値である。
【０２３１】
レジスタ５１には、所定温度（この例では７０℃）における第１の段階の長さを示すデータ（Ｔ_１０ｒ）が格納されている。また、レジスタ５２には、所定温度（この例では７０℃）における第２の段階の長さを示すデータ（Ｔ_１１ｒ）が格納されている。そして、レジスタ５３には、所定温度（この例では７０℃）における第３の段階の長さを示すデータ（Ｔ_１２ｒ）が格納されている。また、レジスタ５４には、所定温度（この例では７０℃）におけるアドレッシング部の長さを示すデータ（Ｔ_２ｒ）が格納されている。なお、アドレッシング部の長さを示すデータは、１表示シーケンス全体の長さを示すデータでもよいし、１選択期間を示すデータでもよい。
【０２３２】
乗算器６１は、レジスタ５５の出力とレジスタ５１の出力とを乗算して印加時間指示信号を作成する。すなわち、ｎ_１・Ｔ_１０ｒの演算を行って印加時間指示信号を作成する。この印加時間指示信号は、図２４に示す比較器３６が用いるＮ_１（第１の段階：リセット部の長さ）に相当する。乗算器６２は、レジスタ５５の出力とレジスタ５３の出力とを乗算して印加時間指示信号を作成する。
【０２３３】
すなわち、ｎ_１・Ｔ_１１ｒの演算を行って印加時間指示信号を作成する。この印加時間指示信号は、図２４に示す比較器３６が用いるＮ_３（第３の段階：フォーカルコニック部の長さ）に相当する。
【０２３４】
また、乗算器６３は、レジスタ５６の出力とレジスタ５２の出力とを乗算して印加時間指示信号を作成する。すなわち、ｎ_２・Ｔ_１１ｒの演算を行って印加時間指示信号を作成する。この印加時間指示信号は、図２４に示す比較器３６が用いるＮ_２（第２の段階：無印加部の長さ）に相当する。
【０２３５】
そして、乗算器６４は、レジスタ５７の出力とレジスタ５４の出力とを乗算して印加時間指示信号を作成する。すなわち、ｍ・Ｔ_２ｒの演算を行って印加時間指示信号を作成する。この印加時間指示信号は、アドレッシング部の期間の長さＮ_４に相当する。ただし、この例では、Ｎ_４は１選択期間を示す値であるとする。
【０２３６】
次に、図２６のタイミング図を参照して動作について説明する。ここでは、ＣＬ−ＬＣを垂直配向させるために必要な液晶印加電圧および線順次駆動におけるオン電圧をＶ_ｒ＋Ｖ_ｃ、ＣＬ−ＬＣをＦＣ状態とＰＬ状態の混在状態に移行させるために必要な液晶印加電圧および線順次駆動におけるオフ電圧をＶ_ｒ−Ｖ_ｃとする。
【０２３７】
コントローラ１１は、ＭＰＵ２０から表示開始が指示されるまで初期状態とする。すなわち、ＣＰ信号をローレベルに、ＬＰ信号をローレベルに、Ｍ信号をハイレベルに、ＤＡＴＡをハイレベルに、／ＤＯＦＦ１信号および／ＤＯＦＦ２信号をローレベルに維持する。／ＤＯＦＦ１信号と／ＤＯＦＦ２信号とがともにローレベルであるので、すべての行電極および列電極が電位Ｖ_０である液晶無印加状態となる。また、基準カウンタ３４およびラインカウンタ３５はともに０を保持する。
【０２３８】
ＭＰＵ２０から表示開始が指示されると、設定レジスタ３７においてＳＴＡＲＴフラグがセットされ、ＳＴＡＲＴ信号がハイレベルになる。ＳＴＡＲＴ信号がハイレベルになと、比較器３６は、基準カウンタ３４を動作状態にする。基準カウンタ３４は、発振器３３からのクロック（ＣＬＫ）に応じてカウント値を１ずつ増やす。
【０２３９】
ラインカウンタ３５の値が０の場合には、基準カウンタ３４は、その値がＮ_４と一致するまでカウントアップする。比較器３６は、基準カウンタ３４のカウント値が偶数の場合にＣＰ信号をハイレベルにし、奇数の場合にはローレベルにして、表示素子のドット数に適合したパルス数分だけＣＰ信号を出力する。この間、ＤＡＴＡはハイレベルであるから、列ドライバ１３の内部レジスタの値は、全てハイレベルになる。
【０２４０】
基準カウンタ３４のカウント値がＮ_４と一致すると、比較器３６は、ＣＮＴ信号を１クロック期間ハイレベルにする。このＣＮＴ信号に応じて、基準カウンタ３４は値を０に戻し、ラインカウンタ３５は値を＋１する。また、このとき、ＬＰ信号を１クロック期間ハイレベルにする。よって、列ドライバ１３の内部レジスタの値が列ドライバ１３の出力に反映される。
【０２４１】
ラインカウンタ３５の値が１になると、比較器３６は、／ＤＯＦＦ２信号をハイレベルにする。実施の形態１と同様であり、図１１に示す関係から、全ての列電極の電圧レベルがＶ_５（Ｖ_ｒ＋Ｖ_ｃ）となる。また、全ての行電極の電圧レベルはＶ_０であるから、全ての画素に対する液晶印加電圧は（Ｖ_ｒ＋Ｖ_ｃ）となる。すなわち、垂直配向に必要な液晶電圧が全面に印加される。
【０２４２】
また、比較器３６は、ＤＡＴＡをローレベルに固定するようなＳＥＬ信号を出力する。セレクタ３９は、そのようなＳＥＬ信号に応じて”０”を選択する。そして、比較器３６は、ＣＰ信号を順次出力して、列ドライバ１３の内部レジスタの値を全てローレベルにする。基準カウンタ３４は、カウント値がＮ_１と一致するまでカウントアップし、カウント値がＮ_１と一致するとカウント値を０に戻す。このとき、ラインカウンタ３５の値が＋１されて２になる。
【０２４３】
ラインカウンタ３５の値が「２」になると、比較器３６は、／ＤＯＦＦ２信号をローレベルにして、列ドライバ１３の出力電位をすべてＶ_０にする。よって、液晶印加電圧は０Ｖとなる。次に、基準カウンタ３４は、カウント値がＮ_２と一致するまでカウントアップする。
【０２４４】
そして、カウント値がＮ_２と一致すると、基準カウンタ３４のカウント値を０に戻し、ラインカウンタ３５の値を＋１する。ラインカウンタ３５の値が２から３に変化する場合に、比較器３６は、ＬＰ信号を１クロック期間ハイレベルにする。その結果、列ドライバ１３の内部レジスタの値が列ドライバ１３の出力に反映される。
【０２４５】
ラインカウンタ３５の値が「３」のときには、比較器３６は、／ＤＯＦＦ２信号をハイレベルにする。このとき、Ｍ信号はハイレベルであり、列ドライバ１３にラッチされているＤＡＴＡはローレベルであるから、図１１に示す関係にもとづいて全ての列電極に対する印加電圧はＶ_３となり、全ての画素に対する液晶印加電圧はＶ_３（Ｖ_ｒ−Ｖ_ｃ）となる。よって、ＦＣ状態に必要な液晶印加電圧が全面に印加される。次いで、基準カウンタ３４は、カウント値がＮ_３と一致するまでカウントアップし、カウント値がＮ_３と一致すると基準カウンタ３４のカウント値が０に戻り、ラインカウンタ３５の値が＋１される。
【０２４６】
なお、ラインカウンタ３５の値が「３」の場合に、比較器３６は、ＤＡＴＡとしてメモリ３８からの表示データを選択ようなＳＥＬ信号を出力する。セレクタ３９は、そのようなＳＥＬ信号に応じてメモリ３８からの表示データを選択する状態になる。そして、比較器３６は、ＣＰ信号を順次出力して、列ドライバ１３の内部レジスタに表示データを入れる。
【０２４７】
ラインカウンタ３５の値が４になると、比較器３６は、ＬＰ信号を１クロック期間ハイレベルにして、列ドライバ１３の内部レジスタの値を列ドライバ１３の出力に反映させる。また、ＬＰ信号のパルスを包含するようにＦＲ信号を一定期間ハイレベルにし、行ドライバ１２に先頭行からの走査を指示する。
【０２４８】
また、比較器３６は、／ＤＯＦＦ１信号をハイレベルに固定する。よって、列ドライバ１２および行ドライバ１３の出力として線順次駆動に必要な電圧が出力される。図２６では、この期間がアドレッシング部として示されている。
【０２４９】
比較器３６は、アドレッシング部において、基準カウンタ３４のカウント値が（Ｎ_４／２）より小さい場合はＭ信号をローレベルにし、（Ｎ_４／２）以上であればハイレベルにして、線順次駆動時の液晶印加電圧を交流化させる。また、次の選択行のためにＤＡＴＡとしてメモリ３８の表示データを出力する。ＤＡＴＡは、ＣＰ信号によって列ドライバ１３の内部レジスタに取り込まれる。基準カウンタ３４はカウント値がＮ_４と一致するまでカウントアップし、Ｎ_４と一致すると基準カウンタ３４のカウント値が０に戻され、ラインカウンタ３５の値が＋１される。比較器３６は、ラインカウンタ３５の値が＋１される毎に、ＬＰ信号をパルス出力して、行ドライバ１２に対して次の行の走査を指示するとともに、列ドライバ１３に対して次の表示データの出力を指示する。
【０２５０】
ラインカウンタ３５の値が（３＋表示行数）になると、比較器３６は、ＣＰ信号およびＬＰ信号をローレベルにし、ＳＥＬ信号でセレクタ３９に対して「１」のＤＡＴＡを出力するように指示し、Ｍ信号をハイレベルに固定するそして、基準カウンタ３４のカウント値がＮ_４と一致したら、ＣＬＲ信号を１クロック期間ハイレベルにして、基準カウンタ３４およびラインカウンタ３５を０クリアする。また、／ＤＯＦＦ１信号および／ＤＯＦＦ２信号をローレベルにして液晶印加電圧を０Ｖにし、ＳＴＡＲＴフラグをクリアして初期状態に戻る。なお、実施の形態３での表示行数は６０行である。
【０２５１】
以上に説明したように、実施の形態３では、従来の液晶駆動装置が取り扱うことができるＭ信号と／ＤＯＦＦ信号とを利用することによって、第１の段階〜第３の段階、すなわち、リセット部、無印加部およびフォーカルコニック部を作成する。したがって、ＩＡＰＴ駆動ドライバを本発明に適用できる。
【０２５２】
そして、温度補償回路４０が、温度センサ８１の検出温度に応じた電圧印加時間を決定し、決定された電圧印加時間にもとづいて液晶パネル１０のリセットおよび表示データの書き込みが行われるので、低温時でも、良好な表示品位を維持することができる。
【０２５３】
さらに、第２の段階（無印加部）は、第１および第３の段階に比べて、温度低下に応じた電圧印加時間の増加割合を大きくする必要があるが、図２５に示すように、第１および第３の段階に関するレジスタ５５と第２の段階に関するレジスタ５６とを別に設けることによって、第１〜第３の段階の長さを温度に応じた適切な長さに制御することができる。
【０２５４】
（例３−１）室温を２５℃にして、液晶パネル１０の全画面を初期化するために、表示シーケンスの開始時に、パネル全体に４０Ｖの電圧を１３．２ｍｓ間印加した。それに続いて、液晶パネル１０に印加される電圧が０Ｖになる無印加時間を１ｍｓ設けた。その後、ＦＣ状態にするための電圧条件として２３Ｖの電圧を３．３ｍｓ間全画素に印加した。そして、線順次駆動を実施した。駆動波形は図９(Ｂ)に示すものを用いた。
【０２５５】
表示データを書き込む前の一連の電圧処理によって、液晶パネル１０が若干の残留反射が残るＦＣ状態になったことが確かめられた。また、引き続き線順次駆動によって表示書き込みを行うことによって、以上の条件でテストパターンを表示したところ、残像もなく、高コントラスト比の表示が得られた。
【０２５６】
さらに、室温を０℃とした場合に、各電圧印加時間をそれぞれ４倍にした。その場合にも、テストパターンを表示したところ、残像もなく、高コントラスト比の表示が得られた。
【０２５７】
（比較例３−１）室温０℃で、例３−１と同じ電圧印加条件（４０Ｖ，１３．２ｍｓ、０Ｖ，１ｍｓ、２３Ｖ，３．３ｍｓ）で液晶パネル１０を駆動した。テストパターンを表示したところ残像が発生した。すなわち、例３−１と同一の駆動条件では、０℃において、残像が多く良好が表示が得られない。また、それぞれの電圧印加時間を例１の場合と同じにして、それぞれの印加電圧値を上げると、所望の表示が得られたが、コントラストが低い表示になってしまった。
【０２５８】
（例３−２）室温２５℃で、例３−１における電圧印加条件（４０Ｖ，１３．２ｍｓ、０Ｖ，１ｍｓ、２３Ｖ，３．３ｍｓ）のうち、第１の段階、第３の段階および線順次駆動期間において電圧印加時間を２倍にし、また、第２の段階の電圧印加時間を４倍にし、かつ、それぞれの期間における印加電圧値を例３−１の場合よりも高くした。テストパターンを表示したところ、残像もなく、高コントラストの表示が得られた。さらに、例３−１の０℃の場合の電圧印加条件に比べて書き込み時間を短くすることができた。
【０２５９】
（比較例３−２）室温０℃で、例３−１における電圧印加条件（４０Ｖ，１３．２ｍｓ、０Ｖ，１ｍｓ、２３Ｖ，３．３ｍｓ）のうち各電圧印加時間を２倍にした。テストパターンを表示したところ、残像はないもののコントラストの低い表示になってしまった。
【０２６０】
上述したように、第１の段階で、それ以前に書き込まれた表示状態を消去するために、ＣＬ−ＬＣの配向状態をＨＯ状態にする。また、第２の段階で、ＣＬ−ＬＣの配向状態をＨＯ状態からＨＧ状態またはＨＧ状態とＰＬ状態の混在状態にする。さらに、第３の段階で、ＨＧ状態またはＨＧ状態とＰＬ状態の混在状態からＦＣ状態またはＦＣ状態とＰＬ状態の混在状態にする。そして、線順次駆動期間で、ＦＣ状態またはＦＣ状態とＰＬ状態の混在状態から所望の表示状態を書き込む。
【０２６１】
例３−１より、ＣＬ−ＬＣの温度が低下した場合には、各段階の電圧印加時間を長くすればよいことがわかる。例えば、２５℃から０℃に低下した場合には、電圧印加時間を数倍すれば良好な表示品位を維持することができる。
【０２６２】
しかし、各配向状態に変化させるために必要な電圧印加時間は、各段階の間で異なっている。例３−２および比較例３−２から、ＣＬ−ＬＣをＨＯ状態からＨＧ状態またはＨＧ状態とＰＬ状態の混在状態にする第２の段階は、それ以外の段階に比べて、温度低下に応じた電圧印加時間の増加割合を大きくする必要があることがわかる。
【０２６３】
第２の段階において、ＨＯ状態から、充分にＨＧ状態またはＨＧ状態とＰＬ状態の混在状態にすることができない場合には、第３の段階において、所望のＦＣ状態またはＦＣ状態とＰＬ状態の混在状態にすることができず、その結果、線順次駆動期間において、本来ＦＣ状態に設定したいオフ時の反射率が上昇しコントラスト比が低下する。
【０２６４】
（例３−３）室温５０℃で、例３−１における電圧印加条件（４０Ｖ，１３．２ｍｓ、０Ｖ，１ｍｓ、２３Ｖ，３．３ｍｓ）に対して、それぞれの期間における印加電圧をやや低めに設定して液晶パネル１０を駆動した。テストパターンを表示させたところ、残像もなく、高コントラスト比の表示が得られた。
【０２６５】
（例３−４）室温５０℃で、例３−１における電圧印加条件（４０Ｖ，１３．２ｍｓ、０Ｖ，１ｍｓ、２３Ｖ，３．３ｍｓ）に対して、それぞれの電圧印加期間を１／２に設定して液晶パネル１０を駆動した。また、それぞれの期間における印加電圧を例３−１の場合よりもやや低めに設定した、テストパターンを表示させたところ、残像もなく、高コントラスト比の表示が得られた。
【０２６６】
以上より、２５℃のときの電圧印加条件を基準に、０℃ときは電圧印加時間を２倍にして、５０℃のときには電圧印加時間を１／２にすれば、２５℃に対して高温または低温になっても良好な表示が得られることがわかる。
【０２６７】
なお、表示データを書き込む前の一連の電圧処理（表示リセット）のうち、第１の段階の期間と第３の段階の期間に関して、温度変化に応じた期間増減の倍率は表示データを書き込むときの期間の増減の倍率と同じである。しかし、第２の期間に関しては、温度が低くなった場合、それらの倍率よりも電圧印加期間（０Ｖの電圧印加期間）の倍率を大きくとることが好ましい。
【０２６８】
具体的な温度設定については、表示リセットにおける第２の段階の期間を除いた全ての期間（表示リセットと表示データの書き込みの期間）に関して、倍率ｎ（ｔ_ｐ）は（ｔ_ｐ＝温度）、５〜５０の範囲の定数であるＫ_Ａを、下記式３を満たすように設定するとコントラストの高い表示を得ることができた。下記式３において、「＾」の右側は指数を示す。
【０２６９】
ｎ（ｔ_ｐ）＝ｎ（２５）×２＾（（２５−ｔ_ｐ）／Ｋ_Ａ） ・・・（３）
【０２７０】
また、所定温度を２５℃とすると、任意の温度ｔ_ｐにおける表示データに対応した電圧条件にもとづいて各画素に電圧を印加する期間（アドレッシング期間）の長さをＴ_２（ｔ_ｐ）としたときに、下記式４の関係を満たすことが好ましい。
【０２７１】
Ｔ_２（ｔ_ｐ）＝Ｔ_２（２５）×２＾（（２５−ｔ_ｐ）／Ｋ_Ｂ） ・・・（４）
【０２７２】
Ｋ_Ｂは使用するＣＬ−ＬＣに応じて設定される定数であり。５〜５０の範囲に設定することが好ましい。Ｋ_ＡとＫ_Ｂはおよそ２５にすることが好ましい。
【０２７３】
さらに、第２の段階は印加電圧０Ｖの状態であるから、所定の温度でその期間をあらかじめ長い期間に設定しておけば、温度によって、全ての段階の期間を一律に設定することができる。かつ、電圧振幅を調整することもなく、各温度において高速の表示を行うことができた。
【０２７４】
次に、ＣＬ−ＬＣＤをＨＧ状態またはＰＬ状態でリセットを行う参考例について説明する。図２７に駆動波形のタイミングチャートを、図２８に駆動回路のうちの信号変換回路のブロック図を、図２９に信号変換回路の動作のタイミングチャートを示す。回路構成と動作に関し、上記の発明の実施の形態１、２および３と多くの点で共通する。本参考例で必要とする電圧パルスを発生するように、図１６の回路構成および図１７の動作タイミングを変更することで達成できる。
【０２７５】
すなわち、例１−１の液晶パネルに図２７の駆動波形で表示を行った。液晶パネル全体に４０Ｖの電圧を１３．３ｍｓ印加し、それに引き続いて、無電圧時間を１ｍｓ設けた。続いて、線順次駆動を行ったｖ。選択時には、オン表示（ＰＬ状態）では、Ｖ_ｒ＋Ｖ_ｃの電圧が印加され、オフ表示（ＦＣ状態）では、Ｖ_ｒ−Ｖ_ｃの電圧が印加された。Ｖ_ｒ＝３５Ｖ，Ｖ_ｃ＝５Ｖとした。また、行電極の選択時間を３．３ｍｓにした。テストパターンを表示した結果、残像もなく高コントラスト比の表示が得られた。
【０２７６】
（例４）上記の発明の実施の形態１、２、３および参考例のそれぞれを用いて、携帯型の表示装置の一種である電子ブック、ページャーやモバイル型表示装置に使用できる液晶パネルを作成した。行電極と列電極を備えた高精彩なフルドットマトリックスの表示が鮮明に行うことができた。図３０にその表示の一態様を示す。文字が細かくても、充分に読み取ることができた。また、視野角が広く、表示画面の書き換えが違和感なく実行され、見やすい表示品位を達成できた。また、比較的大型の表示画面を用いる公衆表示装置や、電子写真表示装置にも適用できるものであった。
【０２７７】
【発明の効果】
以上のように、本発明では、表示データの書き込みを行う前にコレステリック液晶を確実にＦＣ状態または準ＦＣ状態に揃えることができ、高速書き込みを行っても残像を生じさせたり、表示のコントラスト比が低下することを防止でき、表示を高精細化した場合にも表示品位を高くすることができる効果がある。さらに、コレステリック液晶の状態をＦＣ状態に揃えるための時間が短縮されるので、一連の画像を更新するシーケンスに要する時間をより短縮することができる。
【図面の簡単な説明】
【図１】 ＨＯ状態にあるＣＬ−ＬＣＤの電圧パルス印加および遮断後の相対誘電率の変化を示すグラフ。
【図２】 ＣＬ−ＬＣＤの電圧遮断後の反射スペクトルを示すグラフ。
【図３】 第３の電圧パルスの印加時間を３．３ｍｓとした場合のリセット後の反射率と第３の電圧パルスの電圧振幅との関係を示すグラフ。
【図４】 ＣＬ−ＬＣＤの断面の模式図。
【図５】 電圧パルス（１３．３ｍｓ）を印加し消去して表示状態の変化を示す状態図。
【図６】 電圧パルスの幅を短くした場合（６．６ｍｓ）の状態図。
【図７】 電圧パルスの幅を短くした場合（３．３ｍｓ）の状態図。
【図８】 液晶パネルを駆動する駆動装置の構成例を示すブロック図。
【図９】 模式的に示した駆動波形図。
【図１０】 ＩＡＰＴ駆動ドライバの機能を説明するための説明図。
【図１１】 制御信号と印加電圧との関係を示す説明図。
【図１２】 駆動装置（実施の形態１−Ａ）の構成を示すブロック図。
【図１３】 実施の形態１−Ａにおける信号変換回路の構成例を示すブロック図。
【図１４】 信号変換回路の動作を示すタイミング図。
【図１５】 駆動装置（実施の形態２−Ａ）の構成を示すブロック図。
【図１６】 実施の形態２−Ａにおける信号変換回路の構成例を示すブロック図。
【図１７】 実施の形態２−Ａにおける信号変換回路の動作を示すタイミング図。
【図１８】 ＣＬ−ＬＣの配向状態を示す説明図。
【図１９】 パルス幅変調（ＰＷＭ）を用いてＦＣ状態を書き込むまでの所要回数を示す説明図。
【図２０】 ＰＷＭ法のコントローラの構成例を示すブロック図。
【図２１】 ＰＷＭ法のコントローラの動作を示すタイミング図。
【図２２】 ＰＷＭ法のコントローラの動作を示すタイミング図。
【図２３】 温度補償型の駆動装置の構成例を示すブロック図。
【図２４】 温度補償回路の構成例を示すタイミング図。
【図２５】 温度補償回路の構成例を示すタイミング図。
【図２６】 表示シーケンス制御回路の動作を示すタイミング図。
【図２７】 ＰＬ状態でのリセットを行なう場合の駆動波形を示す波形図。
【図２８】 ＰＬ状態でのリセットを行なう駆動回路を示すブロック図。
【図２９】 ＰＬ状態でのリセットを行なう際のタイミング図
【図３０】 本発明の液晶表示装置の一例における表示状態を示す説明図。
【図３１】 ＣＬ−ＬＣの相状態の転移を示す模式図。
【符号の説明】
１Ａ，１Ｂ ガラス基板
２Ａ，２Ｂ 電極
３Ａ，３Ｂ 高分子薄膜
４ 液晶組成物
５ 光吸収体
１０ コレステリック液晶パネル（液晶光学素子）
１１ 信号制御回路（コントローラ）
１２ 行ドライバ
１３ 列ドライバ
１４ 信号変換回路
１５ 電源装置
１６ スイッチ回路
２１ ０．５ライン検出回路
２２ 論理和回路
２３ セレクタ
２３Ａ 論理和回路
２４ ダウンカウンタ
２５〜２９ 比較器
３０ スタートフラグ回路
３１ ＤＯＦＦ制御回路
３３ 発振器
３４ 基準カウンタ
３５ ラインカウンタ
３５ 比較器
３７ 設定レジスタ
３８ メモリ
３９ セレクタ
４０ 温度補償回路
８１ 温度センサ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a driving method and a driving device for a liquid crystal display device including a liquid crystal layer having memory properties.
[0002]
[Prior art]
At present, TN, STN, and TFT liquid crystal display elements are widely used. These liquid crystal display elements always perform predetermined driving to perform display. On the other hand, cholesteric or chiral nematic liquid crystal (hereinafter referred to as CL-LC) having a memory-like operation mode has attracted attention, and practical application of a liquid crystal display device (hereinafter referred to as CL-LCD) including the cholesteric or chiral nematic liquid crystal has been studied. Has been.
[0003]
The CL-LC sandwiched between a pair of parallel substrates has a “twisted structure” in which the liquid crystal director is twisted at a constant period. There is an array in which the central axis of the twist (hereinafter referred to as a helical axis) is perpendicular to the substrate on average.
[0004]
The complete planar state (hereinafter referred to as PP state) in which the helical axes of the plurality of liquid crystal domains are almost completely perpendicular to the substrate surface, and the average direction of the helical axes of the plurality of liquid crystal domains is the substrate surface. On the other hand, there is an incomplete planar state (hereinafter referred to as a PL state) that is substantially perpendicular to the surface. Then, the circularly polarized light corresponding to the twist direction of the liquid crystal layer in the incident light is selectively reflected. The wavelength λ selectively reflected is the average refractive index n of the liquid crystal composition._AVGIs approximately equal to the product of the pitch p of the liquid crystal composition (λ = n_AVG-P).
[0005]
The pitch p is determined by p = 1 / (c · HTP) from the addition amount c of an optically active substance such as a chiral agent and the constant HTP (Helical Twisting Power) of the optically active substance. Therefore, the selective reflection wavelength can be adjusted by the type and amount of optically active substance. If the pitch is set so that the selective reflection wavelength of CL-LC is out of the visible range, it becomes transparent visually during selective reflection and exhibits a transmission scattering operation mode.
[0006]
In the PP state, normal reflection with respect to incident light is large, and extremely high reflection characteristics are exhibited at a specific viewing angle. In the PL state, the regular reflection is relatively small and exhibits high reflection characteristics at a relatively wide viewing angle. Further, the CL-LC can take a focal conic state (hereinafter referred to as an FC state) in which helical axes of a plurality of liquid crystal domains are arranged in a random direction or a non-perpendicular direction with respect to the substrate surface. In general, the liquid crystal layer in the FC state exhibits a weak scattering state as a whole. The light of a specific wavelength is not reflected unlike the selective reflection. The FC state, the PL state, and the PP state exist stably even when there is no electric field.
[0007]
18A is a schematic diagram of the PL state, and FIG. 18B is a schematic diagram of the FC state. The alignment state of the liquid crystal domain indicated by the drum shape is shown. The selective reflection wavelength in the PP state is approximately λ = n_AVG・ It is given by p. Since the selective reflection wavelength in the PL state has a distribution in the direction of the helical axis, it tends to shift to the shorter wavelength side than in the PP state.
[0008]
In the FC state of FIG. 18B, the color of the absorption layer can be displayed by providing the absorption layer on the back surface side. Therefore, it is possible to realize a memory-type display operation using two states, a PL state that is a bright state and an FC state that is a dark state (when the absorption layer is black).
[0009]
The basic structure of the CL-LCD is shown in George H. Heilmeier, Joel E. Goldmacher et al, Appl. Phys. Lett., 13 (1968), 132 and US Pat. No. 3,936,815. US 4097127 shows that there is a stable intermediate state in which the PL state and the FC state are mixed and can be used for display.
[0010]
Next, a driving method of the CL-LCD will be described. In US Pat. No. 3,936,815, the PL state is changed to the FC state and the FC state is changed to the PL state depending on the amplitude of the drive voltage. In the latter case, the highest voltage is required because the liquid crystal molecules are generated via a homeotropic state (hereinafter referred to as HO state) in which the liquid crystal molecules are substantially parallel to the voltage application direction.
[0011]
In CL-LC, the effective value of a series of applied voltage waveforms does not directly determine the state after voltage erasure, but the display after voltage erasure depends on the application time and amplitude value of the voltage pulse applied immediately before. .
[0012]
Next, matrix display in the CL-LCD will be described. The voltage to transfer to the FC state is V_FAnd the lower limit voltage for transition to the PL state is V_PV is the upper limit voltage that does not change the display state even when voltage is applied._SAnd
[0013]
When line sequential driving is performed, the voltage amplitude V is applied to the row electrode._rVoltage pulse is inputted, and the voltage amplitude V is applied to the column electrode in synchronization with it._cInput the voltage pulse (selection pulse). A selection pulse is input once for each row electrode to complete one display sequence. When ON display is selected in the display sequence, (V_r+ V_c) Is input only once, and the voltage V_cIs applied. When off display is selected, (V_r-V_c) Is input only once, and the voltage V is applied during the off-selection non-selection period._cIs applied. Assuming that the PL state is selected when on and the FC state is selected when off, the respective conditions are as follows.
[0014]
V_r+ V_c> V_P, V_r-V_c= V_F
[0015]
In addition, V is set so that the written state does not change._c<V_SMust. If the applied voltage is controlled as described above, matrix display is possible.
[0016]
In the CL-LCD, even if the number of scanning electrodes is increased, the display quality in a state where display data is written does not deteriorate. Further, the drive voltage does not increase even if the number of electrodes increases. However, as the number of scanning electrodes increases, the appearance of display when writing display data becomes worse. That is, when writing a display state, a selection pulse is input to each scan electrode with a fixed application time. At this time, when the number of scanning electrodes increases, a state in which scanning lines flow on the display screen is visually recognized. Therefore, it is necessary to shorten the display sequence by shortening the application time of the selection pulse as the number of scanning electrodes increases.
[0017]
When the application time of the selection pulse is shortened, good display characteristics can be maintained by adjusting the applied voltage amplitude for writing from off display (FC state) to on display (PL state). On the other hand, there is a problem in writing from on display (PL state) to off display (FC state). At this time, a sufficiently fine scattering state cannot be obtained in the FC state, and a part of the liquid crystal alignment showing selective reflection may remain. And the written off display (FC state) does not become dark enough. As described above, this is a case where the black absorption layer is provided on the back side of the CL-LCD.
[0018]
That is, the display contrast ratio is lowered. Also, the area where the previous display is ON display (PL state) and then written to the OFF display (FC state), and the area where the previous display is OFF display and the OFF display is written several times in succession In some cases, there was a difference in brightness and display unevenness.
[0019]
The cause is the application time of the selection pulse. If the application time is shortened, it is not possible to shift to a completely finely scattered FC state by one off display writing. In addition, the written off-display optical characteristics, that is, the degree of fine scattering in the FC state or the degree of remaining liquid crystal alignment exhibiting selective reflection, change depending on the previous state.
[0020]
As a result, a previously written image may appear as an afterimage. Therefore, it has been difficult to shorten the application time of the selection pulse, that is, increase the number of scanning electrodes, while maintaining good display quality.
[0021]
[Problems to be solved by the invention]
As described above, in the CL-LCD, when the number of scanning electrodes is increased to increase the display capacity, there are problems that the contrast ratio is reduced and display unevenness occurs.
[0022]
In other words, it is necessary to increase the writing time in order to maintain the display quality when the display is made high definition. However, if the writing time is lengthened, the scanning line will flow on the display screen with the naked eye. In addition to the driving method of US3936815, the following driving method is known.
[0023]
SID 92, Digest, pages 759 to 761 (1992) shows that a pulsed voltage is applied to CL-LC to reset the alignment state of the liquid crystal before voltage application to the PL state or the FC state. . 6 shows a drive waveform. US5933203 discloses a technique in which a voltage pulse having a smaller amplitude is continuously applied subsequently to a voltage pulse having a large amplitude to be in the HO state.
[0024]
Also, EP 0957394A1 Patent Publication discloses a CL-LCD reset method. After a voltage pulse that causes the liquid crystal layer to enter the HO state, a voltage pulse that causes the PL state to be applied is applied, and then a voltage pulse that causes the FC state to be applied is further applied. In this case, since the transition speed is slow and the phase transition from the HO state to the PL state is performed, the time required for the reset becomes long as a whole. In addition, since all the pixels are temporarily reflected in the PL state, flickering occurs during reset.
[0025]
At the time of rewriting the display, as the CL-LC state after erasing the previous display, either the PL state showing selective reflection or the FC state showing no reflection may be selected. However, since the HO state at the time of erasing does not show reflection, the FC state that does not show reflection similarly after erasing has a natural appearance particularly in the case of negative display with the background being non-reflective.
[0026]
Further, “afterimage” is one of problems caused by shortening the application time of the selection pulse. This occurs because the written off-state optical properties remain behind. That is, the alignment state of the liquid crystal in the FC state is affected by the alignment state before the phase transition, and the liquid crystal alignment at the time of selective reflection remains slightly. Thus, in the case of the prior art, only by applying a short voltage pulse once, there remains no selective reflection at all, and an FC state exhibiting the lowest reflectance when an absorption layer is provided on the back surface is obtained. Is very difficult.
[0027]
Therefore, the present invention intends to provide a driving method capable of resetting the display in a short time in the CL-LCD. That is, an object of the present invention is to provide a driving method and a driving apparatus that can prevent a reduction in display contrast ratio and perform high-quality, high-definition display even when high-speed writing is performed. It is another object of the present invention to provide a method for driving a memory cholesteric liquid crystal display device that exhibits good display quality even at low temperatures.
[0028]
[Means for Solving the Problems]
The inventors of the present invention have studied in detail the state of rearrangement of liquid crystal molecules immediately after applying a high-voltage pulse that brings the CL-LCD to the HO state. First, the relationship between the applied voltage and the optical characteristics after voltage erasure will be described. The CL-LCD to be used has a positive dielectric anisotropy, and a phase is changed by a voltage pulse to perform display.
[0029]
First, the CL-LCD is set to a PL state that exhibits selective reflection. Then, the application time of the applied voltage pulse is fixed, and the voltage amplitude is increased. While the voltage amplitude is small, the initial PL state does not change and the reflectance does not change after the voltage is cut off. When the voltage amplitude is further increased, after the voltage is cut off, the CL-LCD is in the FC state and shows a fine scattering state. Color display by the absorption layer provided on the back side (black display when the absorption layer is black) is obtained.
[0030]
When the voltage amplitude is further increased, a PL state similar to the initial state is obtained as a state after the voltage is cut off. In addition, as an initial state, a voltage pulse is applied to the CL-LCD in the FC state that exhibits a fine scattering state, and the change in the display state is confirmed. The experiment was repeated by changing the conditions.
[0031]
When the initial state is the FC state, the voltage pulse application time is fixed and the voltage amplitude is increased. While the voltage amplitude is small, the initial FC state does not change and the reflectivity hardly changes after the voltage is cut off. When the voltage amplitude is further increased, a weak selective reflection state in which fine scattering and selective reflection are mixed is obtained as a state after the voltage is cut off. When the voltage is further increased, a PL state exhibiting selective reflection can be obtained as a state after the voltage is cut off.
[0032]
That is, a voltage pulse having a predetermined voltage amplitude or more is applied to the CL-LCD in the PL state to cut off the voltage. Then, the PL state changes to the FC state. In the FC state, when a voltage pulse with a larger voltage amplitude is applied, the state after the voltage interruption becomes the PL state. When a high voltage is applied to enter the PL state, the liquid crystal molecules pass through the HO state in which the major axis direction of the liquid crystal molecules is aligned with the voltage application direction when the voltage is applied, regardless of whether the initial state is the PL state or the FC state.
[0033]
While the CL-LCD in the HO state is rearranged to the PL state after the voltage is cut off, it goes through several liquid crystal alignments. Therefore, depending on the viscosity of the liquid crystal, a time of several hundred ms to several seconds may be required.
[0034]
FIG. 1 shows a change in relative dielectric constant of a CL-LCD after applying a voltage pulse to bring it into a HO state. The change in dielectric constant is considered to indicate the change in the average orientation direction of the liquid crystal molecules. The dielectric constant shows a minimum value about 0.5 ms after the voltage is cut off, and becomes almost stable in about 1.5 ms. That is, it can be seen that the average orientation direction of the liquid crystal molecules is most parallel to the substrate surface around 0.5 ms after the voltage is cut off.
[0035]
FIG. 2 shows a change in the reflection spectrum after the voltage of the CL-LCD is cut off. The time of “0.4 to 100 ms” in the figure indicates the elapsed time after voltage interruption. It can be seen that selective reflection is not observed until about 1 ms after the voltage is cut off, and thereafter the reflection intensity gradually increases, and it takes a time of several hundred ms or more for complete rearrangement from the HO state to the PL state.
[0036]
From the state of dielectric constant change and reflection characteristics, it was found that CL-LC had a special molecular arrangement immediately after application of a high-voltage voltage pulse to bring it into the HO state. That is, there is a homogeneous liquid crystal alignment (hereinafter referred to as HG state) which is a transitional state where the dielectric constant is the smallest and the liquid crystal molecules are substantially parallel to the substrate and does not have a helical structure with a predetermined pitch. In addition, the time from when the voltage is cut off until the HG state appears is expressed as τ_HAnd
[0037]
Further, CL-LC gradually forms a helical structure with a predetermined pitch after passing through the HG state. The liquid crystal alignment during this period is called an intermediate state between the HG state and the PL state. In order to obtain a good FC state in as short a time as possible, after applying the first voltage pulse (high voltage pulse) for setting the HO state, the second voltage pulse is applied, and then the FC state is set. The third pulse is applied.
[0038]
The amplitude of the second voltage pulse was set to 0 V, and the application time of the third voltage pulse was set to 3.3 msec in order to achieve reset in as short a time as possible. FIG. 3 shows the relationship between the reflectance after reset and the amplitude of the third voltage pulse in this case.
[0039]
The numerical values (●: 0 sec, ▲: 0.3 msec, ■: 1 msec, x: 3.3 msec) in FIG. 3 indicate the width of the second voltage pulse. When the width of the second voltage pulse is 0 sec, this corresponds to the prior art, and the third voltage pulse is applied immediately after the first voltage pulse without applying the second voltage pulse.
[0040]
As is apparent from FIG. 3, the width of the second voltage pulse is τ_HIn the following cases, the obtained reflectance in the FC state is high. Further, the margin of the optimum voltage of the third pulse is small. In particular, unless the second voltage pulse is used, the FC state cannot be formed with a short third voltage pulse. The FC state here includes a mixed state of the FC state and the PL state. The optical state can continuously change between the FC state and the PL state according to the ratio of the FC state and the PL state. A mixed state is also called a quasi-FC state. FIG. 31A schematically shows the basic phase change in the present invention. This is a case of transition from the HO state to the HG state and then to the quasi-FC state. FIG. 31B is a prior art, and schematically shows a transition to the HO state, the PL state, and the FC state.
[0041]
In order to enable the FC state to be formed in a short period, it is preferable that the width of the second voltage pulse for changing from the HO state to the HG state or the mixed state of the HG state and the PL state is as small as possible. Specifically, the width of the second voltage pulse is set to τ₂It is preferable that the following formula 1 is satisfied.
[0042]
0.8 ・ τ_H≦ τ₂≦ 8 ・ τ_H                ... (1)
[0043]
Furthermore, it is more preferable to satisfy the following formula 2.
[0044]
τ_H≦ τ₂≦ 5 ・ τ_H                ... (2)
[0045]
In addition, τ₂In order to reduce the voltage, the third voltage pulse can be applied from the HG state that does not show the predetermined selective reflection in the PL state.
[0046]
From the above, if the application time of the second voltage pulse is gradually reduced, τ_HThe FC state is formed up to the vicinity. However, τ_HIf it is smaller than that, the voltage margin is also reduced, and the FC state is not sufficiently formed. τ_HIs obtained by the dielectric constant measurement method of FIG. From FIG. 2, τ_HIt does not show selective reflection in a small area from the vicinity.
[0047]
That is, τ_HThere is no selective reflection in a slight region beyond the vicinity, or the degree of selective reflection is low, and the width τ of the second voltage pulse₂Even if is set in such an area, it is considered that the viewer does not feel uncomfortable every time the display data is rewritten. In the present invention, in the characteristic curve shown in FIG. 2, a region within about 30% of the maximum reflectance value in the PL state is set as a region that can be used for the reset operation. The transition to a desired phase state is controlled by adjusting the voltage pulse to be applied within that range.
[0048]
When display is performed by a conventional driving method, a kind of flash phenomenon may occur. That is, first, the HO state becomes a dark state (a state where the black color on the back surface is visually recognized), and thereafter, the PL state by the second voltage pulse becomes the bright state, and further, the third voltage pulse becomes the dark state again. Then, each time the display data is rewritten, the display device changes from the dark state to the bright state, and further changes from the bright state to the dark state, which makes the viewer feel uncomfortable.
[0049]
In the present invention, in addition to the advantage that the initialization process can be performed in the shortest possible time for high-speed display data rewriting, every time the display data is rewritten, the viewer feels uncomfortable. There is also an advantage that there is nothing.
[0050]
Based on the above considerations, the basic configuration of the embodiment of the present invention is that the CL-LC orientation is substantially parallel to the voltage application direction before the voltage is applied to each pixel based on the voltage condition corresponding to the display data. A first stage in which voltage is applied so as to become a second stage, a second stage in which voltage is applied to shift CL-LC to an HG state or a mixed state of HG state and PL state, and CL-LC to HG state. Alternatively, a third stage of applying a voltage for shifting from the mixed state of the HG state and the PL state to the FC state is provided.
[0051]
Further, in the second stage, the CL-LC may be set to an HG state that does not show predetermined selective reflection in the PL state, and the third voltage pulse may be applied from that state. Further, a preferable voltage value applied in the second stage is 0V.
[0052]
The driving method of the CL-LCD is such that the applied voltage waveform in the first stage is V₁The voltage waveform of the third stage is V.₃It is composed of a pulse voltage with a voltage amplitude of₁, Τ₃V₁Is V₃Larger and τ₃Is τ₁It is preferable to set it to be smaller.
[0053]
In addition, when the line sequential operation is performed to apply the voltage waveform based on the display data of each display pixel after the first stage to the third stage, the PL state is written in the on display, and in the off display. When the applied voltage condition is determined so that the FC state is written, a pulse width modulation method may be used for halftone display.
[0054]
According to a first aspect of the present invention, in a driving method for driving a liquid crystal display device including a memory cholesteric liquid crystal, a first step of applying a voltage so that the orientation of the cholesteric liquid crystal is substantially parallel to the voltage application direction; A second stage of applying a voltage for shifting the cholesteric liquid crystal to a homogeneous state or a mixed state of homogeneous and planar, and a voltage for shifting the cholesteric liquid crystal to a focal conic state from the homogeneous or mixed state of homogeneous and planar And a third stage. A driving method is provided.
[0055]
According to a second aspect, in a driving method for driving a liquid crystal display device including a memory cholesteric liquid crystal, a first step of applying a voltage so that the orientation of the cholesteric liquid crystal is substantially parallel to the voltage application direction; A second stage for applying a voltage for shifting the cholesteric liquid crystal to a homogeneous or homogeneous / planar mixed state; and And a third step of applying a voltage. A driving method is provided.
[0056]
In the third aspect, the period of the second stage is set to τ.₂Τ is the time required for the cholesteric liquid crystal in the homeotropic state to exhibit the lowest dielectric constant after voltage interruption by applying voltage._HThen 0.8 × τ_H≦ τ₂≦ 8 × τ_HThe driving method according to the first aspect or the second aspect is provided. The fourth aspect is τ_H≦ τ₂≦ 5 × τ_HA driving method according to a third aspect that satisfies the above is provided.
[0057]
The fifth aspect provides the driving method according to any one of the first to fourth aspects, in which the voltage value applied in the second stage is 0V.
[0058]
In the sixth aspect, the applied voltage waveform in the first stage is V₁The voltage waveform of the third stage is V.₃It is composed of a pulse voltage with a voltage amplitude of₁, Τ₃V₁Is V₃Larger and τ₃Is τ₁A driving method according to any one of the smaller first to fifth aspects is provided.
[0059]
Further, in the seventh aspect, when a line sequential operation is performed to apply a voltage waveform based on display data of each display pixel after the first stage to the third stage, a planar is written in the on display. When the applied voltage condition is determined so that the focal conic is written in the off display, the driving method according to any one of the first to sixth aspects using the pulse width modulation method for the halftone display is provided.
[0060]
According to an eighth aspect, in a driving device for driving a liquid crystal display device provided with a memory-type cholesteric liquid crystal, first period setting means for setting a period of the first stage, and a first period following the first stage. Oriented in the first period created by the second period setting means for setting the second period, the third period setting means for setting the third period following the second stage, and the first period setting means A voltage for applying a voltage to the cholesteric liquid crystal so that is substantially parallel to the voltage application direction, and shifting the cholesteric liquid crystal to a homogeneous or a mixture of homogeneous and planar in the second period created by the second period setting means Is applied to the cholesteric liquid crystal in the third period created by the third period setting means from the homogeneous or homogeneous and planar state to the focal conic or planar. To provide a driving apparatus characterized by comprising a voltage applying means for applying a voltage for shifting to a mixed state of Okarukonikku.
[0061]
According to a ninth aspect of the present invention, there is provided a driving method for driving a liquid crystal display device provided with a cholesteric liquid crystal having a memory property, wherein the driving method is performed before applying a voltage to each pixel based on a voltage condition corresponding to display data. In addition, a first step of applying a voltage so that the orientation of the cholesteric liquid crystal is substantially parallel to the voltage application direction, and a second step of applying a voltage for shifting the cholesteric liquid crystal to a homogeneous state or a mixed state of a homogeneous and a planar state. And a third stage for applying a voltage for promoting the transition from the homogeneous state of the cholesteric liquid crystal or the mixed state of the homogeneous and the planar state to the focal conic state or the mixed state of the focal conic and the planar state. A driving method characterized by repeating the second stage and the third stage after Subjected to.
[0062]
The tenth aspect provides the driving method according to the ninth aspect, in which the voltage value applied in the second stage is 0V.
[0063]
The eleventh aspect provides the driving method according to the ninth aspect or the tenth aspect, wherein the number of repetitions of the second stage and the third stage is 2 to 10 times.
[0064]
In the twelfth aspect, the applied voltage waveform in the first stage is V₁The voltage waveform of the third stage is V.₃It is composed of a pulse voltage with a voltage amplitude of₁, Τ₃V₁Is V₃Larger and τ₃Is τ₁A smaller driving method of the ninth, tenth, or eleventh aspect is provided.
[0065]
In the thirteenth aspect, the applied voltage waveform in the first stage is V₁The voltage waveform of the third stage is V.₃It is composed of a pulse voltage with a voltage amplitude of₁, Τ₃V₁Is V₃And τ₃Is τ₁A smaller driving method of the ninth, tenth, or eleventh aspect is provided.
[0066]
In the fourteenth aspect, when the line sequential operation is performed to apply the voltage waveform based on the display data of each display pixel after the first stage to the third stage are completed, a planar is used for on display. When the applied voltage condition is determined so that the focal conic is written in the off display, the driving method according to any one of the ninth to thirteenth aspects using the pulse width modulation method in the halftone display is provided.
[0067]
According to a fifteenth aspect, in a driving device for driving a liquid crystal display device provided with a cholesteric liquid crystal having memory properties, a first period setting means for setting a period of the first stage, and a first stage Second period setting means for setting a second period that follows, third period setting means for setting a third period following the second stage, and a first period created by the first period setting means To apply a voltage to the cholesteric liquid crystal so that the orientation is substantially parallel to the voltage application direction, and to shift the cholesteric liquid crystal to a homogeneous state or a mixture of homogeneous and planar in the second period created by the second period setting means. And the focal period or the mixed state of the cholesteric liquid crystal in the third period created by the third period setting means. A voltage applying means for applying a voltage for promoting the transition to the mixed state of the Renner and the focal conic, and a second period setting means and a third period setting means after operating the first period setting means. Provided is a drive device comprising a number-of-times control means for repeated operation.
[0077]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 4 shows a schematic cross-sectional view of the CL-LCD of the present invention. CL-LCD in which glass substrates 1A and 1B, electrodes 2A and 2B, polymer thin films 3A and 3B, liquid crystal composition 4 and black light absorber 5 are arranged on the back side, and stably display FC state and PL state It is.
[0078]
An inorganic thin film such as silica may be formed instead of the polymer thin films 3A and 3B. However, when the surface of the thin film in contact with the CL-LC is rubbed, the stability of the CL state of the CL-LC may be lost depending on the type of the thin film. Therefore, a thin film without rubbing is provided, or an electrode and a liquid crystal composition are provided in direct contact with each other.
[0079]
The gap between the electrodes is held by a spacer or the like, and preferably 2 to 15 μm. Furthermore, 3-6 micrometers is preferable. This is because if the electrode gap is too small, the display contrast ratio decreases, and if it is too large, the drive voltage increases.
[0080]
The display mode may be non-full dot matrix display such as segment display or dot matrix display. The substrate may be a glass substrate or a resin substrate, or a combination of a glass substrate and a resin substrate. When used as a reflective display element, a light absorber may be installed on the inner surface or the outer surface of one of the substrates, or a substrate having a light absorbing function may be used.
[0081]
A very small amount of spacer is dispersed in the electrode surface, the four sides of the opposed substrate are sealed with a sealing material such as epoxy resin except for the injection holes, and the liquid crystal composition is filled into the cell by vacuum injection.
[0082]
For the CL-LCD, in order to examine the applied voltage and the optical characteristics after voltage erasure, a voltage pulse was applied to the liquid crystal panel and then erased to repeat the experiment for confirming the display state. Each of the PL state and the FC state was used as a state before performing the voltage processing. 5, 6 and 7 are explanatory diagrams showing an outline of the experimental results. FIG. 5 shows an example of the relationship between the voltage amplitude and the reflectance when the reflectance is measured 10 seconds after the voltage pulse of 13.2 ms is applied and erased. In FIG. 5, rhombuses (♦) indicate the case where the initial state is the PL state, and squares (■) indicate the case where the initial state is the FC state. 6 and 7 show experimental results when the voltage pulse width is further shortened.
[0083]
From the experimental results, it can be seen that the PL state, which is a stable state with high reflectivity, can be realized by applying a voltage having an amplitude of 35 V or more regardless of the previous state. In other words, if pulse voltage processing is performed such that the voltage is sufficiently vertically aligned when a voltage is applied, it can be changed to the PL state by erasing the voltage. The FC state, which is a stable state with low reflectance, can be formed by a process of applying a voltage having an amplitude of 23V.
[0084]
That is, in the CL-LC used in the experiment, regardless of the initial state, the CL-LCD is brought into the PL state by applying a voltage having an amplitude of 35 V or more to the CL-LCD for 13.2 ms. Can do. The FC state, which is a stable state with low reflectance, can be formed by a process of applying a voltage having an amplitude of 23V. This makes it possible to reset in a short time, which was difficult with the prior art.
[0085]
In addition, when the voltage process corresponding to the HO state is performed according to the conditions obtained from the experimental results as shown in FIGS. 5 to 7 and the voltage process corresponding to the FC state is continuously performed, the first voltage process is performed. Sometimes the vertical alignment state is taken, but after the next voltage treatment, the predetermined FC state may not be obtained.
[0086]
Therefore, in this embodiment, after the process of applying a relatively high voltage, which is the first stage, is performed, a second stage in which no voltage is applied, that is, a potential difference of 0 V is provided. Thereafter, voltage processing (third stage) corresponding to the FC state is performed, and writing according to individual display data is performed. A period in which no voltage is applied, that is, a period in which the potential difference is 0 V (second stage period) is a time from the HO state to the HG state or a mixed state of the HG state and the PL state. Here, the potential difference 0 V may be a voltage pulse with a small voltage value that can effectively act as zero.
[0087]
In the voltage processing as described above, the state written before is completely erased by the first voltage processing. That is, the CL-LCD is in a vertical alignment state in which the alignment of the cholesteric liquid crystal is substantially parallel to the voltage application direction (concept including perfect parallelism). Then, the alignment state of the CL-LCD changes to the HG state or the mixed state of the HG state and the PL state in the period of the potential difference of 0 V in the first voltage processing. In addition, by the next voltage processing, the FC state or the mixed state of the FC state and the PL state is written.
[0088]
Further, when the application time is shortened in the next voltage processing (third stage) corresponding to writing to the FC state, a mixed state of the FC state and the PL state is obtained. After that, by writing individual display data, the display in the PL state is obtained from the mixed state when turned on, and the complete FC state is obtained from the mixed state when turned off. Therefore, even in that case, display with a high contrast ratio can be realized at high speed.
[0089]
That is, in the third stage, it is not necessary to apply a voltage amplitude that causes the CL-LCD to be sufficiently in the FC state, that is, the orientation state in which the selective reflection hardly remains. That is, a voltage having such an amplitude that the CL-LCD is in a mixed state of the PL state and the FC state may be applied. In other words, a lower voltage can be applied or the voltage application period can be shortened compared to a case where the FC state in which the selective reflection hardly remains is obtained.
[0090]
As described above, in the line-sequential driving period following the first to third stages described above, there is almost no residual selective reflection after the application voltage is applied when the display is turned off at the time of selection, that is, when the FC state is set. If the state can be achieved, a display with a good contrast ratio can be obtained.
[0091]
(Embodiment 1) Embodiment 1 of the present invention will be described below with reference to FIG. In this driving circuit, a frame signal (FR) as a control signal from the controller 11, a latch pulse signal (LP) for switching rows, an AC signal or an output inversion signal (M), and a / DOFF signal (/ DOFF) is input to the row driver 12. The column driver 13 receives an LP signal, a clock pulse signal (CP), an M signal, a / DOFF signal, and display data as control signals from the controller 11.
[0092]
The row driver 12 selects the first row when the FR signal becomes high level. The LP signal corresponds to a signal indicating that the selected row is shifted one row at a time. The M signal is a signal for alternating current. The CP signal is used as a clock for transferring display data from the controller 11 to the column driver 13. When the / DOFF signal becomes low level, the row driver 12 and the column driver 13 respectively set the voltage level applied to the CL-LCD 100 to a predetermined level (level V at the time of erasure).₀). When the / DOFF signal is at a high level, it is in a normal writing state.
[0093]
(Example 1-1) A polyimide thin film was formed by spinner coating on the surface of a glass substrate having a stripe-shaped transparent electrode in contact with the liquid crystal layer. Thereafter, resin spacers having a diameter of 4 μm were sprayed on the upper and lower substrate surfaces. Empty cells were formed by superimposing glass substrates on four sides excluding the injection holes so that the striped electrodes intersected with an epoxy resin printed with a width of about 0.4 mm.
[0094]
T_c= 87 ° C., Δn = 0.231, Δε = 16.5, Viscosity η = 32 mPa · s, Specific resistance 2 × 10¹¹84.7 parts of nematic liquid crystal of Ω · cm, 5.1 parts of a chiral agent shown in Chemical Formula 1, 5.1 parts of a chiral agent shown in Chemical Formula 2, 5.1 parts of a chiral agent shown in Chemical Formula 3, A chiral nematic liquid crystal (hereinafter referred to as “liquid crystal A”) having a helical pitch of about 0.34 μm was prepared.
[0095]
[Chemical 1]

[0096]
[Chemical formula 2]

[0097]
[Chemical 3]

[0098]
Liquid crystal A was injected into the empty cell by vacuum injection, and the injection hole was sealed with an ultraviolet curable material to prepare a liquid crystal panel. The number of electrodes is 240 rows of row electrodes and 320 lines of column electrodes, and the resolution is about 100 dpi. One substrate of the liquid crystal panel was uniformly painted by spraying a matte black paint.
[0099]
Next, one electrode is selected for each row and column of this liquid crystal panel, and a voltage of 40 V is applied to the intersection for 20 msec. When viewed from the side of the substrate not painted black after application, the intersection is reflected green. Colored. Next, when a voltage of 20 V was applied for 20 ms, the intersection portion was almost black when viewed from the side of the substrate that was not black-coated after application.
[0100]
In order to initialize the entire screen of the liquid crystal panel 10, a voltage of 40 V was applied to the entire panel for 13.2 ms at the start of the display sequence. Following that, a non-application time in which the voltage applied to the liquid crystal panel 10 was 0 was provided for 1 ms. Thereafter, a voltage of 23 V was applied to all the pixels for 3.3 ms as a voltage condition for setting the FC state. Then, line sequential driving was performed.
[0101]
A specific driving procedure will be described with reference to a timing chart of FIG. For example, the row driver 12 applies V to all the row electrodes._rAnd the column driver 13 applies V to all the column electrodes._cTo the state to apply. For example, V_rIs 35V, V_cIs −5V. Then, a voltage of 40 V is applied to all the pixels of the liquid crystal panel 10. In FIG. 9A, a period during which a voltage of 40 V is applied is shown as a reset unit. The reset unit corresponds to the first period.
[0102]
Thereafter, the non-application state where the applied voltage is 0 V is continued for 1 ms, and then a voltage of 23 V is applied to all the pixels for 3.3 msec. Specifically, the row driver 12 and the column driver 13_r-V_cApply a voltage of. In FIG. 9A, these periods are shown as a non-application part and a focal conic part. The non-application part corresponds to the second period, and the focal conic part corresponds to the third period.
[0103]
Subsequently, writing of display data, that is, line sequential driving starts. In line-sequential driving, the selected rows are switched in order, and a column voltage corresponding to display data is output to the column electrodes in synchronization with the selected rows. The drive voltage waveform is inverted in polarity at an appropriate period and converted into an alternating current. In the line-sequential drive period, when selected, V is displayed in the ON display (PL state)_r+ V_cIs applied, and in the off display (FC state), V_r-V_cIs applied.
[0104]
In this example, V_r35V, V_cWas 5V. In addition, the period during which the row electrode is selected once is set to 3.3 ms. In FIG. 9A, the line sequential driving period is shown as an addressing unit. A non-application portion may or may not be provided between the focal conic portion and the addressing portion. FIG. 9A illustrates the case where the non-application portion is provided.
[0105]
It was confirmed that the CL-LCD 100 was in the FC state in which some residual reflection remained due to a series of voltage processing before writing the display data. Further, by continuously performing display writing by line-sequential driving, a test pattern was displayed under the above conditions. As a result, a display with a high contrast ratio was obtained without an afterimage.
[0106]
(Example 1-2) Of the driving conditions of Example 1-1, a voltage of 40 V was applied to the entire CL-LCD 100 for 13.2 ms, followed by a non-application time of 0 ms where the applied voltage was 0 V. . In the next voltage processing period, that is, in the focal conic portion, the applied voltage was set to 24 V for 2.0 ms, line sequential driving was started, and a test pattern was displayed.
[0107]
Then, although the alignment state before the start of line-sequential driving is a mixed state of FC state and PL state, the display state by line-sequential driving has no afterimage and is slightly inferior to Example 1-1. The display state was high in contrast. Further, the time required for the display sequence can be shortened as compared with Example 1-1.
[0108]
As described above, in order to completely erase the previously written display state, all the pixels must be once vertically aligned. For this purpose, for example, a voltage of 40 V is applied to all the pixels of the CL-LCD 100 for a predetermined period (the reset unit in FIG. 9A). However, in practice, the application time may be set longer in order to reduce the applied voltage.
[0109]
From the results of this example, it can be seen that a display state with a relatively high contrast ratio can be obtained even if the focal conic portion, which is the third stage, is shortened. When the focal conic portion is shortened, the alignment state before the start of line-sequential driving is an insufficient FC state in which selective reflection in the PL state remains, that is, a mixed state of the FC state and the PL state. However, since the FC state is written as OFF display during line sequential driving, a relatively high contrast ratio can be obtained.
[0110]
Therefore, the voltage condition for setting the HO state is V₁(Reset voltage value) and τ₁(Reset period), the voltage condition for writing to the FC state is V₃(Voltage value of focal conic part) and τ₃(Focal Conic Club period)₁> V₃And τ₁> Τ₃It may be.
[0111]
(Comparative Example 1-1) In the driving conditions of Example 1-1, when the time of the non-applied portion was changed between 0 to 0.3 ms, the line sequential driving driving condition was changed in any way. The display with the same contrast ratio as 1-1 could not be obtained.
[0112]
(Comparative Example 1-2) τ₂Is τ_HIn the case of 20 ms, which is 40 times the value, flickering occurred during reset. In addition, the time required for initialization (reset) becomes relatively long. Such a required time greatly affects the configuration of one display sequence.
[0113]
(Example 1-3) Under the driving conditions of Example 1-1, when writing display data by line sequential driving, the column electrode application time is equally divided into 10 with respect to the selection period, and the gradation is divided into each divided period. A voltage corresponding to ON and OFF according to the data was applied to the column electrode. When the test pattern was displayed by such a voltage application method, uniform gradation display corresponding to the display data was obtained.
[0114]
(Comparative Example 1-3) Under the driving conditions of Example 1-1, when the applied voltage of the column electrode is on, V_c-V when off_cN · V according to the gradation data_cA voltage value of (−1 <n <1) was applied to the column electrode. Ten gradation display was performed by changing the voltage value. When various test patterns were displayed, display unevenness parallel to the column electrodes occurred, resulting in uneven gradation display.
[0115]
Therefore, when performing halftone display, it was found that good gradation display can be obtained if pulse width modulation is used, but good gradation display cannot be obtained if amplitude modulation is used. .
[0116]
Next, a driving circuit for driving the CL-LCD will be described. Drive drivers that realize line-sequential selection methods (for example, APT: Alto Pleshko Technique and improved APT: Improved APT), which are basic drive methods for simple matrix STN liquid crystal display elements, are widely used as dedicated ICs. Yes.
[0117]
An IAPT driving driver for driving a simple matrix type STN liquid crystal display element can apply a selection voltage to only one row electrode. Therefore, to make the initial state of the entire surface of the CL-LCD uniform to the FC state using it, it takes at least one frame period to transition to the HO state. Furthermore, it takes at least one frame period to transition to the FC state. However, in order to transition to the HO state in one frame period, it must be performed in one selection time at the time of addressing, so that a voltage higher than the ON voltage needs to be applied.
[0118]
To achieve this, a high voltage driver is required, which is difficult. Conversely, if a sufficient vertical alignment is to be obtained with an applied voltage equal to the ON voltage, one selection time must be lengthened, and the time required for initialization becomes longer than the writing time.
[0119]
That is, if the IAPT drive driver is applied to the CL-LCD as it is, the above-described voltage application processing (first stage to third stage) cannot be realized, and the time required for initialization is the time for selecting one screen. It becomes several times. That is, the time required for rewriting one screen including initialization becomes long. Therefore, the driving device of the present invention using an easy-to-use IAPT driving driver is proposed.
[0120]
10 and 11 are explanatory diagrams for explaining the function of the IAPT drive driver. As shown in FIG. 10, the column driver (COL-DRV) and the row driver (ROW-DRV) each require four levels of liquid crystal drive voltage, but the entire system requires six levels of voltage. Where V_rIs the voltage applied to the row electrode during selection and V_cIs ½ of the difference between the on-voltage and off-voltage applied to the row electrode.
[0121]
As shown in FIG. 11, the output voltage is determined by the row driver and the column driver in accordance with the polarity inversion signal (M signal) and the non-display instruction signal (/ DOFF signal) which are level signals. However, when the / DOFF signal is at low level, all outputs of the row driver and column driver are V₀Output level.
[0122]
FIG. 12 is a block diagram showing Embodiment 1-A of the drive device. In this case, a signal conversion circuit 14 is further provided for the general drive circuit shown in FIG. The signal conversion circuit 14 is installed between the controller 11 and the row driver 12 and the column driver 13, and based on each signal from the controller 11, the first stage (reset unit) and the second stage (no application). Part) and a third stage (focal conic part) are generated and supplied to the row driver 12 and the column driver 13.
[0123]
Here, the signal conversion circuit 14 is described as being independent of the signal control circuit 11, but they may be integrated. When they are integrated, the signal timing can be optimized, and the time required for initialization can be shortened.
[0124]
Further, the M signal is a polarity inversion signal created by the signal conversion circuit 14, and DATA is display data created by the signal conversion circuit 14. DATA is the same as the display data output from the signal control circuit 11 in the addressing unit. The / DOFF1 signal is a / DOFF signal created by the signal conversion circuit 14 and supplied to the column driver 13, and the / DOFF2 signal is a / DOFF signal created by the signal conversion circuit 14 and supplied to the row driver 12.
[0125]
A memory-type CL-LCD maintains its display state once data is written, so it is not necessary to perform writing every frame period, but it is necessary to instruct the timing at which data rewriting is required from the outside. A signal for this purpose is a start signal (START) shown in FIG. The START signal may be a signal that is generated by a timer and becomes valid every certain period, or may be a display rewrite instruction signal from an MPU that is a display data generation source or an external switch. FIG. 12 shows an example output from the MPU.
[0126]
FIG. 13 is a block diagram illustrating a configuration example of the signal conversion circuit 14 according to Embodiment 1-A. In the signal conversion circuit 14 shown in FIG. 13, the 0.5 line detection circuit 21 determines the timing of ½ of the selection period using the LP signal as a trigger, and outputs a signal whose level is inverted at the timing to the OR circuit. 22 for output. The down counter 24 is a counter that presets (N−1) when the FR signal is input, and decrements the count value by 1 in accordance with the input of the LP signal. Here, N is the number of display lines. First to fifth comparators (hereinafter referred to as comparators) 25, 26, 27, 28, and 29 respectively compare the count value of the down counter 24 with a predetermined value.
[0127]
If the mask signal from the DOFF control circuit 31 is in a low level state, the OR circuit 22 outputs the output signal of the 0.5 line detection circuit 21 to the row driver 12 and the column driver 13 as an M signal, and the mask signal is In the high level state, a high level M signal is output to the row driver 12 and the column driver 13.
[0128]
The selector 23 also outputs display data, high level data, or low level data from the signal control circuit 11 to the column driver 13 as a DATA signal according to the state of the selection signal.
[0129]
The start flag circuit 30 synchronizes the START signal with the FR signal and sets the start flag. The DOFF control circuit 31 is notified that the start flag has been set. Further, the start flag is reset according to an instruction from the DOFF control circuit 31. The DOFF control circuit 31 functions in a state where the start flag is set. Then, the / DOFF1 signal is given to the column driver 13 and the / DOFF2 signal is given to the row driver 12 in accordance with the output status of the comparators 25, 26, 27, 28, and 29. Further, a mask signal is given to the OR circuit 22 and a selection signal is given to the selector 23.
[0130]
Next, the operation will be described with reference to the timing chart of FIG. The comparators 25, 26, 27, and 29 are configured such that the time length of the reset unit (first stage) is A, the time length of the non-application part (second stage) is B, and the time length of the focal conic part (third stage). It is provided to set the time length to C. Each of the comparators 25 to 29 introduces the count value of the down counter 24 that counts down the LP signal, compares the count value with a predetermined value, and outputs a coincidence signal when they match.
[0131]
In this embodiment, the first period setting means for setting the time length A of the reset unit is realized by the down counter 24 and the comparators 25 and 26. The second period setting means for setting the time length B of the non-application part is realized by the down counter 24 and the comparators 26 and 27. The third period setting means for setting the time length C of the focal conic part is realized by the down counter 24 and the comparators 27 and 29. The voltage applying means for applying a predetermined voltage in the first to third stages is realized by the OR circuit 22, the selector 23, and the DOFF control circuit 31.
[0132]
The predetermined value for comparison by the comparator 25 is (A + B + C), and the predetermined value for comparison by the comparator 26 is (A + B). The predetermined value for comparison by the comparator 27 is B, and the predetermined value for comparison by the comparator 28 is 1. The predetermined value for comparison by the comparator 29 is zero. Note that A + B + C <N (N is the number of display rows).
[0133]
In the state where the start flag is not set, the DOFF control circuit 31 sets all the column electrodes and row electrodes to the potential V.₀The non-display instruction signals (/ DOFF1 signal and / DOFF2 signal) for the column driver 13 and the row driver 12 are fixed at a low level so that the non-application state is.
[0134]
Therefore, the CL-LCD 100 is in a voltage non-application state regardless of the signal state from the signal control circuit 11. Further, in order to fix the M signal and the DATA signal at high level, the mask signal to the OR circuit 22 is fixed at high level, and the selection signal to the selector 23 is selected to be high level (“1”). Set to. When the FR signal is input after the START signal is input, the start flag circuit 30 sets a start flag. The FR signal is input every frame period.
[0135]
When the FR signal is input, (N−1) is preset in the down counter 24. Thereafter, the down counter 24 counts down using a row switching signal (LP signal) as a trigger. The comparator 25 outputs a coincidence signal to the DOFF control circuit 31 when the count value of the down counter 24 coincides with (A + B + C). The DOFF control circuit 31 receives a coincidence signal from the comparator 25 when both the / DOFF1 signal and the / DOFF2 signal are at a low level. Further, when the LP signal is input, / DOFF1 to the column driver 13 is received. Fix the signal to high level.
[0136]
As a result, based on the relationship shown in FIG.₅(V_r+ V_c) In addition, the voltage level of all the row electrodes is V₀Therefore, the liquid crystal applied voltage for all pixels is V_r+ V_cIt becomes. For example, V_r= 35V, V_cIf = 5V, the liquid crystal applied voltage is 40V.
[0137]
The comparator 26 outputs a coincidence signal to the DOFF control circuit 31 when the count value of the down counter 24 coincides with (B + C). The DOFF control circuit 31 receives the coincidence signal from the comparator 26 when the / DOFF1 signal is at a high level and the / DOFF2 signal is at a low level. Further, when the LP signal is input, the / DOFF1 signal to the column driver 13 is fixed to the low level. As a result, on the basis of the relationship shown in FIG.
[0138]
At this time, the DOFF control circuit 31 sets the selection signal to the selector 23 so that the low level (“0”) is selected.
[0139]
Liquid crystal applied voltage is V_r+ V_cThe period from when the voltage changes to when no voltage is applied is the period during which the count value of the down counter 24 advances "A", and this period is the reset unit as shown in FIG.
[0140]
The comparator 27 outputs a coincidence signal to the DOFF control circuit 31 when the count value of the down counter 24 coincides with C. The DOFF control circuit 31 receives the coincidence signal from the comparator 27 when both the / DOFF1 signal and the / DOFF2 signal are at a low level.
[0141]
Further, when the LP signal is input, the / DOFF1 signal to the column driver 13 is fixed to the high level. As a result, based on the relationship shown in FIG.₃(V_r-V_c) In addition, the voltage level of all the row electrodes is V₀Therefore, the liquid crystal applied voltage for all pixels is V_r-V_cIt becomes. For example, V_r= 35V, V_cIf = 5V, the liquid crystal applied voltage is 30V.
[0142]
From the time when the liquid crystal applied voltage changes to the state in which no voltage is applied, V_r-V_cA period until the count value reaches “B” is a period during which the count value of the down counter 24 advances “B”, and as shown in FIG.
[0143]
The comparator 28 outputs a coincidence signal to the DOFF control circuit 31 when the count value of the down counter 24 coincides with 1. The DOFF control circuit 31 receives the coincidence signal from the comparator 28 when the / DOFF1 signal is at a high level and the / DOFF2 signal is at a low level. Further, when the LP signal is input, the selection signal to the selector 23 is changed so as to select display data as the DATA signal.
[0144]
The comparator 29 outputs a coincidence signal to the DOFF control circuit 31 when the count value of the down counter 24 coincides with 0. The DOFF control circuit 31 receives the coincidence signal from the comparator 29 when the / DOFF1 signal is at a high level and the / DOFF2 signal is at a low level. 13 and the / DOFF1 signal and / DOFF2 signal to the row driver 12 are fixed to a high level.
[0145]
Further, the mask signal to the OR circuit 22 is fixed at a low level so that the output of the 0.5 line detection circuit 21 becomes an M signal. Therefore, an addressing unit that starts display in accordance with the DATA signal and the M signal by line sequential driving is started. At this time, the ON voltage is V_r+ V_c, OFF voltage is V_r-V_cIt becomes.
[0146]
Liquid crystal applied voltage is V_r-V_cThe period until the voltage corresponding to on / off from the time when the value changes to is the period during which the count value of the down counter 24 advances by “C”. As shown in FIG. Become.
[0147]
Further, when a coincidence signal is output from the comparator 29 in a state where both the / DOFF1 signal and the / DOFF2 signal which are non-display instruction signals to the column driver 13 and the row driver 12 are at a high level, the DOFF control circuit 31 Resets the start flag and fixes both the / DOFF1 signal and the / DOFF2 signal to low level, and sets the liquid crystal application voltage to all the pixels to 0V.
[0148]
Therefore, the CL-LCD remains in a state where the writing state is stored. Further, the mask signal to the OR circuit 22 is fixed at a high level, and the selection signal is switched so that the output of the selector 23 is fixed at a high level. The state is maintained until the next START signal is input.
[0149]
As described above, in the embodiment 1-A, by using the M signal and the / DOFF signal that can be handled by the conventional driving device, the first stage to the third stage, that is, the reset unit, no mark Create an additional part (or standby part) and a focal conic part. Therefore, the IAPT drive driver can be applied to the present invention.
[0150]
Next, FIG. 15 shows a configuration of the embodiment 1-B. In the embodiment 1-B, the signal conversion circuit 14 also outputs a SEL signal that is a voltage switching instruction signal. Further, a power supply device 15 and a switch circuit 16 are provided. The power supply device 15 can supply a VLCD 2 having an arbitrary voltage level in addition to the VLCD 1 that is a normal voltage for driving the liquid crystal display panel. In the embodiment 1-B, the power supply device 15 and the switch circuit 16 are also part of voltage application means for applying a predetermined voltage in the first to third stages.
[0151]
The VLCD 1 has an on-voltage V during normal writing.₅(V_r+ V_c). VLCD2 is also V₅(V_r+ V_c), But a value different from VLCD1. For example, the voltage value is such that VLCD2 is 24V when VLCD1 is 40V. In response to the SEL signal from the signal conversion circuit 14, the switch circuit 16 supplies one of VLCD 1 and VLCD 2 by dividing the voltage level necessary for the row driver 12 and the column driver 13.
[0152]
FIG. 16 is a block diagram illustrating a configuration example of the signal conversion circuit 14 according to Embodiment 1-B. In the signal conversion circuit 14 shown in FIG. 16, the 0.5 line detection circuit 21, the OR circuit 22, the down counter 24, the comparators 25 to 29, and the start flag circuit 30 are the same as those in the embodiment 1-A. Operate. In the DOFF control circuit 31, control of the SEL signal that instructs switching of the power supply voltage is added. Further, the selector 23 used in the embodiment 1-A is changed, and an OR circuit 23A is provided.
[0153]
Next, the operation will be described with reference to the timing chart of FIG. In the state where the start flag is not set, the DOFF control circuit 31 sets all the column electrodes and row electrodes to the potential V.₀The non-display instruction signals (/ DOFF1 signal and / DOFF2 signal) for the column driver 13 and the row driver 12 are fixed at a low level so that the non-application state is.
[0154]
Therefore, the CL-LCD 10 is in a voltage non-application state regardless of the signal state from the signal control circuit 11. Further, in order to fix the M signal and the DATA signal at a high level, the mask signal to the OR circuit 22 and the mask signal to the OR circuit 23A are fixed to a high level. When the FR signal is input after the START signal is input, the start flag circuit 30 sets a start flag. The FR signal is input every frame period.
[0155]
When the FR signal is input, (N−1) is preset in the down counter 24. Thereafter, the down counter 24 counts down the row switching signal (LP signal). The comparator 25 outputs a coincidence signal to the DOFF control circuit 31 when the count value of the down counter 24 coincides with (A + B + C).
[0156]
The DOFF control circuit 31 receives a coincidence signal from the comparator 25 when both the / DOFF1 signal and the / DOFF2 signal are at a low level. Further, when the LP signal is input, / DOFF1 to the column driver 13 is received. Fix the signal to high level.
[0157]
As a result, based on the relationship shown in FIG.₅(V_r+ V_c) In addition, the voltage level of all the row electrodes is V₀Therefore, the liquid crystal applied voltage for all pixels is V_r+ V_cIt becomes. For example, V_r= 35V, V_cIf = 5V, the liquid crystal applied voltage is 40V.
[0158]
The comparator 26 outputs a coincidence signal to the DOFF control circuit 31 when the count value of the down counter 24 coincides with (B + C). The DOFF control circuit 31 receives the coincidence signal from the comparator 26 when the / DOFF1 signal is at a high level and the / DOFF2 signal is at a low level.
[0159]
Further, when the LP signal is input, the / DOFF1 signal to the column driver 13 is fixed to the low level. As a result, based on the relationship shown in FIG.
[0160]
Liquid crystal applied voltage is V_r+ V_cThe period from when the voltage is changed to the time when no voltage is applied is a period during which the count value of the down counter 24 advances "A", and this period is a reset unit as shown in FIG.
[0161]
The comparator 27 outputs a coincidence signal to the DOFF control circuit 31 when the count value of the down counter 24 coincides with C. The DOFF control circuit 31 receives a coincidence signal from the comparator 27 when both the / DOFF1 signal and the / DOFF2 signal are at a low level. Further, when the LP signal is input, the DOFF control circuit 31 supplies / DOFF1 to the column driver 13. Fix the signal to high level.
[0162]
Further, the SEL signal is fixed at a high level. The switch circuit 16 shown in FIG. 15 enters a state in which the VLCD 2 from the power supply device 15 is selected and supplied to the row driver 12 and the column driver 13 in response to the SEL signal becoming high level.
[0163]
As a result, based on the relationship shown in FIG.₅(V_r+ V_c) In addition, the voltage level of all the row electrodes is V₀Therefore, the liquid crystal applied voltage for all pixels is V_r+ V_cIt becomes. However, at this stage, since the SEL signal is at a high level, the liquid crystal applied voltage is VLCD2, and the normal V used for the reset unit and line sequential drive is used._r+ V_cDifferent from (= VLCD1). For example, V_r+ V_c= 24V.
[0164]
The period from when the liquid crystal applied voltage changes to the voltage non-applied state until the supply of the VLCD 2 starts is a period during which the count value of the down counter 24 advances by “B”. As shown in FIG. Becomes a non-application part.
[0165]
The comparator 28 outputs a coincidence signal to the DOFF control circuit 31 when the count value of the down counter 24 coincides with 1. The DOFF control circuit 31 receives the coincidence signal from the comparator 28 when the / DOFF1 signal is at the high level and the / DOFF2 signal is at the low level, and further, when the LP signal is input, The mask signal to the circuit 23A is fixed at a low level, and display data is output as a DATA signal.
[0166]
The comparator 29 outputs a coincidence signal to the DOFF control circuit 31 when the count value of the down counter 24 coincides with 0. The DOFF control circuit 31 receives the coincidence signal from the comparator 29 when the / DOFF1 signal is at a high level and the / DOFF2 signal is at a low level.
[0167]
Further, when the LP signal is input, the / DOFF1 signal and the / DOFF2 signal to the column driver 13 and the row driver 12 are fixed to a high level. Then, the SEL signal is returned to the low level. As a result, the row driver 12 and the column driver 13 are returned to the state in which the VLCD 1 is supplied from the power supply device 15. Further, the mask signal to the OR circuit 22 is fixed at a low level so that the output of the 0.5 line detection circuit 21 becomes an M signal. Therefore, an addressing unit that starts display in accordance with the DATA signal and the M signal by line sequential driving is started. At this time, the ON voltage is V_r+ V_c, OFF voltage is V_r-V_cIt becomes.
[0168]
The period from when the liquid crystal applied voltage changes to the voltage based on VLCD 2 until the voltage corresponding to the normal ON / OFF is the period during which the count value of the down counter 24 advances by “C”, as shown in FIG. Thus, this period becomes the focal conic part.
[0169]
Further, when a coincidence signal is output from the comparator 29 in a state where both the / DOFF1 signal and the / DOFF2 signal which are non-display instruction signals to the column driver 13 and the row driver 12 are at a high level, the DOFF control circuit 31 Resets the start flag and fixes both the / DOFF1 signal and the / DOFF2 signal to low level, and sets the liquid crystal application voltage to all the pixels to 0V. Therefore, the CL-LCD remains in a state where the writing state is stored.
[0170]
Further, the mask signal to the OR circuit 22 and the mask signal to the OR circuit 23A are fixed at a high level, and the M signal and the DATA signal are fixed at a high level. The state is maintained until the next START signal is input.
[0171]
As described above, even in Embodiment 1-B, the reset unit, the non-application unit, and the focal conic unit can be created by using the M signal and the / DOFF signal that can be handled by the conventional driving device. . Therefore, the IAPT drive driver can be applied to the present invention.
[0172]
Moreover, in Embodiment 1-B, the voltage amplitude in the focal conic part can be set arbitrarily, so that the optimum voltage value required for the focal conic part can be used. Note that the voltage amplitude in the reset unit may be set to an arbitrary value.
[0173]
In each of the above embodiments, the length of the first to third stages is set using the LP signal. However, the length of the first to third stages is set based on a clock signal other than the LP signal. It may be set. In that case, the time required for initialization can be further shortened by using a higher frequency clock signal.
[0174]
Further, in each of the above embodiments, a positive pulse voltage is applied to the CL-LC in the first stage (reset section) and the third stage (focal conic section). A positive pulse and a negative pulse having the same absolute value of the voltage amplitude may be applied.
[0175]
(Embodiment 2) Next, Embodiment 2-A using a pulse width modulation system will be described. FIG. 19 is an explanatory diagram showing the experimental results. With an application time of 1 ms, the CL-LC can be brought into an almost complete FC state by applying the voltage about 5 times. However, in order to realize the same state with only one voltage application, an application time of 10 ms is required. As described above, it is understood that the total time for realizing the FC state can be reduced by applying the voltage many times in a short application time, rather than realizing the FC state by one voltage application. .
[0176]
That is, in the preparation period for writing the display data, after applying a voltage to make CL state temporarily to the HO state and resetting the previous display state, a state in which no voltage is applied, that is, a period in which the potential difference is 0V is set. Provide. Further, a voltage pulse that causes the CL-LC to be in a mixed state of the FC state and the PL state is intermittently applied in a short application time. With this method, CL-LC is preferably brought into an FC state in which selective reflection hardly remains or a mixed state of the FC state and the PL state, and voltage writing corresponding to display data is performed in that state.
[0177]
According to such a driving method, the time required for a sequence for updating a series of images can be further shortened. Further, CL-LC shifts to the HG state or the mixed state of the HG state and the PL state in the period of the potential difference of 0 V, so that the reset time can be efficiently shortened.
[0178]
Furthermore, since the initial state is set to the FC state or the mixed state of the FC state and the PL state, all pixels are temporarily reflected in the PL state, so that no flicker occurs at the time of reset.
[0179]
As shown in FIGS. 5 to 7, when the application time is shortened, the optimum voltage at which the FC state is written increases. Therefore, the applied voltage for vertical alignment is V₁, Application time τ₁The applied voltage per time for writing the FC state or the mixed state of the FC state and the PL state is V₃, Apply time τ₃When V₃And τ₃If you choose properly, τ₁> Τ₃V₁And V₃Can be shared. Therefore, the circuit configuration of the drive driver can be simplified.
[0180]
FIG. 20 is a block diagram illustrating a configuration example of the controller 11 according to Embodiment 2-A. The oscillator 33 generates a clock signal (CLK) having a predetermined frequency. The reference counter 34 receives CLK and counts it. When the count value of the reference counter 34 reaches a predetermined value, the line counter 35 increments the value by +1. The comparator 36 includes a count value (DOT) of the reference counter 34, a count value (LINE) of the line counter 35, and a set value (N₁~ N₅) To generate a CP signal, an M signal, an LP signal, a / DOFF1 signal, a / DOFF2 signal, and a SEL signal. The SEL signal is output to the selector 39.
[0181]
The memory 38 stores display data from the MPU 20. The selector 39 selects one of the data in the memory 38, the “1” fixed signal, and the “0” fixed signal according to the SEL signal, and outputs the selected data to the CL-LCD as a DATA signal.
[0182]
A setting value for setting the voltage application time is written from the MPU 20 to the setting register 37. Each time is a value converted by the number of clocks output from the oscillator 33. Here, the high voltage application time (first stage period) for vertical alignment is represented by N₁, The time of the non-applied part (second stage period) is N₂, The voltage application time for transition to the FC state (the period of the third stage) is N₃, N₂And N₃The number of repetitions with N₄, 1 selection time in line sequential driving is N₅And
[0183]
Once the data is written into the CL-LCD, the display state is maintained, so it is not necessary to perform writing every frame period, but it is necessary to notify the timing at which data rewriting is required from the outside. For this purpose, the MPU instructs the setting register 37 to rewrite the display. When a display rewrite instruction is set in the setting register 37, a START signal is output to the comparator 36.
[0184]
In Embodiment 2-A, the first period setting means for setting the high voltage application period for vertical alignment, the second period setting means for setting the time of the non-application portion, and the FC The third period setting means for setting the voltage application time for the transition to the state is realized by the reference counter 34, the line counter 35, the setting register 37, and the comparator 36. Voltage application means for applying a predetermined voltage in the first to third stages is realized by the memory 38, the selector 39, and the comparator 36. The number of times control means for repeating the second stage and the third stage is realized by the setting register 37 and the comparator 36.
[0185]
Next, the operation will be described with reference to the timing chart of FIG. Here, N₄= 2 and the on-voltage in line sequential driving is V_r+ V_c, Turn off voltage V_r-V_cAnd
[0186]
The controller 11 is in an initial state until a display start is instructed from the MPU 20. That is, the CP signal is maintained at a low level, the LP signal is maintained at a low level, the M signal is maintained at a high level, the DATA is maintained at a high level, and the / DOFF1 signal and the / DOFF2 signal are maintained at a low level. Since both the / DOFF1 signal and the / DOFF2 signal are at a low level, all the row electrodes and column electrodes are at the potential V₀The liquid crystal is not applied. Further, both the reference counter 34 and the line counter 35 hold 0.
[0187]
When the display start is instructed from the MPU 20, the START flag is set in the setting register 37, and the START signal becomes high level. When the START signal becomes high level, the comparator 36 puts the reference counter 34 into an operating state. The reference counter 34 increases the count value by 1 according to the clock (CLK) from the oscillator 33. When the value of the line counter 35 is 0, the reference counter 34 has a value of N₅Counts up until it matches.
[0188]
The comparator 36 sets the CP signal to the high level when the count value of the reference counter 34 is an even number, and sets the CP signal to the low level when the count value is an odd number, and outputs the CP signal by the number of pulses suitable for the number of dots of the display element. . During this time, since DATA is at a high level, the values of the internal registers of the column driver 13 are all at a high level.
[0189]
The count value of the reference counter 34 is N₅If it matches, the comparator 36 sets the CNT signal to the high level for one clock period. In response to the CNT signal, the reference counter 34 returns the value to 0, and the line counter 35 increments the value by 1. At this time, the LP signal is set to the high level for one clock period. Therefore, the value of the internal register of the column driver 13 is reflected in the output of the column driver 13.
[0190]
When the value of the line counter 35 becomes 1, the comparator 36 sets the / DOFF2 signal to the high level. From the relationship shown in FIG. 11, the voltage levels of all the column electrodes are V₅(V_r+ V_c) In addition, the voltage level of all the row electrodes is V₀Therefore, the liquid crystal applied voltage for all pixels is V_r+ V_cIt becomes. That is, a voltage necessary for the vertical alignment of the liquid crystal is applied to the entire display surface.
[0191]
The comparator 36 outputs a SEL signal that fixes DATA to a low level. The selector 39 selects “0” according to such a SEL signal. Then, the comparator 36 sequentially outputs the CP signal to set all the values of the internal registers of the column driver 13 to the low level. The reference counter 34 has a count value of N₁Counts up until it matches, and the count value is N₁If it matches, the count value is reset to zero. At this time, the value of the line counter 35 is incremented by 1 and becomes 2.
[0192]
The value of the line counter 35 is 2n (1 ≦ n ≦ N₄), The comparator 36 sets the / DOFF2 signal to the low level and sets all the output potentials of the column driver 13 to V.₀To. Therefore, the liquid crystal applied voltage is 0V. The reference counter 34 has a count value of N₂Counts up until it matches. And the count value is N₂If the two match, the count value of the reference counter 34 is reset to 0, and the value of the line counter 35 is incremented by one. When the value of the line counter 35 changes from 2 to 3, the comparator 36 sets the LP signal to the high level for one clock period. As a result, the value of the internal register of the column driver 13 is reflected in the output of the column driver 13.
[0193]
The value of the line counter 35 is 2n + 1 (1 ≦ n ≦ N₄), The comparator 36 sets the / DOFF2 signal to the high level. At this time, since the M signal is at a high level and DATA latched in the column driver 13 is at a low level, the applied voltage to all the column electrodes is V based on the relationship shown in FIG.₃The liquid crystal applied voltage for all pixels is V₃(V_r-V_c) Therefore, a voltage necessary for forming the FC state is applied to the entire surface. The reference counter 34 has a count value of N₃Counts up until it matches, and the count value is N₃If the value matches, the count value of the reference counter 34 returns to 0, and the value of the line counter 35 is incremented by one.
[0194]
When the value of the line counter 35 is 2n + 1, the value is (2.N₄When +1), the comparator 36 outputs a SEL signal for selecting display data from the memory 38 as DATA. The selector 39 enters a state of selecting display data from the memory 38 in accordance with such a SEL signal. The comparator 36 sequentially outputs CP signals and puts display data into the internal register of the column driver 13.
[0195]
The reference counter 34 has a count value of N₃Counts up until it matches, and the count value is N₃If the value matches, the count value of the reference counter 34 returns to 0, and the value of the line counter 35 is incremented by one. In this example, the value of the line counter 35 at this stage is 6. The comparator 36 sets the LP signal to the high level for one clock period, and reflects the value of the internal register of the column driver 13 in the output of the column driver 13. Further, the FR signal is set to a high level for a certain period so as to include the LP signal pulse, and the row driver 12 is instructed to scan from the first row.
[0196]
The line counter value is (2.N₄If it exceeds +1), the comparator 36 fixes the / DOFF1 signal and the / DOFF2 signal to high level. Therefore, a voltage necessary for line sequential driving is output as the output of the column driver 12 and the row driver 13. In FIG. 10, this period is shown as an addressing unit.
[0197]
The comparator 36 is configured such that the count value of the reference counter 34 is (N₅/ 2) is smaller, the M signal is set to low level and (N₅/ 2) If it is above, it is set to the high level, and the liquid crystal applied voltage at the time of line sequential driving is changed to AC. In addition, the display data of the memory 38 is output as DATA for the next selected row. DATA is taken into the internal register of the column driver 13 by the CP signal.
[0198]
The reference counter 34 has a count value of N₅Counts up until it matches, N₅If the two match, the count value of the reference counter 34 is reset to 0, and the value of the line counter 35 is incremented by one. Each time the value of the line counter 35 is incremented by one, the comparator 36 outputs an LP signal to instruct the row driver 12 to scan the next row and to the column driver 13 for the next display. Directs data output.
[0199]
The value of the line counter 35 is (2.N₄+ 1 + number of display rows), the comparator 36 sets the CP signal and the LP signal to low level, instructs the selector 39 to output “1” DATA by the SEL signal, and sets the M signal to high level. Then, the count value of the reference counter 34 is N₅If the two coincide with each other, the CLR signal is set to the high level for one clock period, and the reference counter 34 and the line counter 35 are cleared to zero. Further, the / DOFF1 signal and the / DOFF2 signal are set to the low level, the liquid crystal application voltage is set to 0 V, the START flag is cleared, and the initial state is restored.
[0200]
As described above, in Example 2-1, by using the M signal and the / DOFF signal, the first stage to the third stage, that is, the reset unit, the non-application unit, and the focal conic promotion unit ( A state that promotes transition to the FC state). Therefore, the IAPT drive driver can be applied to the present invention.
[0201]
Then, the non-applied part and the focal conic promoting part are repeated several times (N₄Repeat). Therefore, the CL-LCD 10 can be initialized to a sufficient FC state in a shorter time than when the FC state is realized with one pulse. Here, N₄= 2 but with the configuration shown in FIG.₄Initialization can be performed with any value of.
[0202]
Next, Embodiment 2-B of the invention will be described with reference to the timing chart of FIG. The configuration of the controller 11 may be the same as the configuration (Embodiment 2-A) shown in FIG.
[0203]
In Embodiment 2-B, when the value of the line counter 35 becomes 1, the comparator 36 sets the / DOFF2 signal to a high level, and the comparator 36 outputs a SEL signal that fixes DATA to a low level. . However, the comparator 36 does not output a CP signal. Therefore, the value of the internal register of the column driver 13 remains at a high level. The reference counter 34 has a count value of N₁Counts up until it matches, and the count value is N₁If it matches, the count value is reset to zero. At this time, the value of the line counter 35 is incremented by 1 and becomes 2.
[0204]
In the embodiment 2-B, the value of the line counter 35 is 2n + 1 (1 ≦ n ≦ N₄), The comparator 36 sets the / DOFF2 signal to the high level. At this time, the M signal is at the high level, and all the data latched in the column driver 13 are at the high level. 11 is based on the relationship shown in FIG.₅The liquid crystal applied voltage is V₅(V_r+ V_c)
[0205]
The operation at other stages is the same as that of the embodiment 2-A. In the embodiment 2-B, the same voltage is applied to the CL-LCD 10 in the first stage and the third stage. That is, the applied voltage value for orienting the CL-LC to the HO state and the applied voltage value for bringing the FC state to the FC state could be shared.
[0206]
Example 2-1 A liquid crystal panel was formed in the same manner as in Example 1-1. Next, one electrode is selected for each row and column of this liquid crystal panel, and a voltage of 40 V is applied to the intersection for 20 ms. When viewed from the side of the substrate not painted black after application, the intersection is reflected in green. Colored. Next, when a voltage of 20 V was applied for 20 ms, the intersection portion was almost black when viewed from the side of the substrate that was not black-coated after application.
[0207]
In order to initialize the entire screen of the liquid crystal panel, a voltage of 45 V was applied to the entire display surface for 5 ms. Subsequently, a non-applied portion where the voltage applied to the liquid crystal panel was 0 V was provided for 0.3 ms. Thereafter, a voltage of 33 V was applied for 1 ms as a voltage for setting the FC state. After repeating the non-application portion and the voltage application period for setting the FC state five times in total, line-sequential driving was performed.
[0208]
The period during which the row electrode is selected is 0.1 ms. In the 0.3 ms no-voltage application section, the CL-LC shifts to the HG state or the mixed state of the HG state and the PL state, so that the reset time can be efficiently shortened.
[0209]
Then, the FC state was sufficiently written by a series of voltage processing before writing display data, and a display with a high contrast ratio was obtained. That is, when the test pattern was displayed, a display with a high contrast ratio was obtained without an afterimage. The time required for a series of display writing operations was 17.5 ms.
[0210]
(Comparative Example 2-1) As in the case of Example 2-1, a voltage of 45 V was applied to the entire panel for 5 ms in order to initialize the entire screen. Subsequently, a non-applied portion where the voltage applied to the liquid crystal panel was 0 V was provided for 0.3 ms. Thereafter, a voltage of 23 V was applied for 10 ms as a voltage for setting the FC state, and then line sequential driving was performed. The period during which the row electrode is selected is 0.1 ms.
[0211]
When the test pattern was displayed, a high-contrast display was obtained with no afterimage, but the time required for a series of display writing operations was 21.3 ms, which was longer than in Example 2-1.
[0212]
(Example 2-2) As in the case of Example 2-1, in order to initialize the entire screen, a voltage of 45 V was applied to the entire panel for 5 ms. Subsequently, a non-applied portion where the voltage applied to the liquid crystal panel was 0 V was provided for 0.3 ms. Thereafter, a voltage of 45 V was applied for 0.3 ms as a voltage for setting the FC state. After repeating the non-application portion and the voltage application period for setting the FC state eight times in total, line sequential driving was performed. The period during which the row electrode is selected is 0.1 ms.
[0213]
When the test pattern was displayed, a high contrast ratio display was obtained with no afterimage, but the time required for a series of display writing operations was 15.8 ms, and the required time could be further improved. In addition, among the steps for initializing the entire screen, the voltage condition for vertical alignment, that is, 45 V, 5 ms could be shared.
[0214]
This is advantageous when the drive circuit is put to practical use because the voltage level of the power supply circuit can be reduced. In addition, the number of repetitions of the non-applied portion and the voltage application period for setting the FC state is preferably about 10 times or less.
[0215]
(Comparative Example 2-2) As in the case of Example 2-2, in order to initialize the entire screen, a voltage of 45 V was applied to the entire panel for 5 ms. Subsequently, a non-applied portion where the voltage applied to the liquid crystal panel was 0 V was provided for 0.3 ms. Thereafter, a voltage of 45 V was applied for 10 ms as a voltage for setting the FC state, and then line sequential driving was performed.
[0216]
The period during which the row electrode is selected is 0.1 ms. When the test pattern was displayed, a high contrast ratio display was obtained without an afterimage, but the time required for a series of display writing operations was 21.3 ms, which was longer than in Example 2-2.
[0217]
(Example 2-3) Under the driving conditions of Example 2-1, when display data is written by line-sequential driving, the column electrode application time is equally divided by 10 with respect to the selection period, and the gradation is divided into each divided period. A voltage corresponding to ON and OFF according to data is applied to the column electrode. When the test pattern was displayed by such a voltage application method, uniform gradation display corresponding to the display data was obtained.
[0218]
(Comparative Example 2-3) Under the driving conditions of Example 2-1, when the applied voltage of the column electrode is on, V_c-V when off_cN · V according to the gradation data_cA voltage value of (−1 <n <1) was applied to the column electrode. Ten gradation display was performed by changing the voltage value. When various test patterns were displayed, display unevenness parallel to the column electrodes occurred, resulting in uneven gradation display.
[0219]
In the case of halftone display, good gradation display can be obtained by using pulse width modulation. However, good gradation display cannot be obtained when amplitude modulation is used.
[0220]
(Embodiment 3) Next, Embodiment 3 of the present invention capable of driving in a wider temperature range will be described. FIG. 23 is a block diagram showing an embodiment of the driving device. The FR signal, LP signal, M signal, and / DOFF1 signal are input from the controller 11 to the row driver 12 as control signals. The column driver 13 receives the LP signal, CP signal, M signal, / DOFF2 signal and display data (DATA) from the controller 11. The / DOFF1 signal is a / DOFF signal created by the controller 11 and supplied to the column driver 13, and the / DOFF2 signal is a / DOFF signal created by the controller 11 and supplied to the row driver 12. The row driver 12 and the column driver 13 are supplied with necessary voltages from the power supply device 14.
[0221]
The row driver 12 selects the first row when the FR signal becomes high level. The LP signal corresponds to a signal indicating that the selected row is shifted one row at a time. The M signal is a signal for alternating current. The CP signal is used as a clock for transferring display data from the controller 11 to the column driver 13. When the / DOFF signal becomes low level, the row driver 12 and the column driver 13 set the voltage level applied to the liquid crystal panel 10 to a predetermined level (level V at the time of erasure).₀). When the / DOFF signal is at a high level, it is in a normal writing state.
[0222]
The START signal instructs the timing of data rewriting. The START signal may be a signal that becomes valid every certain period by a timer, or may be a display rewrite instruction signal from an MPU that is a source of display data or an external switch. FIG. 23 shows an example output from the MPU 20.
[0223]
Further, a temperature sensor 81 is provided in the vicinity of the liquid crystal panel 10, and the detection output of the temperature sensor 81 is input to the temperature compensation circuit 40. The temperature compensation circuit 40 gives an application time instruction signal corresponding to the detection output of the temperature sensor 81 to the controller 11.
[0224]
FIG. 24 is a block diagram illustrating a configuration example of the controller 11. The oscillator 33 generates a clock signal (CLK) having a predetermined frequency. The reference counter 34 receives CLK and counts it. When the count value of the reference counter 34 reaches a predetermined value, the line counter 35 increments the value by +1. The comparator 36 includes a count value (DOT) of the reference counter 34, a count value (LINE) of the line counter 35, and a set value (N₁~ N₄) To generate a CP signal, an M signal, an LP signal, a / DOFF1 signal, a / DOFF2 signal, and a SEL signal. The SEL signal is output to the selector 39.
[0225]
The memory 38 stores display data from the MPU 20. The selector 39 selects one of the data in the memory 38, the “1” fixed signal, and the “0” fixed signal in accordance with the SEL signal, and outputs the selected data to the CL-LCD 10 as a DATA signal.
[0226]
An application time instruction signal (setting value) for setting the voltage application time is written from the temperature compensation circuit 40 to the setting register 37. In this embodiment, the set value is a value converted by the number of clocks output from the oscillator 33. Here, the high voltage application time (first stage period) for vertical alignment is represented by N₁, The time of the non-applied part (second stage period) is N₂, The voltage application time (the period of the third stage) for transition to the FC state is N₃, 1 selection time in line sequential driving is N₄And
[0227]
When the data needs to be rewritten, the MPU instructs the setting register 37 to rewrite the display. When a display rewrite instruction is set in the setting register 37, a START signal is output to the comparator 36.
[0228]
FIG. 25 is a block diagram showing a configuration example of the temperature compensation circuit 40. The detection output of the temperature sensor 81 is converted into a digital signal by the A / D converter 41 and given to the address converter 42. The register 55 stores temperature coefficients relating to the first stage period and the third stage period corresponding to each temperature. The register 56 stores a temperature coefficient related to the period of the second stage corresponding to each temperature. The register 57 stores a temperature coefficient related to the period of the addressing unit corresponding to each temperature. Each temperature coefficient storage area has an address corresponding to the detected temperature.
[0229]
For example, if the detected temperature exceeds 65 ° C. and 75 ° C., the address converter 42 uses the temperature coefficient n corresponding to 70 ° C. in the registers 55, 56, and 57.₁, N₂, M are output. In FIG. 25, the temperature coefficient n corresponding to 70 ° C.₁, N₂, M is n₁(70), n₂(70), m (70).
[0230]
Where n₂≧ n₁And n₂≧ m. In each of the registers 55, 56 and 57, the lower temperature value is a larger value. In this embodiment, since the temperature coefficient corresponding to the highest temperature is “1”, each value stored in the registers 55, 56, and 57 is one or more values.
[0231]
The register 51 stores data (T) indicating the length of the first stage at a predetermined temperature (70 ° C. in this example)._10r) Is stored. The register 52 also contains data (T) indicating the length of the second stage at a predetermined temperature (70 ° C. in this example)._11r) Is stored. The register 53 stores data (T) indicating the length of the third stage at a predetermined temperature (70 ° C. in this example)._12r) Is stored. The register 54 stores data (T) indicating the length of the addressing section at a predetermined temperature (70 ° C. in this example)._2r) Is stored. The data indicating the length of the addressing unit may be data indicating the length of one display sequence or data indicating one selection period.
[0232]
Multiplier 61 multiplies the output of register 55 and the output of register 51 to create an application time instruction signal. That is, n₁・ T_10rThe application time instruction signal is generated by performing the above calculation. This application time instruction signal is N N used by the comparator 36 shown in FIG.₁This corresponds to (first stage: length of reset unit). Multiplier 62 multiplies the output of register 55 and the output of register 53 to create an application time instruction signal.
[0233]
That is, n₁・ T_11rThe application time instruction signal is generated by performing the above calculation. This application time instruction signal is N N used by the comparator 36 shown in FIG.₃This corresponds to (third stage: length of focal conic portion).
[0234]
The multiplier 63 multiplies the output of the register 56 and the output of the register 52 to create an application time instruction signal. That is, n₂・ T_11rThe application time instruction signal is generated by performing the above calculation. This application time instruction signal is N N used by the comparator 36 shown in FIG.₂This corresponds to (second stage: length of the non-applied portion).
[0235]
The multiplier 64 multiplies the output of the register 57 and the output of the register 54 to create an application time instruction signal. That is, m · T_2rThe application time instruction signal is generated by performing the above calculation. This application time instruction signal is the length N of the period of the addressing section.₄It corresponds to. However, in this example, N₄Is a value indicating one selection period.
[0236]
Next, the operation will be described with reference to the timing chart of FIG. Here, the liquid crystal application voltage required for vertically aligning the CL-LC and the on-voltage in line sequential driving are expressed as V_r+ V_c, The liquid crystal applied voltage and the off-voltage in line-sequential driving required to shift CL-LC to a mixed state of FC state and PL state_r-V_cAnd
[0237]
The controller 11 is in an initial state until a display start is instructed from the MPU 20. That is, the CP signal is maintained at a low level, the LP signal is maintained at a low level, the M signal is maintained at a high level, the DATA is maintained at a high level, and the / DOFF1 signal and the / DOFF2 signal are maintained at a low level. Since both the / DOFF1 signal and the / DOFF2 signal are at a low level, all the row electrodes and column electrodes are at the potential V₀The liquid crystal is not applied. Further, both the reference counter 34 and the line counter 35 hold 0.
[0238]
When the display start is instructed from the MPU 20, the START flag is set in the setting register 37, and the START signal becomes high level. When the START signal becomes high level, the comparator 36 puts the reference counter 34 into an operating state. The reference counter 34 increases the count value by 1 according to the clock (CLK) from the oscillator 33.
[0239]
When the value of the line counter 35 is 0, the reference counter 34 has a value of N₄Counts up until it matches. The comparator 36 sets the CP signal to the high level when the count value of the reference counter 34 is an even number, and sets the CP signal to the low level when the count value is an odd number, and outputs the CP signal by the number of pulses suitable for the number of dots of the display element. . During this time, since DATA is at a high level, the values of the internal registers of the column driver 13 are all at a high level.
[0240]
The count value of the reference counter 34 is N₄If it matches, the comparator 36 sets the CNT signal to the high level for one clock period. In response to the CNT signal, the reference counter 34 returns the value to 0, and the line counter 35 increments the value by 1. At this time, the LP signal is set to the high level for one clock period. Therefore, the value of the internal register of the column driver 13 is reflected in the output of the column driver 13.
[0241]
When the value of the line counter 35 becomes 1, the comparator 36 sets the / DOFF2 signal to the high level. Similar to the first embodiment, the voltage levels of all the column electrodes are V from the relationship shown in FIG.₅(V_r+ V_c) In addition, the voltage level of all the row electrodes is V₀Therefore, the liquid crystal applied voltage for all pixels is (V_r+ V_c) That is, a liquid crystal voltage necessary for vertical alignment is applied to the entire surface.
[0242]
The comparator 36 outputs a SEL signal that fixes DATA to a low level. The selector 39 selects “0” according to such a SEL signal. Then, the comparator 36 sequentially outputs the CP signal to set all the values of the internal registers of the column driver 13 to the low level. The reference counter 34 has a count value of N₁Counts up until it matches, and the count value is N₁If it matches, the count value is reset to zero. At this time, the value of the line counter 35 is incremented by 1 and becomes 2.
[0243]
When the value of the line counter 35 becomes “2”, the comparator 36 sets the / DOFF2 signal to the low level and sets all the output potentials of the column driver 13 to V.₀To. Therefore, the liquid crystal applied voltage is 0V. Next, the reference counter 34 has a count value of N₂Counts up until it matches.
[0244]
And the count value is N₂If the two match, the count value of the reference counter 34 is reset to 0, and the value of the line counter 35 is incremented by one. When the value of the line counter 35 changes from 2 to 3, the comparator 36 sets the LP signal to the high level for one clock period. As a result, the value of the internal register of the column driver 13 is reflected in the output of the column driver 13.
[0245]
When the value of the line counter 35 is “3”, the comparator 36 sets the / DOFF2 signal to the high level. At this time, since the M signal is at a high level and DATA latched in the column driver 13 is at a low level, the applied voltage to all the column electrodes is V based on the relationship shown in FIG.₃The liquid crystal applied voltage for all pixels is V₃(V_r-V_c) Therefore, the liquid crystal applied voltage necessary for the FC state is applied to the entire surface. Next, the reference counter 34 has a count value of N₃Counts up until it matches, and the count value is N₃If the value matches, the count value of the reference counter 34 returns to 0, and the value of the line counter 35 is incremented by one.
[0246]
When the value of the line counter 35 is “3”, the comparator 36 outputs a SEL signal for selecting display data from the memory 38 as DATA. The selector 39 enters a state of selecting display data from the memory 38 in accordance with such a SEL signal. The comparator 36 sequentially outputs CP signals and puts display data into the internal register of the column driver 13.
[0247]
When the value of the line counter 35 becomes 4, the comparator 36 sets the LP signal to the high level for one clock period and reflects the value of the internal register of the column driver 13 in the output of the column driver 13. Further, the FR signal is set to a high level for a certain period so as to include the LP signal pulse, and the row driver 12 is instructed to scan from the first row.
[0248]
The comparator 36 fixes the / DOFF1 signal at a high level. Therefore, a voltage necessary for line sequential driving is output as the output of the column driver 12 and the row driver 13. In FIG. 26, this period is shown as an addressing unit.
[0249]
The comparator 36 is configured such that the count value of the reference counter 34 is (N₄/ 2) is smaller, the M signal is set to low level and (N₄/ 2) If it is above, it is set to the high level, and the liquid crystal applied voltage at the time of line sequential driving is changed to AC. In addition, the display data of the memory 38 is output as DATA for the next selected row. DATA is taken into the internal register of the column driver 13 by the CP signal. The reference counter 34 has a count value of N₄Counts up until it matches, N₄If the two match, the count value of the reference counter 34 is reset to 0, and the value of the line counter 35 is incremented by one. Each time the value of the line counter 35 is incremented by one, the comparator 36 outputs an LP signal to instruct the row driver 12 to scan the next row and to the column driver 13 for the next display. Directs data output.
[0250]
When the value of the line counter 35 becomes (3 + number of display rows), the comparator 36 sets the CP signal and the LP signal to low level, and instructs the selector 39 to output “1” DATA with the SEL signal. , The M signal is fixed to the high level, and the count value of the reference counter 34 is N₄If the two coincide with each other, the CLR signal is set to the high level for one clock period, and the reference counter 34 and the line counter 35 are cleared to zero. Further, the / DOFF1 signal and the / DOFF2 signal are set to the low level, the liquid crystal application voltage is set to 0 V, the START flag is cleared, and the initial state is restored. Note that the number of display lines in the third embodiment is 60 lines.
[0251]
As described above, in the third embodiment, by using the M signal and the / DOFF signal that can be handled by the conventional liquid crystal driving device, the first stage to the third stage, that is, the reset unit. The non-application part and the focal conic part are created. Therefore, the IAPT drive driver can be applied to the present invention.
[0252]
The temperature compensation circuit 40 determines the voltage application time corresponding to the temperature detected by the temperature sensor 81, and the liquid crystal panel 10 is reset and the display data is written based on the determined voltage application time. However, good display quality can be maintained.
[0253]
Furthermore, in the second stage (non-applied part), it is necessary to increase the rate of increase of the voltage application time according to the temperature drop compared to the first and third stages, but as shown in FIG. By separately providing the register 55 relating to the first and third stages and the register 56 relating to the second stage, the length of the first to third stages can be controlled to an appropriate length according to the temperature. .
[0254]
Example 3-1 In order to initialize the entire screen of the liquid crystal panel 10 at a room temperature of 25 ° C., a voltage of 40 V was applied to the entire panel for 13.2 ms at the start of the display sequence. Subsequently, a non-application time in which the voltage applied to the liquid crystal panel 10 was 0 V was provided for 1 ms. Thereafter, a voltage of 23 V was applied to all the pixels for 3.3 ms as a voltage condition for setting the FC state. Then, line sequential driving was performed. The driving waveform shown in FIG. 9B was used.
[0255]
It was confirmed that the liquid crystal panel 10 was in the FC state in which some residual reflection was left by a series of voltage processing before writing the display data. Further, by continuously performing display writing by line-sequential driving, a test pattern was displayed under the above conditions. As a result, a display with a high contrast ratio was obtained without an afterimage.
[0256]
Furthermore, when the room temperature was 0 ° C., each voltage application time was quadrupled. Even in that case, when the test pattern was displayed, there was no afterimage and a display with a high contrast ratio was obtained.
[0257]
(Comparative Example 3-1) The liquid crystal panel 10 was driven at the room temperature of 0 ° C. under the same voltage application conditions (40 V, 13.2 ms, 0 V, 1 ms, 23 V, 3.3 ms) as in Example 3-1. An afterimage occurred when the test pattern was displayed. That is, under the same driving conditions as in Example 3-1, a good display cannot be obtained with many afterimages at 0 ° C. Further, when each voltage application time was made the same as in Example 1 and each applied voltage value was increased, a desired display was obtained, but a display with a low contrast was obtained.
[0258]
(Example 3-2) The first stage, the third stage, and the line among the voltage application conditions (40 V, 13.2 ms, 0 V, 1 ms, 23 V, 3.3 ms) in Example 3-1 at room temperature of 25 ° C. In the sequential drive period, the voltage application time was doubled, the voltage application time in the second stage was quadrupled, and the applied voltage value in each period was higher than in Example 3-1. When the test pattern was displayed, there was no afterimage and a high contrast display was obtained. Furthermore, the writing time could be shortened compared to the voltage application condition at 0 ° C. in Example 3-1.
[0259]
(Comparative Example 3-2) At the room temperature of 0 ° C., each voltage application time was doubled among the voltage application conditions (40 V, 13.2 ms, 0 V, 1 ms, 23 V, 3.3 ms) in Example 3-1. When the test pattern was displayed, there was no afterimage, but the display showed a low contrast.
[0260]
As described above, in the first stage, the CL-LC alignment state is changed to the HO state in order to erase the previously written display state. In the second stage, the CL-LC alignment state is changed from the HO state to the HG state or a mixed state of the HG state and the PL state. Further, in the third stage, the FC state or the mixed state of the FC state and the PL state is changed from the HG state or the mixed state of the HG state and the PL state. Then, in the line sequential drive period, a desired display state is written from the FC state or the mixed state of the FC state and the PL state.
[0261]
From Example 3-1, when the temperature of CL-LC falls, it turns out that the voltage application time of each step should just be lengthened. For example, when the temperature falls from 25 ° C. to 0 ° C., good display quality can be maintained by multiplying the voltage application time several times.
[0262]
However, the voltage application time required for changing to each orientation state differs between the stages. From Example 3-2 and Comparative Example 3-2, the second stage in which the CL-LC is changed from the HO state to the HG state or the mixed state of the HG state and the PL state depends on the temperature decrease compared to the other stages. It can be seen that the increase rate of the voltage application time needs to be increased.
[0263]
If the HO state cannot be sufficiently changed from the HO state to the mixed state of the HG state and the PL state in the second stage, the desired FC state or the mixed state of the FC state and the PL state is set in the third stage. As a result, in the line-sequential driving period, the off-state reflectivity originally desired to be set to the FC state increases and the contrast ratio decreases.
[0264]
(Example 3-3) With respect to the voltage application conditions (40 V, 13.2 ms, 0 V, 1 ms, 23 V, 3.3 ms) in Example 3-1, at a room temperature of 50 ° C., the applied voltage in each period is slightly lower. The liquid crystal panel 10 was driven after setting. When the test pattern was displayed, there was no afterimage and a display with a high contrast ratio was obtained.
[0265]
(Example 3-4) At a room temperature of 50 ° C., the voltage application period is halved with respect to the voltage application conditions (40 V, 13.2 ms, 0 V, 1 ms, 23 V, 3.3 ms) in Example 3-1. The liquid crystal panel 10 was driven after setting. In addition, when a test pattern was displayed in which the applied voltage in each period was set slightly lower than in Example 3-1, a high contrast ratio display was obtained without an afterimage.
[0266]
Based on the voltage application conditions at 25 ° C., the voltage application time is doubled at 0 ° C., and the voltage application time is halved at 50 ° C. It can be seen that good display can be obtained even at low temperatures.
[0267]
Of the series of voltage processing (display reset) before writing the display data, regarding the first stage period and the third stage period, the period increase / decrease ratio according to the temperature change is the same as when the display data is written. It is the same as the increase / decrease rate of the period. However, regarding the second period, when the temperature is low, it is preferable that the magnification of the voltage application period (0 V voltage application period) is larger than those magnifications.
[0268]
For specific temperature settings, the magnification n (t) for all the periods (display reset and display data writing period) except for the period of the second stage in the display reset._p) Is (t_p= Temperature), K which is a constant in the range of 5-50_AIs set so as to satisfy the following expression 3, a display with high contrast can be obtained. In the following formula 3, the right side of “^” indicates an index.
[0269]
n (t_p) = N (25) × 2 ^ ((25−t_p) / K_A(3)
[0270]
Further, if the predetermined temperature is 25 ° C., an arbitrary temperature t_pThe length of the period (addressing period) during which voltage is applied to each pixel based on the voltage condition corresponding to the display data in T₂(T_p), It is preferable to satisfy the relationship of the following formula 4.
[0271]
T₂(T_p) = T₂(25) × 2 ^ ((25-t_p) / K_B(4)
[0272]
K_BIs a constant set according to the CL-LC used. It is preferable to set in the range of 5-50. K_AAnd K_BIs preferably about 25.
[0273]
Furthermore, since the second stage is in a state where the applied voltage is 0 V, if the period is set to a long period at a predetermined temperature, the period of all stages can be set uniformly according to the temperature. In addition, high-speed display could be performed at each temperature without adjusting the voltage amplitude.
[0274]
Next, a reference example in which the CL-LCD is reset in the HG state or the PL state will be described. FIG. 27 shows a timing chart of drive waveforms, FIG. 28 shows a block diagram of a signal conversion circuit in the drive circuit, and FIG. 29 shows an operation timing chart of the signal conversion circuit. The circuit configuration and operation are common in many respects to the first, second, and third embodiments of the present invention. This can be achieved by changing the circuit configuration of FIG. 16 and the operation timing of FIG. 17 so as to generate the voltage pulses required in this reference example.
[0275]
That is, display was performed on the liquid crystal panel of Example 1-1 with the drive waveform of FIG. A voltage of 40 V was applied to the entire liquid crystal panel for 13.3 ms, followed by a non-voltage time of 1 ms. Subsequently, line sequential driving was performed v. At the time of selection, in the ON display (PL state), V_r+ V_cIn the off display (FC state), V_r-V_cVoltage was applied. V_r= 35V, V_c= 5V. The row electrode selection time was 3.3 ms. As a result of displaying the test pattern, a display with a high contrast ratio was obtained without an afterimage.
[0276]
(Example 4) Using each of the first, second, and third embodiments of the present invention and the reference example, a liquid crystal panel that can be used for an electronic book, a pager or a mobile display device which is a kind of portable display device is created. did. A high-definition full-dot matrix with row and column electrodes can be clearly displayed. FIG. 30 shows one aspect of the display. Even if the characters were fine, they could be read sufficiently. In addition, the viewing angle was wide, and the display screen was rewritten without discomfort. Further, it can be applied to a public display device using a relatively large display screen and an electrophotographic display device.
[0277]
【The invention's effect】
As described above, according to the present invention, the cholesteric liquid crystal can be surely aligned with the FC state or the quasi-FC state before writing display data, and an afterimage is generated even when high-speed writing is performed. Can be prevented, and the display quality can be improved even when the display is highly refined. Furthermore, since the time for aligning the state of the cholesteric liquid crystal with the FC state is shortened, the time required for a sequence for updating a series of images can be further shortened.
[Brief description of the drawings]
FIG. 1 is a graph showing a change in relative permittivity after voltage pulse application and interruption of a CL-LCD in a HO state.
FIG. 2 is a graph showing a reflection spectrum after voltage interruption of a CL-LCD.
FIG. 3 is a graph showing the relationship between the reflectance after reset and the voltage amplitude of the third voltage pulse when the application time of the third voltage pulse is 3.3 ms.
FIG. 4 is a schematic cross-sectional view of a CL-LCD.
FIG. 5 is a state diagram showing a change in display state when a voltage pulse (13.3 ms) is applied and erased.
FIG. 6 is a state diagram when the width of the voltage pulse is shortened (6.6 ms).
FIG. 7 is a state diagram when the width of the voltage pulse is shortened (3.3 ms).
FIG. 8 is a block diagram illustrating a configuration example of a driving device that drives a liquid crystal panel.
FIG. 9 is a drive waveform diagram schematically shown.
FIG. 10 is an explanatory diagram for explaining a function of an IAPT drive driver.
FIG. 11 is an explanatory diagram showing a relationship between a control signal and an applied voltage.
FIG. 12 is a block diagram showing a configuration of a driving device (Embodiment 1-A).
FIG. 13 is a block diagram illustrating a configuration example of a signal conversion circuit in Embodiment 1-A.
FIG. 14 is a timing chart showing the operation of the signal conversion circuit.
FIG. 15 is a block diagram showing a configuration of a driving device (Embodiment 2-A).
FIG. 16 is a block diagram illustrating a configuration example of a signal conversion circuit in Embodiment 2-A.
FIG. 17 is a timing chart showing the operation of the signal conversion circuit in Embodiment 2-A.
FIG. 18 is an explanatory diagram showing the alignment state of CL-LC.
FIG. 19 is an explanatory diagram showing the required number of times until the FC state is written using pulse width modulation (PWM).
FIG. 20 is a block diagram showing a configuration example of a PWM method controller.
FIG. 21 is a timing chart showing the operation of the PWM method controller.
FIG. 22 is a timing chart showing the operation of the PWM method controller.
FIG. 23 is a block diagram illustrating a configuration example of a temperature compensation type driving device.
FIG. 24 is a timing chart showing a configuration example of a temperature compensation circuit.
FIG. 25 is a timing chart showing a configuration example of a temperature compensation circuit.
FIG. 26 is a timing chart showing the operation of the display sequence control circuit.
FIG. 27 is a waveform diagram showing a drive waveform when reset is performed in a PL state.
FIG. 28 is a block diagram showing a drive circuit that performs reset in the PL state.
FIG. 29 is a timing chart when resetting in the PL state.
30 is an explanatory diagram showing a display state in an example of a liquid crystal display device of the present invention. FIG.
FIG. 31 is a schematic diagram showing phase state transition of CL-LC.
[Explanation of symbols]
1A, 1B glass substrate
2A, 2B electrode
3A, 3B polymer thin film
4 Liquid crystal composition
5 Light absorber
10 Cholesteric liquid crystal panel (liquid crystal optical element)
11 Signal control circuit (controller)
12 line driver
13 row driver
14 Signal conversion circuit
15 Power supply
16 Switch circuit
21 0.5 line detection circuit
22 OR circuit
23 Selector
23A OR circuit
24 Down counter
25-29 comparator
30 Start flag circuit
31 DOFF control circuit
33 Oscillator
34 Reference counter
35 line counter
35 comparator
37 Setting register
38 memory
39 Selector
40 Temperature compensation circuit
81 Temperature sensor

Claims (15)

  In a driving method for driving a liquid crystal display device including a memory cholesteric liquid crystal, a first step of applying a voltage so that the orientation of the cholesteric liquid crystal is substantially parallel to a voltage application direction; and the cholesteric liquid crystal is homogeneous or homogeneous A second stage for applying a voltage for shifting to a planar mixed state; and a third stage for applying a voltage for shifting the cholesteric liquid crystal from a homogeneous or homogeneous / planar mixed state to a focal conic. A driving method characterized by that.   In a driving method for driving a liquid crystal display device including a memory cholesteric liquid crystal, a first step of applying a voltage so that the orientation of the cholesteric liquid crystal is substantially parallel to a voltage application direction; and the cholesteric liquid crystal is homogeneous or homogeneous A second stage for applying a voltage for shifting to a mixed state of the planar, and a third stage for applying a voltage for shifting the cholesteric liquid crystal from a homogeneous or mixed state of the homogeneous and planar to a mixed state of focal conic and planar A driving method comprising the steps of: Assuming that the period of the second stage is τ ₂ and the time until the cholesteric liquid crystal in the homeotropic state exhibits the lowest dielectric constant after voltage interruption is τ _H by voltage application, 0.8 × τ _H ≦ τ ₂ ≦ 8 × the method according to claim 1 or claim 2 satisfies the tau _H. The driving method according to claim 3, wherein τ _H ≦ τ ₂ ≦ 5 × τ _H is satisfied.   The driving method according to any one of claims 1 to 4, wherein a voltage value applied in the second stage is 0V. The applied voltage waveform of the first stage is constituted by a pulse voltage having a voltage amplitude of V _1, a voltage waveform applied in the third stage is formed by a pulse voltage having a voltage amplitude of V _3, of each stage 6. The driving method according to claim ₁ , wherein when application time is τ ₁ and τ ₃ , V ₁ is larger than V ₃ and τ ₃ is smaller than τ ₁ .   When performing a line sequential operation to apply a voltage waveform based on display data of each display pixel after the first stage to the third stage, a planar is written for on display and a focal conic is applied for off display. The driving method according to any one of claims 1 to 6, wherein a pulse width modulation method is used for halftone display when the applied voltage condition is determined so that writing is performed.   In a driving device for driving a liquid crystal display device provided with a memory cholesteric liquid crystal, first period setting means for setting a period of a first stage and a second period for setting a second period following the first stage The period setting means, a third period setting means for setting a third period following the second stage, and a first period created by the first period setting means, the orientation is substantially parallel to the voltage application direction. A voltage is applied to the cholesteric liquid crystal so that the cholesteric liquid crystal transitions to a homogeneous state or a mixture of homogeneous and planar in the second period created by the second period setting means, In the third period created by the third period setting means, the cholesteric liquid crystal is changed from a homogeneous or a mixture of homogeneous and planar to a focal conic or planar. Driving apparatus characterized by comprising a voltage applying means for applying a voltage for shifting to a mixed state of the focal conic with.   In a driving method for driving a liquid crystal display device provided with a cholesteric liquid crystal having a memory property, the driving method is such that the alignment of the cholesteric liquid crystal is performed before applying a voltage to each pixel based on a voltage condition corresponding to display data. A first stage in which a voltage is applied so as to be substantially parallel to a voltage application direction; a second stage in which a voltage is applied to shift the cholesteric liquid crystal to a homogeneous state or a mixed state of a homogeneous and planar; and the cholesteric liquid crystal And a third step of applying a voltage for promoting the transition from the homogeneous state or the mixed state of the homogeneous and the planar state to the focal conic state or the mixed state of the focal conic and the planar state, and the first step after the first step. 2. Driving method characterized by repeating steps 2 and 3 .   The driving method according to claim 9, wherein the voltage value applied in the second stage is 0V.   The driving method according to claim 9 or 10, wherein the number of repetitions of the second stage and the third stage is 2 to 10 times. The applied voltage waveform of the first stage is constituted by a pulse voltage having a voltage amplitude of V _1, a voltage waveform applied in the third stage is formed by a pulse voltage having a voltage amplitude of V _3, of each stage 12. The driving method according to claim 9, wherein when the application time is τ ₁ and τ ₃ , V ₁ is larger than V ₃ and τ ₃ is smaller than τ ₁ . The applied voltage waveform of the first stage is constituted by a pulse voltage having a voltage amplitude of V _1, a voltage waveform applied in the third stage is formed by a pulse voltage having a voltage amplitude of V _3, of each stage the application time tau _1, when the tau _3, equal to V ₁ was V _3, and the driving of a cholesteric liquid crystal display device according to tau ₃ is tau ₁ smaller claim 9 in any one of claims 11 Method.   When the line sequential operation is performed to apply the voltage waveform based on the display data of each display pixel after the first stage to the third stage are completed, the planar is written in the on display and the focal is in the off display. The driving method according to any one of claims 9 to 13, wherein a pulse width modulation method is used for halftone display when the applied voltage condition is determined so that a conic is written.   In a driving device for driving a liquid crystal display device provided with a cholesteric liquid crystal having memory properties, first period setting means for setting a period of a first stage and a second period following the first stage are set. The second period setting means, the third period setting means for setting the third period following the second stage, and the first period created by the first period setting means are oriented in the voltage application direction. A voltage is applied to the cholesteric liquid crystal so as to be substantially parallel, and a voltage is applied to shift the cholesteric liquid crystal to a homogeneous state or a mixed state of homogeneous and planar in the second period created by the second period setting means. Then, in the third period created by the third period setting means, the cholesteric liquid crystal is homogeneous or mixed with a homogeneous and planar state, and the focal conic or Voltage application means for applying a voltage for promoting the transition to a mixed state of planar and focal conic, and the second period setting means and the third period after operating the first period setting means A drive device comprising: a number control means for repeatedly operating the setting means.

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