JP4703821B2 - IC card - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an IC card that performs communication with a reader / writer.
[0002]
[Prior art]
The IC card generally returns an initial response (ATR) when a reset signal is supplied from the reader / writer. The IC card has different initial response values depending on the terminal environment used.
There are various types of IC chips mounted on the IC card, and each IC has a maximum operating frequency according to each type.
[0003]
[Problems to be solved by the invention]
The IC card can double the external clock signal supplied from the reader / writer and generate an internal clock signal with a frequency higher than the external clock signal frequency, thereby improving the internal signal processing speed of the IC chip. It is.
In this case, it is necessary to double the internal clock signal frequency so that the internal clock signal frequency is equal to or lower than the maximum operating frequency that can be processed by the IC chip.
An object of the present invention is to provide an IC card capable of improving the signal processing speed.
[0004]
According to the present invention, there is provided an IC card which is provided with an external clock from a reader / writer and transmits / receives data to / from the reader / writer,
Performing signal processing based on the internal clock, and a control circuit and a memory, and a signal processing circuit, an external clock supplied from the reader-writer, based on the specified multiply rate, and imperial times, anda frequency Tei multiplying circuit for generating the internal clock,
The memory stores a maximum allowable frequency of the external clock and a maximum operating frequency of the signal processing circuit higher than the maximum allowable frequency of the external clock;
The control circuit stores, in the memory, the maximum operating frequency of the signal processing circuit stored in the memory at an initial response in which data indicating the maximum frequency of the external clock supplied from the reader / writer is transmitted to the reader / writer. Dividing by the maximum allowable frequency of the stored external clock to calculate the magnification, and designating the calculated magnification to the frequency multiplication circuit,
An IC card is provided.
[0005]
Preferably, the IC card is
A transmission / reception circuit that is supplied with the external clock, receives data from the reader / writer based on the supplied external clock, and transmits data from the signal processing circuit to the reader / writer;
A buffer circuit provided between the transmission / reception circuit and the signal processing circuit for adjusting a speed of the data to be transmitted / received;
It has further .
[0006]
The multiplier circuit multiplies the external clock signal from the reader / writer based on the initial response value to generate an internal clock signal. The signal processing speed of the signal processing circuit can be improved by setting the frequency of the internal clock signal to be larger than the external clock signal frequency and not more than the maximum operating frequency of the signal processing circuit.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[0008]
FIG. 1 is a schematic block diagram showing an embodiment of an IC card according to the present invention.
The IC card 10 includes interface circuits (I / F circuits) 11 and 12 and a central processing unit (CPU) 9. The CPU 9 is configured by, for example, a one-chip microcomputer (one-chip microcomputer), and includes a multiplier circuit 1, a transmission / reception circuit 2, and a signal processing circuit 6.
[0009]
The I / F circuit 11 is supplied with the external clock signal CLK0 from the reader / writer 20, and supplies the supplied external clock signal CLK0 to the CPU 9 in a signal form suitable for the CPU 9.
The I / F circuit 12 is supplied with various signals DT0 from the reader / writer 20, and supplies the supplied signal DT0 to the CPU 9 in a signal form suitable for the CPU 9. The I / F circuit 12 is supplied with various signals DT1 from the CPU 9, and supplies the supplied signal DT1 to the reader / writer 20 in a signal form suitable for the reader / writer 20.
[0010]
The transmission / reception circuit 2 has functions of a transmission circuit and a reception circuit. The transmission / reception circuit 2 is supplied with the external clock signal CLK0 from the I / F circuit 11, and performs a transmission / reception operation based on the supplied external clock signal CLK0.
The transmission / reception circuit 2 is supplied with the signal DT0 from the I / F circuit 12, and supplies the supplied signal DT0 to the signal processing circuit 6. Further, the transmission / reception circuit 2 is supplied with the signal DT 1 from the signal processing circuit 6, and supplies the supplied signal DT 1 to the reader / writer 20 via the I / F circuit 12.
[0011]
The buffer circuit 3 is supplied with an external clock signal CLK0 and an internal clock signal CLK1. The buffer circuit 3 adjusts the speed of signal transfer between the transmission / reception circuit 2 and the signal processing circuit 6.
[0012]
The multiplier circuit 1 is supplied with an external clock signal CLK 0 from the I / F circuit 11. The multiplier circuit 1 multiplies the external clock signal CLK0 based on the initial response value, and generates an internal clock signal CLK1 having a frequency equal to or higher than the external clock signal frequency. Then, the internal clock signal CLK1 is supplied to the signal processing circuit 6.
[0013]
The signal processing circuit 6 includes a control circuit 4 and a memory 5.
The signal processing circuit 6 performs various processes based on the internal clock signal CLK1. The signal processing circuit 6 returns an initial response indicating the maximum allowable frequency of the external clock signal CLK 0 supplied from the reader / writer 20 to the reader / writer 20 by the transmission / reception circuit 2.
[0014]
The control circuit 4 is a controller that controls the entire IC card 10 or CPU 9, and performs various signal processing and arithmetic processing using the internal clock signal CLK1. The control circuit 4 outputs a control signal S4 for controlling the multiplication to the multiplication circuit 1.
[0015]
The control circuit 4 is supplied with the signal DT0 from the transmission / reception circuit 2 via the buffer circuit 3, and performs various signal processing based on the supplied signal DT0.
Of the signal DT0 from the transmission / reception circuit 2, a data signal other than the reset signal is supplied to the control circuit 4 via the buffer circuit 3, and the reset signal is supplied directly from the transmission / reception circuit 2 to the control circuit 4. Also good. The reset signal may be supplied directly from the I / F circuit 12 to the control circuit 4.
[0016]
The control circuit 4 generates a signal DT1 and supplies the signal DT1 to the transmission / reception circuit 2 via the buffer circuit 3. The signal DT1 is, for example, an initial response signal for the reader / writer 20, and this initial response signal has data indicating the maximum allowable frequency fa of the external clock signal CLK0 from the reader / writer 20 and communication conditions. The control circuit 4 controls access to the memory 5.
[0017]
The memory 5 stores data FI indicating the maximum allowable frequency fa of the external clock signal CLK0 and data indicating the maximum operating frequency fm of the signal processing circuit 6, and supplies these data to the control circuit 4. The memory 5 may be configured to store data accessed from the reader / writer 20.
[0018]
The control circuit 4 generates a control signal S4 based on the maximum allowable frequency fa and the maximum operating frequency fm, and outputs this control signal S4 to the multiplier circuit 1.
The multiplier circuit 1 multiplies the external clock signal CLK0 having a frequency equal to or lower than the maximum allowable frequency fa supplied from the reader / writer 20 based on the control signal S4 to generate an internal clock signal CLK1. The frequency of the internal clock signal CLK1 is larger than the frequency of the external clock signal CLK0 and is not more than the maximum operating frequency fm of the signal processing circuit 6.
[0019]
FIG. 2 is a schematic explanatory diagram illustrating the correspondence between the maximum allowable frequency of the external clock signal and data indicating the maximum allowable frequency.
For example, JIS X 6304 and ISO / IEC 7816-3 have descriptions that define the contents of the initial response.
The initial response (initial response signal) sent back after the IC card 10 is reset includes information such as a start character TS, a configuration display character T0, connection information characters TA1, TB1, and TC1. Connection information character TA1 has data FI indicating maximum allowable frequency fa of external clock signal CLK0.
[0020]
When the data FI = 1, the maximum allowable frequency fa is 5 MHz.
When the data FI = 2, the maximum allowable frequency fa is 6 MHz.
When the data FI = 3, the maximum allowable frequency fa is 8 MHz.
When the data FI = 4, the maximum allowable frequency fa is 12 MHz.
When the data FI = 5, the maximum allowable frequency fa is 16 MHz.
When the data FI = 6, the maximum allowable frequency fa is 20 MHz.
For example, when FI = 5, the IC card 10 can perform signal processing when the frequency of the external clock signal CLK0 is 16 MHz or less.
[0021]
The control circuit 4 includes the multiplier circuit 1 so that the multiplication value of the maximum allowable frequency fa of the external clock signal CLK0 and the magnification (multiple magnification) is equal to or less than the maximum operating frequency fm of the signal processing circuit 6. The magnification is designated by the control signal S4.
The multiplication factor of the multiplication circuit 1 is equal to or less than the division value (fm / fa) obtained by dividing the maximum operating frequency fm by the maximum allowable frequency fa, and is the same or substantially the same as the division value (fm / fa). The frequency of the internal clock signal CLK1 can be brought close to the maximum operating frequency fm, and the signal processing speed can be further improved.
[0022]
The multiplier circuit 1 may have a configuration in which the frequency of the internal clock signal CLK1 is a power of two of the frequency of the external clock signal CLK0. By doing so, the multiplier circuit 1 can have a simple configuration. Is possible.
[0023]
The I / F circuits 11 and 12 may be configured with external connection terminals when the IC card 10 is a contact IC card, and electrical signals when the IC card 10 is a non-contact IC card. It may be configured by a conversion circuit such as an antenna device that performs conversion between radio waves and radio waves.
Moreover, the said embodiment is an illustration of this invention and this invention is not limited to the said embodiment.
[0024]
【The invention's effect】
As described above, according to the present invention, an IC card capable of improving the signal processing speed can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing an embodiment of an IC card according to the present invention.
FIG. 2 is a schematic explanatory diagram illustrating the correspondence between the maximum allowable frequency of an external clock signal and data indicating the maximum allowable frequency.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Multiplier circuit (multiplication circuit), 2 ... Transmission / reception circuit, 3 ... Buffer circuit, 4 ... Control circuit, 5 ... Memory, 6 ... Signal processing circuit, 9 ... Central processing unit (CPU), 10 ... IC card, 11 , 12 ... I / F circuit, 20 ... reader / writer, CLK0 ... external clock signal, CLK1 ... internal clock signal, S4 ... control signal.

Claims (2)

An IC card is provided with an external clock from a reader / writer and transmits / receives data to / from the reader / writer,
Performing signal processing based on the internal clock, and a control circuit and a memory, and a signal processing circuit,
Said external clock supplied from the reader-writer, and based on the specified multiply rate, have multiplied, the frequency Tei multiplying circuit for generating the internal clock,
Have
The memory stores a maximum allowable frequency of the external clock and a maximum operating frequency of the signal processing circuit higher than the maximum allowable frequency of the external clock;
The control circuit stores, in the memory, the maximum operating frequency of the signal processing circuit stored in the memory at an initial response in which data indicating the maximum frequency of the external clock supplied from the reader / writer is transmitted to the reader / writer. Dividing by the maximum allowable frequency of the stored external clock to calculate the magnification, and designating the calculated magnification to the frequency multiplication circuit,
IC card. The IC card
A transmission / reception circuit that is supplied with the external clock, receives data from the reader / writer based on the supplied external clock, and transmits data from the signal processing circuit to the reader / writer;
A buffer circuit provided between the transmission / reception circuit and the signal processing circuit for adjusting a speed of the data to be transmitted / received;
Further having
The IC card according to claim 1.

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