JP4703422B2 - Decode circuit - Google Patents

Description

  The present invention relates to a decoding circuit for image information, and has a display output and a recording output, a function capable of switching and outputting a decoded image and a captured image to a display output, and two decoding operations can be performed simultaneously. The present invention relates to a decoding circuit that specifies two decoding operations when switching a display output to a decoded image and a captured image in a decoding circuit having various functions.

  Recently, digital technology has become widespread. Along with this, compression / decompression technology such as MPEG (Moving Picture Expert Group) is also used in moving picture information such as digital TV and DVD (Digital Versatile Disk) player. It has been used in various image information devices.

  In general, in a television apparatus capable of receiving digital broadcasting, display output to a CRT (Casode Ray Tube), flat panel, etc. (output for display) and recording output for recording equipment such as a VCR (Video Casette Recorder) (recording) For output). When the recording output is considered for the purpose of recording the back program, it is necessary to continuously output the same channel video regardless of the display output in which the display channel is switched by the remote control operation from the user. In other words, when the display output is switched to capture (analog broadcasting, external input) from the state where one program is decoded and output to the display output and the recording output, the captured image is output to the display output, It is necessary to continue the decoding operation of the program and output it to the recording output.

  On the other hand, since the recording output is generally lower than the display resolution on a CRT, flat panel, etc. compatible with high-definition display, when considering only the output to the recording output with a low resolution, it is not a normal decoding operation. By performing a simple decoding operation in which the memory access amount is reduced as compared with the normal decoding operation, the memory access amount of the decoding circuit can be reduced.

  However, when switching the display output to capture display from the state where an image that has been subjected to normal decoding is output for display output and recording output, after stopping normal decoding to switch the decoding mode from normal decoding to simple decoding, When simple decoding is started, there is a problem that the decoded program is interrupted and the back program recording is interrupted.

  As a conventional technique, a technique is disclosed in which a stream decoding operation before and after a skip playback switching point is simultaneously performed, and a decoded image is smoothly switched before and after the switching point (see, for example, Patent Document 1). In the prior art described in Patent Document 1, only a decoding operation for performing continuous reproduction before and after the skip reproduction switching point is specified.

For this reason, in the prior art described in Patent Document 1, there is a problem that the recording output is interrupted when the display output is switched from the decoded image to the captured image.
JP 11-220695 A

As described above, the conventional decoding circuit has a problem that the recording output is interrupted when the display output is switched from the decoded image to the captured image.
An object of the present invention is to provide a decoding circuit that switches the decoding mode from normal decoding to simple decoding without interrupting the recording output when the display output is switched from the decoded image to the captured image.

  It is another object of the present invention to provide a decoding circuit that suppresses memory access peaks in a switching sequence.

  In order to achieve the above object, according to the present invention, a first decoding unit that receives and decodes compressed image information and outputs image information, and a first decoding unit that receives and decodes the compressed image information and outputs image information. 2 decoding units, a first buffer for storing image information output from the first decoding unit, a second buffer for storing image information output from the second decoding unit, and image information input from the outside The third buffer, the first selector for selecting image information stored in the first buffer and the second buffer, and the image information stored in the first buffer and the third buffer. A second selector unit, a first output unit that reads out image information stored in the buffer selected by the first selector unit, performs image processing, and outputs the image information; A second output unit that reads out image information stored in the buffer selected by the rectifier unit, outputs the processed image information, and a control unit; and the control unit includes: (a) the first decoding unit (B) when the second decoding unit is stopped, (c) the first selector selects the first buffer, and the first output unit is stored in the first buffer. (D) The second selector unit selects the first buffer, and the second output unit is processing and outputting the image information stored in the first buffer. In the states (a) and (b) and (c) and (d), the image information output by the second output unit is stored in the first buffer using the second selector unit. Stored in the third buffer from the image information The second output unit stops reading the image information stored in the first buffer, then starts the decoding operation of the second decoding unit, and then Using the first selector unit, the first output unit is changed to process and output the image information stored in the second buffer instead of the first buffer, and then the first decoding unit Next, using the second selector unit, the second output unit processes and outputs the image information stored in the third buffer instead of the first buffer. Then, the decoding circuit is characterized in that the second output unit controls to start reading the image information stored in the third buffer.

  In order to achieve the above object, according to the present invention, a first decoding unit that receives and decodes compressed image information and outputs image information, and receives and decodes the compressed image information to output image information. A second buffer that stores image information output from the first decoder, a second buffer that stores image information output from the second decoder, and image information input from the outside A first buffer for selecting image information stored in the first buffer and the second buffer, and image information stored in the first buffer and the third buffer. A second selector unit to be selected, a first output unit that reads out image information stored in the buffer selected by the first selector unit, performs image processing, and outputs A second output unit that reads out image information stored in the buffer selected by the second selector unit, performs image processing, and outputs the image information; and a control unit, wherein the control unit includes (a) the first (B) the second decoding unit is in a decoding operation, (c) the first selector unit selects the second buffer, and the first output unit stores in the second buffer. (D) the second selector unit selects the third buffer, and the second output unit processes the image information stored in the third buffer. In the states (a), (b), (c), and (d) during output, the image information output by the second output unit is stored in the third buffer using the second selector unit. Stored in the first buffer. The second output unit stops reading the image information stored in the third buffer, and then starts the decoding operation of the first decoding unit, The first selector unit is used to change the first output unit to process and output the image information stored in the first buffer instead of the second buffer. 2 The decoding operation of the decoding unit is stopped, and then, using the second selector unit, the second output unit processes the image information stored in the first buffer instead of the third buffer. The decoding circuit is characterized in that the second output unit controls to start reading the image information stored in the first buffer.

  Note that the present invention relating to an apparatus is also established as an invention relating to a method.

  According to the present invention, it is possible to provide a decoding circuit that switches the decoding mode from normal decoding to simple decoding without interrupting the recording output when the display output is switched from the decoded image to the captured image.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram showing a configuration of a decoding circuit according to the first embodiment of the present invention.
FIG. 3 is a block diagram showing an example of operation control of the decoding circuit (display output is decoded image → captured image).
FIG. 5 is a block diagram showing an example of operation control of the decoding circuit (display output is captured image → decoded image).
FIG. 7 is a block diagram showing an example of the configuration of a broadcast receiver that similarly includes a decoding circuit.

<Decode Circuit which is an Example of the Present Invention>
(Constitution)
An example of the configuration of a decoding circuit according to an embodiment of the present invention is, as shown in FIG. 1, a decoder unit to which a stream signal selected from an external tuner unit or the like (which may be an input terminal not shown) is input. 101, 102, buffers 103, 104 to which the output is input, a buffer 105 to which an image signal selected from an external input unit (which may be an input unit not shown) is input, and a selection unit 106 Then, the image signal stored in the buffers 103 and 104 is read out, subjected to image processing, and output to a recording output (may be an output terminal (not shown)), and stored in the buffers 103 and 105. The output unit 109 is configured to read out an image signal, and perform image processing to output to a display output (which may be an output terminal or a display device (not shown)). Each of the components by a control unit (not shown) is controlled.

Examples of image processing performed by the output unit 108 generally include scaling and image quality improvement (correction).
The decoding circuit according to an embodiment of the present invention can be realized by the above-described configuration as an example, but may be configured by a logic circuit having a desired function, or stores a microcomputer and an operation program. You may comprise as a microcomputer system by RAM, ROM, etc.

  Further, the decoding circuit according to an embodiment of the present invention can be incorporated in any device, but is particularly suitable for application to a broadcast receiving device as shown in FIG. It is not limited.

(Broadcast receiving apparatus to which a decoding circuit according to an embodiment of the present invention can be applied)
Next, an example of the configuration of a broadcast receiving apparatus to which the decoding circuit according to an embodiment of the present invention can be applied will be described in detail with reference to the drawing of FIG.
In the broadcast receiving apparatus of FIG. 7, the control unit 13 is connected to each unit via a control signal line (not shown) so as to control the entire operation, and a user instruction using the remote control 15 passes through the remote control light receiving unit 14. The control unit 13 controls each unit in accordance with an instruction from the user.

  When receiving a digital broadcast, a stream signal output from the BS / CS digital tuner 1 and the terrestrial digital tuner 2 is selected using the TS selector 3 and supplied to the TS separation unit 4. The TS separation unit 4 outputs the program information to the program information storage unit 5, and the control unit 13 uses the program information output to the program information storage unit 5 to display the program information on the GUI or the like via the video processing unit 23 for display output. Are output to the audio decoding unit 6 and the video stream is output to the video decoding unit 8.

  The audio signal decoded by the audio decoding unit 6 is output to the audio processing unit 7, and the video signal decoded by the video decoding unit 8 is output to the decoding buffer 20 of the video processing unit 9.

  At the time of analog broadcast reception or capture from an external input terminal (HDMI terminal, D terminal, S terminal, composite terminal, etc.), the capture signal (sound, video) selected by the capture selector 12 is sent to the audio processing unit 7 and video. The data is output to the capture buffer 21 of the processing unit 9.

  The decoded audio and the captured audio input to the audio processing unit 7 are subjected to audio processing under the control of the control unit 13, and then the decoded audio is output to the recording output (audio) and the captured audio is output to the speaker output.

  The decoded video (decode buffer 20) and the captured video (capture buffer 21) input to the video processing unit 9 are controlled by the control unit 13, and the image selected by the display selector 22 is displayed for display output. After the video processing is performed by the unit 23, the video is output to a CRT / flat panel or the like. As for the recording output, the decoded video is processed by the video processing unit 24 for recording output and then output to the recording output (video).

(Decoding processing unique to one embodiment of the present invention)
A decoding circuit according to an embodiment of the present invention can display a captured input image on a TV screen or the like as well as decode a stream obtained by receiving a digital broadcast or the like and display the stream on a TV screen or the like. is there.

  Also, two streams can be decoded simultaneously. As a decoding method, for example, in addition to a normal decoding operation, for example, a smaller access amount than a normal decoding operation instead of reducing the horizontal resolution in half. It has a simple decoding mode that can be decoded by

<Process to switch display output from decoded image to captured image (recorded output maintains decoded image)>
In the decoding circuit according to the embodiment of the present invention, a specific example of processing for switching the display output from the decoded image to the captured image while maintaining the decoded image output as the recording output is shown in the transition diagram of FIG. 3 and the flowchart of FIG. Will be described.

・ Problem when transition processing according to one embodiment of the present invention is not used In the following, the state transition for comparison of FIG. 4 using the comparison circuit of the decoding circuit according to one embodiment of the present invention shown in FIG. This will be described with reference to the drawings.
In the state transition diagram of FIG. 4, the image normally decoded (decoded A) by the decoder 101 is output to Buffer (A) 103, and the decoded image stored in Buffer (A) 103 is output using output means (α) 108. From the state of being output as video output (VCR) and output as video output (display) using the output means (β) 109, the image that is simply decoded (decoded B) by the decoder 101 is output to Buffer (A) 103 , The captured captured image is output to Buffer (C) 105, the decoded image stored in Buffer (A) 103 is output as video output (VCR) using output means (α) 108, and Buffer (C ) The captured image stored in 105 is used as video output (display) using the output means (β) 109. It shows a state transition to a state that force.

  Since the comparison circuit shown in FIG. 2 has only one decoding unit, only one stream can be decoded simultaneously. Therefore, when the decoding method is switched from the normal decoding (A) to the simple decoding (B), it is necessary to stop the decoding operation once. Therefore, as shown in FIG. 4, the video output (display) is decoded (A). In the state transition from switching to capture (C), there is a problem that the video output (VCR) must be stopped once.

In the case of the transition process according to an embodiment of the present invention The transition process for avoiding the above-described problem is illustrated in FIG. 1 as follows. The decoding circuit in the embodiment of the present invention and the state transition diagram and diagram of FIG. This will be described with reference to the flowchart of FIG.

  In the state transition diagram of FIG. 3, the image normally decoded (decoded A) by the decoder 101 is output to Buffer (A) 103, and the decoded image stored in Buffer (A) 103 is output using output means (α) 108. From the state of being output as video output (VCR) and being output as video output (display) using the output means (β) 109, the image that is simply decoded (decoded B) by the decoder 102 is output to the Buffer (B) 104 , The captured captured image is output to Buffer (C) 105, the decoded image stored in Buffer (B) 104 is output as video output (VCR) using output means (α) 108, and Buffer (C ) The captured image stored in 105 is used as video output (display) using the output means (β) 109. It shows a state transition to a state that force.

  First, an image normally decoded (decoded A) by the decoder 101 is output to the Buffer (A) 103, and the decoded image stored in the Buffer (A) 103 is output as a video (VCR) using the output means (α) 108. ) From the state of being output as video output (display) using the output means (β) 109, and the user captures the display output from the decoded image using the remote control 15 (terrestrial analog broadcast, external input, etc.) It is determined whether or not an instruction to switch to is issued (step S80). If there is such an instruction, the reading of the image stored in the Buffer (A) 103 of the output means (β) 109 is stopped, and the display output is stopped (Mute) (step S81).

  Next, after confirming that the memory access has been reduced by stopping the reading of the image by the output means (β) 109 (step S 82), the decoder 102 simply decodes the same stream supplied to the decoder 101 (decode B). Then, the buffer (B) 104 starts output (step S83).

  Next, after confirming that storage of an image that can be displayed on the Buffer (B) 104 has started (step S84), the decoded image read by the output means (α) 108 is converted into the normal decode (stored in the Buffer (A) 103 ( The selector 106 is switched so that the decoded (decoded A) becomes the simple decoded (decoded B) stored in the buffer (B) 104, and then the normal decoding (decode A) in the decoder 101 is stopped. (Step S85).

  Next, after confirming that the memory access has been reduced by stopping the normal decoding (decoding A) in the decoder 101 (step S86), the capturing of the captured image into the Buffer (C) 105 is started, and the output means (β ) 109 starts reading the image stored in the buffer (C) 105 (step S87).

  Next, after confirming that capture image capture into Buffer (C) 105 has started (step S88), display output by the output means (β) 109 is started (mute release) (step S89).

From the viewpoint of memory access amount,
Display output + VCR output + decode (A) → display output + VCR output + decode (A) + capture (C)
The amount of memory access after the state transition becomes
→ Display output + VCR output + Decode (B) + Capture (C)
By doing so, the maximum memory access amount required for the decoding circuit to operate is maximized,
Decode (A)-Decode (B)
The purpose is to reduce by a minute, and during the state transition,
Display output + VCR output + decode (A) + capture (C)
There is no point in exceeding the limit.
The difference between the memory access amount in the transition processing (see FIG. 3) and the memory access amount of the display output + VCR output + decode (A) + capture (C) according to the embodiment of the present invention is as follows: It becomes as follows.

Display output + VCR output + decode (A): Decrease capture (C) → VCR output + decode (A) + decode (B): Display output-decode (B) + decrease capture (C) → VCR output + decode ( B) + capture (C): display output + decode (A) -decode (B) decrement → display output + VCR output + decode (B) + capture (C): decode (A) -decode (B) decrement

  Here, when the memory access amount of the display output + capture (C)> the memory access amount of the decode (B), the memory access amount during the transition processing is the display output + VCR output + decode (A) + capture (C). As a result, the maximum memory access peak can be reduced as a result of the advantages of the transition processing according to an embodiment of the present invention, thereby reducing the memory bandwidth requirement for the decoding circuit. It is possible to prevent an increase in circuit cost due to maintaining a high memory bandwidth.

<Process to switch display output from captured image to decoded image (recorded output maintains decoded image)>
Hereinafter, in the decoding circuit according to an embodiment of the present invention, a specific example of the process of switching the display output from the decoded image to the captured image while maintaining the decoded image output as the recording output (the state opposite to the state transition described above) Transition method) will be described with reference to the transition diagram of FIG. 5 and the flowchart of FIG.

-Failure when the transition process according to one embodiment of the present invention is not used The following is a state transition for comparison in FIG. 6 using the comparison circuit of the decode circuit according to one embodiment of the present invention shown in FIG. This will be described with reference to the drawings.
In the state transition diagram of FIG. 6, the image that is simply decoded (decoded B) by the decoder 101 is output to Buffer (A) 103, and the captured image that is captured and input is output to Buffer (C) 105, and Buffer (A) 103 is output. The stored decoded image is output as video output (VCR) using the output means (α) 108, and the captured image stored in the Buffer (C) 105 is output as video output (display) using the output means (β) 109. ), The image normally decoded (decoded A) by the decoder 101 is output to the Buffer (A) 103, and the decoded image stored in the Buffer (A) 103 is output to the output means (α) 108. Output as video output (VCR) and output means (β) 109 as video output (display) It shows a state transition to a state that force.

  Since the comparison circuit shown in FIG. 2 has only one decoding unit, only one stream can be decoded simultaneously. Therefore, when the decoding method is switched from the simple decoding (B) to the normal decoding (A), it is necessary to stop the decoding operation once. Therefore, as shown in FIG. 6, the video output (display) is captured (C). In the state transition from switching to decoding (A), the video output (VCR) must be temporarily stopped (Mute).

In the case of the transition process according to the embodiment of the present invention The transition process for avoiding the above-described problem is illustrated in FIG. 1 as follows. The decoding circuit in the embodiment of the present invention and the state transition diagram and diagram of FIG. This will be described with reference to the flowchart of FIG.

  In the state transition diagram of FIG. 5, an image that has been simply decoded (decoded B) by the decoder 102 is output to Buffer (B) 104, and a captured image that has been captured and input is output to Buffer (C) 105. The stored decoded image is output as video output (VCR) using the output means (α) 108, and the captured image stored in the Buffer (C) 105 is output as video output (display) using the output means (β) 109. ), The image normally decoded (decoded A) by the decoder 101 is output to the Buffer (A) 103, and the decoded image stored in the Buffer (A) 103 is output to the output means (α) 108. Output as video output (VCR) and output means (β) 109 as video output (display) It shows a state transition to a state that force.

  First, the image that is simply decoded (decoded B) by the decoder 102 is output to the Buffer (B) 104, and the captured image that is captured and input is output to the Buffer (C) 105, and is stored in the Buffer (B) 104. The image is output as video output (VCR) using the output means (α) 108, and the captured image stored in the Buffer (C) 105 is output as video output (display) using the output means (β) 109. From this state, it is determined whether or not the user is instructed to switch the display output from the captured image (terrestrial analog broadcast, external input, etc.) to the decoded image using the remote controller 15 (step S90). If there is such an instruction, reading of the image stored in the Buffer (B) 104 of the output means (β) 109 is stopped and display output is stopped (Mute) (step S91).

  Next, after confirming that the reading of the image by the output means (β) 109 is stopped (step S92), the capturing of the captured image into the Buffer (C) 105 is stopped (step S93).

  Next, after confirming that the memory access has been reduced by stopping the capture of the captured image to Buffer (C) 105 (step S94), the decoder 101 performs normal decoding (decoding A) on the same stream supplied to the decoder 102. Then, the buffer (A) 103 starts output (step S95).

  Next, after confirming that storage of an image that can be displayed on Buffer (A) 103 is started (step S96), the decoded image read by output means (α) 108 is simply decoded (stored in Buffer (B) 104 ( The selector 106 is switched from the decoded B) to the normal decoded (decoded A) stored in the Buffer (A) 103, and then the simple decoding (decode B) in the decoder 102 is performed. Stop (step S97).

  Next, after confirming that memory access has been reduced by stopping simple decoding (decoding B) in the decoder 102 (step S98), display output by the output means (β) 109 is started (mute release) (step S99). ).

Perform the transition process as described above,
Memory output of display output + capture (C)> decode (B)
As a result of the advantage of the transition processing that is one embodiment of the present invention when the memory access amount is, the maximum peak of memory access can be reduced, so that the memory bandwidth requirement for the decode circuit can be lowered, It is possible to prevent an increase in circuit cost due to maintaining a high memory bandwidth.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

1 is a block diagram showing an example of a configuration of a decoding circuit according to an embodiment of the present invention. The block diagram which shows the example used as the comparison of a decoding circuit. FIG. 5 is a block diagram showing an example of operation control of a decoding circuit (display output is a decoded image → captured image). The block diagram which shows an example of the operation control (a display output is a decoding image-> capture image) of the example used as the comparison of a decoding circuit. The block diagram which shows an example of the operation control of a decoding circuit (a display output capture image-> decode image). The block diagram which shows an example of the operation control (a display output is a captured image-> decoded image) of the example used as the comparison of a decoding circuit. The block diagram which shows an example of a structure of the broadcast receiver containing a decoding circuit. 6 is a flowchart for explaining an example of operation control of a decoding circuit (display output is decoded image → captured image). 6 is a flowchart for explaining an example of operation control of a decode circuit (display output is captured image → decoded image).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... BS / CA digital tuner, 2 ... Terrestrial digital tuner, 3 ... TS selector, 4 ... TS separation part, 5 ... Program information storage part, 6 ... Audio decoding part, 7 ... Audio processing part, 8 ... Video decoding part, DESCRIPTION OF SYMBOLS 9 ... Video processing part, 10 ... Terrestrial analog tuner, 11 ... External input, 12 ... Capture selector, 13 ... Control part, 20 ... Decoding buffer, 21 ... Capture buffer, 22 ... Display output selector, 23 ... Video processing for display output , 24 ... Video processing unit for recording output, 101, 102 ... Decoding unit, 103, 104, 105 ... Buffer, 106, 107 ... Selector unit, 108, 109 ... Output unit.

Claims (3)

A first decoding unit that receives and decodes the compressed image information and outputs the image information;
A second decoding unit that receives the compressed image information and decodes it to output image information;
A first buffer for storing image information output by the first decoding unit;
A second buffer for storing image information output by the second decoding unit;
A third buffer for storing image information input from the outside;
A first selector for selecting image information stored in the first buffer and the second buffer;
A second selector for selecting image information stored in the first buffer and the third buffer;
A first output unit that reads out image information stored in the buffer selected by the first selector unit, performs image processing, and outputs the image information;
A second output unit that reads out image information stored in the buffer selected by the second selector unit, performs image processing, and outputs the image information;
A control unit,
The controller is
(A) During the decoding operation of the first decoding unit,
(B) The second decoding unit is stopping the decoding operation,
(C) The first selector unit selects the first buffer, and the first output unit is processing and outputting image information stored in the first buffer,
(D) the second selector unit selects the first buffer, and the second output unit is processing and outputting image information stored in the first buffer;
In the states (a) and (b) and (c) and (d),
When switching the image information output from the second output unit from the image information stored in the first buffer to the image information stored in the third buffer using the second selector unit,
The second output unit stops reading image information stored in the first buffer;
Next, the decoding operation of the second decoding unit is started,
Next, using the first selector unit, the first output unit is changed to process and output the image information stored in the second buffer instead of the first buffer,
Next, the decoding operation of the first decoding unit is stopped,
Next, using the second selector unit, the second output unit is changed to process and output the image information stored in the third buffer instead of the first buffer,
Next, the decoding circuit characterized in that the second output unit controls to start reading the image information stored in the third buffer. A first decoding unit that receives and decodes the compressed image information and outputs the image information;
A second decoding unit that receives the compressed image information and decodes it to output image information;
A first buffer for storing image information output by the first decoding unit;
A second buffer for storing image information output by the second decoding unit;
A third buffer for storing image information input from the outside;
A first selector for selecting image information stored in the first buffer and the second buffer;
A second selector for selecting image information stored in the first buffer and the third buffer;
A first output unit that reads out image information stored in the buffer selected by the first selector unit, performs image processing, and outputs the image information;
A second output unit that reads out image information stored in the buffer selected by the second selector unit, performs image processing, and outputs the image information;
A control unit,
The controller is
(A) The first decoding unit is stopping the decoding operation,
(B) The second decoding unit is decoding.
(C) The first selector unit selects the second buffer, and the first output unit is processing and outputting image information stored in the second buffer,
(D) the second selector unit selects the third buffer, and the second output unit is processing and outputting image information stored in the third buffer;
In the states (a) and (b) and (c) and (d),
When switching the image information output by the second output unit from the image information stored in the third buffer using the second selector unit to the image information stored in the first buffer,
The second output unit stops reading image information stored in the third buffer;
Next, the decoding operation of the first decoding unit is started,
Next, using the first selector unit, the first output unit is changed to process and output the image information stored in the first buffer instead of the second buffer,
Next, the decoding operation of the second decoding unit is stopped,
Next, using the second selector unit, the second output unit is changed to process and output the image information stored in the first buffer instead of the third buffer,
Next, a decoding circuit characterized in that the second output unit controls to start reading image information stored in the first buffer.   When comparing the case where the first decoding unit performs the decoding operation and the case where the second decoding unit performs the decoding operation, the second decoding unit performs the decoding operation with fewer memory accesses than the first decoding unit. The decoding circuit according to claim 1 or 2, characterized in that:

Images