JP4700040B2 - Display device - Google Patents

Description

The present invention relates to a matrix display equipment that uses current as a signal transmission means, in particular, it relates to a display equipment which aimed to reduce power consumption.

  In a matrix display device such as a liquid crystal display device and a plasma display panel (hereinafter also referred to as PDP), a display controller that sequentially outputs image data and a display panel are driven based on the image data output from the display controller. A source driver that generates a drive signal and a display panel that displays an image using the drive signal are provided.

  Conventionally, in such a display device, transmission of a signal between the display controller and the source driver is performed by a voltage signal composed of two values of a power supply potential and a ground potential. However, when trying to increase the speed of the voltage signal, a delay occurs due to the parasitic capacitance of the transmission path, so that there is a limit to increasing the speed of the voltage signal.

  Therefore, the present applicant has developed a technique for transmitting a signal by electric current and disclosed it in Patent Document 1. With this technique, it is possible to suppress the influence of the parasitic capacitance of the transmission path and increase the signal speed. Moreover, in this patent document 1, the technique which provides a power supply in a receiving part without providing a power supply in the transmission part was also disclosed. Thereby, even if the number of reception units changes, it is not necessary to change the specification of the transmission unit, and the design of the transmission unit is facilitated.

  Specifically, a pair of wires for transmitting a signal is provided between the transmitter and the receiver. In the transmitter, one of the wires is connected to the ground electrode and the other is floated based on the signal to be transmitted. Set to the state (high impedance state). As a result, a current flows from the power source provided in the receiving unit to the wiring connected to the ground electrode, and no current flows to the other wiring. As a result, complementary signals can be transmitted through the pair of wires. The applicant named this transmission system CMADS (Current Mode Advanced Differential Signaling).

  FIG. 15 is a block diagram showing a conventional liquid crystal display device to which this CMADS is applied. As shown in FIG. 15, in this conventional liquid crystal display device, a display controller 101, a source driver 102, and a liquid crystal panel 103 are provided. In addition, two pairs of wirings 104 a and 104 b and 105 a and 105 b are provided between the display controller 101 and the source driver 102.

  The display controller 101 receives image data that is a digital binary voltage signal from the outside, and outputs the image data for each line. In the display controller 101, a display data memory 106, a timing control circuit 107, an image data V-I conversion circuit 108, and a clock signal V-I conversion circuit 109 are provided. The display data memory 106 receives image data from the outside and holds image data for one screen. The timing control circuit 107 reads out image data for one line from the display data memory 106 and outputs a clock signal to the clock signal V-I conversion circuit 109. In synchronization with the clock signal, the timing control circuit 107 outputs the clock signal for one line. Are sequentially output to the V-I conversion circuit 108 for image data. The image data V-I conversion circuit 108 is connected to one end of a pair of wirings 104a and 104b. Based on the image data, one of the wirings 104a and 104b is connected to the ground electrode, and the other is in a floating state. To do. The clock signal VI conversion circuit 109 is connected to one end of a pair of wirings 105a and 105b. Based on the clock signal, one of the pair of wirings 105a and 105b is connected to the ground electrode and the other is connected to the other. It is intended to float.

  The source driver 102 includes an image data IV conversion circuit 121, a clock signal IV conversion circuit 122, a shift register 123, a data latch circuit 124, a gradation selection circuit 125, and an output circuit 126. Yes. The image data IV conversion circuit 121 is connected to the other end of the pair of wirings 104a and 104b. When the image data VI conversion circuit 108 connects the wiring 104a or 104b to the ground electrode, this grounding is performed. A current is passed through the wiring connected to the electrodes to generate a complementary current signal in the pair of wirings 104a and 104b, thereby receiving the image data from the image data V-I conversion circuit 108 as a current signal. It is. Then, based on this current signal, the image data is reconverted into a binary voltage signal and output to the data latch circuit 124. The clock signal IV conversion circuit 122 is connected to the other ends of the pair of wirings 105a and 105b. When the clock signal VI conversion circuit 109 connects the wiring 105a or 105b to the ground electrode, this grounding is performed. A current is caused to flow through the wiring connected to the electrodes to generate complementary current signals in the pair of wirings 105a and 105b, thereby receiving the clock signal as a current signal from the clock signal VI conversion circuit 109. It is. Based on this current signal, the clock signal is reconverted into a binary voltage signal and output to the shift register 123.

  The shift register 123 receives a clock signal and sequentially outputs pulse signals from a plurality of output terminals to the data latch circuit 124. The data latch circuit 124 captures a plurality of image data in synchronization with the pulse signal and outputs the plurality of image data to the gradation selection circuit 125 simultaneously. The gradation selection circuit 125 is a DA converter, and outputs a gradation signal that is an analog voltage signal to the output circuit 126 by digital-analog conversion (D / A conversion) of the output signal of the data latch circuit 124. It is. The voltage of the gradation signal is a voltage applied to each pixel of the liquid crystal panel 103. The output circuit 126 amplifies the current of the gradation signal to generate a drive signal and outputs it to each pixel of the liquid crystal panel 103.

  Further, in the liquid crystal panel 103, two transparent substrates (not shown) arranged opposite to each other, a liquid crystal layer (not shown) sandwiched between the transparent substrates, and the rear of the two transparent substrates. And a backlight (not shown). In the liquid crystal panel 103, pixels (not shown) are arranged in a matrix.

  Next, the operation of this conventional liquid crystal display device will be described. First, image data, which is a binary voltage signal, is input to the display data memory 106 and held for one screen. The timing control circuit 107 reads out image data for one line from the display data memory 106 and outputs a clock signal, which is a binary voltage signal, to the clock signal VI conversion circuit 109. The timing control circuit 107 sequentially outputs image data to the image data V-I conversion circuit 108 in synchronization with the clock signal.

  Next, the image data V-I conversion circuit 108 connects one of the pair of wirings 104a and 104b to the ground electrode based on the image data, and sets the other to a floating state. For example, when the image data is high, the wiring 104a is connected to the ground electrode, the wiring 104b is in a floating state, and when the image data is low, the wiring 104a is in a floating state, and the wiring 104b is connected to the ground electrode. Further, the clock signal VI conversion circuit 109 connects one of the pair of wirings 105a and 105b to the ground electrode based on the clock signal, and puts the other in a floating state.

  As a result, the image data IV conversion circuit 121 causes a current to flow through the wiring connected to the ground electrode of the pair of wirings 104a and 104b. This current flows from the image data IV conversion circuit 121 to the ground electrode via the wiring 104a or 104b. On the other hand, no current flows through the floating wiring. As a result, the image data, which is a voltage signal, is converted into a pair of complementary current signals, and the image data V-I conversion circuit 108 converts the image data into IV through the pair of wirings 104a and 104b. It is transmitted to the circuit 121. The image data IV conversion circuit 121 reconverts the current signal into a binary voltage signal to regenerate the image data, and outputs the image data to the data latch circuit 124.

  Similarly, the clock signal IV conversion circuit 122 supplies a current to the wiring connected to the ground electrode among the pair of wirings 105a and 105b. On the other hand, no current flows through the floating wiring. As a result, the clock signal, which is a voltage signal, is converted into a complementary pair of current signals, and the clock signal I / V conversion circuit 109 converts the clock signal I / V through the pair of wirings 105a and 105b. Is transmitted to the circuit 122. The clock signal IV conversion circuit 122 reconverts the current signal into a binary voltage signal, regenerates the clock signal, and outputs the clock signal to the shift register 123.

  Then, the shift register 123 takes in the clock signal from the clock signal IV conversion circuit 122 and sequentially outputs pulse signals to the data latch circuit 124 from a plurality of output terminals. The data latch circuit 124 takes in a plurality of image data from the image data IV conversion circuit 121 in synchronization with the pulse signal, and outputs the plurality of image data to the gradation selection circuit 125 simultaneously. Next, the gradation selection circuit 125 performs D / A conversion on the output signal to generate a gradation signal that is an analog voltage signal, and outputs the gradation signal to the output circuit 126. Next, the output circuit 126 amplifies the current of the gradation signal to generate a drive signal and applies it to each pixel of the liquid crystal panel 103.

  On the other hand, in the liquid crystal panel 103, the backlight irradiates each pixel with light. Then, the light transmittance is changed according to the voltage of the drive signal applied to the liquid crystal layer of each pixel, and an image is formed as the entire liquid crystal panel 103.

JP 2001-053598 A

  However, the conventional techniques described above have the following problems. Recently, particularly in a small display device such as a mobile phone, a function for saving the amount of image data such as a subtractive color mode is mounted as standard. For example, the amount of image data is reduced from 18 bits to 3 bits by reducing the image data of 260,000 colors to 8 colors. A technique for encoding and compressing image data is also being used in general.

  As described above, when the amount of image data is reduced, dummy transfer is performed except for data necessary for displaying an image in signal transfer between the display controller and the source driver. At this time, when image data is transmitted by a voltage signal as in the conventional case, power consumption can be reduced by reducing the amount of image data. However, when the image data is transmitted by the current signal as described above, the current continues to flow through the wiring between the display controller and the source driver even during the dummy transfer, which has the effect of reducing power consumption. There is a problem that it cannot be obtained.

The present invention was made in view of the above problems, and an object thereof is to provide a display equipment which can reduce the speed and power consumption of the signal transmission.

The display device according to the present invention includes an image data wiring, a display controller connected to one end of the image data wiring, and an image sent to the image data wiring connected to the other end of the image data wiring. A source driver that generates a drive signal based on the data, and a display panel that displays an image based on the drive signal, wherein the display controller displays a predetermined amount of data for each pixel. The image according to an image display mode that designates a normal mode based on the image data or a color reduction mode in which the image display is performed based on the image data in which the amount of data for each pixel is smaller than the normal mode. The display controller adjusts the frequency of data. The display controller outputs a control signal according to an image display mode, and the image data. And a timing control circuit for outputting a receiver control signal indicating the display mode of the image and sequentially outputting at a frequency adjusted based on the control signal, and the source driver indicates the receiver control signal A drive signal is generated based on an image display mode, and one or more pairs of the image data wirings are provided, and the display controller selects one of the pairs of the image data wirings based on the image data. An image data switching control circuit in which one is connected to a reference potential terminal and the other is in a floating state, and the source driver causes the current to flow through a line connected to the reference potential terminal among the image data lines. Generate one or more pairs of complementary current signals based on image data and drive based on these current signals It generates No., characterized in that in accordance with the display mode of the image which the receiver control signal indicates is for controlling the magnitude of current to be supplied to the image data lines.

  In the present invention, by generating a complementary current signal based on the image data, the current signal is transmitted through the image data wiring. Thereby, image data can be transmitted at high speed. Further, when the display controller connects one of each pair of the image data wirings to the reference potential terminal based on the image data and does not float the other, that is, the output of the image data is stopped. In some cases, it is possible to reduce power consumption by preventing current from flowing through any of the image data lines.

  The display device includes a pair of clock signal wirings, the display controller is connected to one end of the clock signal wiring, and one of the pair of clock signal wirings based on a clock signal. Is connected to a reference potential terminal and the other is floated to output the clock signal, the source driver is connected to the other end of the clock signal wiring, and the display controller is outputting the clock signal A pair of complementary current signals based on the clock signal is generated by causing a current to flow through the wiring connected to the reference potential terminal among the pair of clock signal wirings, and the display controller is stopped when the clock signal is stopped. In some cases, it is preferable that no current flow through any of the clock signal wirings.

  Thus, by generating a complementary current signal based on the clock signal, the current signal is transmitted through the clock signal wiring. Thereby, a clock signal can be transmitted at high speed. In addition, when the output of the clock signal is stopped, the power consumption can be reduced by preventing the current from flowing through any of the clock signal wirings.

  Further, the display controller outputs a receiver control signal indicating whether the display controller is outputting image data or stopping image data output, and the image controller outputs the image based on the image data output from the timing control circuit. An image data switching circuit in which one of each pair of data wiring is connected to a reference potential terminal and the other is in a floating state, and the source driver indicates that the receiver control signal is outputting image data Is configured to generate one or more pairs of complementary current signals based on the image data by passing a current through a line connected to the reference potential terminal among the one or more pairs of image data lines. The image data is regenerated based on the current signal, and the receiver control signal is stopped outputting image data. Preparative may stop applying a current to the connected image data wire to said reference potential terminal to indicate.

  Alternatively, the source driver generates a pair of complementary current signals based on the clock signal by causing a current to flow through a line connected to the reference potential terminal among the pair of clock signal lines. A clock signal conversion circuit that regenerates the clock signal based on the signal, and a clock signal stop detection circuit that detects whether the clock signal conversion circuit generates a current signal based on the clock signal. Then, it may be determined whether the display controller is outputting the clock signal or stopping the output of the clock signal based on the detection result.

  Alternatively, the display controller reads a predetermined amount of the image data and sequentially outputs the image data, and the timing control circuit reads the predetermined amount of image data read before one drive timing and the predetermined amount of current read. A data comparison circuit that compares the image data and outputs the result to the timing control circuit, and either one of the pairs of the image data wirings based on the image data output from the timing control circuit. An image data switching circuit connected to a reference potential terminal and floating the other, and the timing control circuit indicates whether image data output is being performed or image data output is being stopped based on a comparison result of the data comparison circuit A receiver control signal is output, and the source driver When the receiver control signal indicates that image data is being output, one pair based on the image data is caused by passing a current through a line connected to the reference potential terminal among the one or more pairs of image data lines. Alternatively, when a plurality of pairs of complementary current signals are generated and the image data is regenerated based on the current signals, and the receiver control signal indicates that image data output is stopped, it is connected to the reference potential terminal. It may be possible to stop the flow of current through the image data wiring.

  In the present invention, by adjusting the frequency of the current signal according to the display mode, the frequency of the current signal can be lowered when the amount of image data is small.

  A display unit configured to output a control signal according to an image display mode; and a receiver that sequentially outputs the image data at a frequency adjusted based on the control signal and indicates the image display mode. A timing control circuit that outputs a control signal, and the source driver may generate a drive signal based on a display mode of the image indicated by the receiver control signal. Further, one or more image data lines are provided, and the display controller connects one of the image data lines to a reference potential terminal and floats the other based on the image data. An image data switching control circuit for setting a state, and the source driver causes one or a plurality of pairs based on the image data to flow through a line connected to the reference potential terminal among the line for image data. Complementary current signals are generated, drive signals are generated based on these current signals, and the magnitude of the current flowing through the image data wiring is controlled according to the image display mode indicated by the receiver control signal It may be. As a result, in a display mode such as a color reduction mode with a small amount of image data, the current value necessary for transmitting the current signal is reduced, so that the current value can be lowered. As a result, power consumption can be suppressed.

  The display panel may be a liquid crystal display panel, a plasma display panel, or an organic EL (Electro Luminescence) display panel.

  As described above in detail, according to the present invention, when image data is transmitted between the display controller and the source driver in the display device, the image data is transmitted by a current signal, and the current is transmitted when the image data is not transmitted. By stopping, signal transmission speed can be increased and power consumption can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing a liquid crystal display device according to the present embodiment, FIG. 2 is a circuit diagram showing a V-I conversion circuit for image data of the liquid crystal display device shown in FIG. 1, and FIG. It is a circuit diagram which shows the IV conversion circuit for image data of the liquid crystal display device shown. The liquid crystal display device according to the present embodiment is a liquid crystal display device to which CMADS is applied.

  As shown in FIG. 1, in the liquid crystal display device according to the present embodiment, a display controller 1, a source driver 2, and a liquid crystal panel 3 are provided. Between the display controller 1 and the source driver 2, two pairs of wirings 4a and 4b and 5a and 5b are provided, and a wiring 11 is further provided. The number of source drivers 2 depends on the size of the liquid crystal panel 3 and the performance of the source driver 2. For example, a display device having a small liquid crystal panel such as a cellular phone is provided with one source driver. A large display is provided with, for example, about 10 to 12 source drivers.

  The display controller 1 receives image data as a digital binary voltage signal from the outside, and outputs this image data for each line of the image. The display data memory 6, the timing control circuit 7, and the image data V− An I conversion circuit 8, a clock signal V-I conversion circuit 9, and a mode register 10 are provided. The display data memory 6 receives external image data and holds a certain amount of image data, for example, image data for one screen. The mode register 10 receives data relating to an image display mode such as a subtractive color mode, and outputs a control signal to the display data memory 6 and the timing control circuit 7 in accordance with the display mode. The display data memory 6 and the mode register 10 are provided with input terminals.

  The timing control circuit 7 reads out a fixed amount of image data, for example, one line of image data, from the display data memory 6 based on the control signal output from the mode register 10, and sends it to the clock signal VI conversion circuit 9. A clock signal is output to the image data, and the image data for one line is sequentially output to the image data V-I conversion circuit 8 based on the control signal in synchronization with the clock signal. A receiver control signal indicating whether or not image data is output is output to the source driver 2 through the wiring 11. In addition, the timing control circuit 7 outputs a signal STH that activates the source driver 2. The signal STH is transmitted to the source driver 2 through a wiring (not shown).

  As shown in FIG. 2, the image data VI conversion circuit 8 includes an input terminal T1, two inverters INV1 and INV2, two N-channel MOS transistors Qn9 and Qn10, and ground electrodes GND1 and GND2. It has been. The input terminal of the inverter INV1 is connected to the input terminal T1, and the output terminal is connected to the input terminal of the inverter INV2 and the gate of the transistor Qn9. The output terminal of the inverter INV2 is connected to the gate of the transistor Qn10. The drain of the transistor Qn9 is connected to the wiring 4a, the source is connected to the ground electrode GND1, the drain of the transistor Qn10 is connected to the wiring 4b, and the source is connected to the ground electrode GND2.

  The configuration of the clock signal VI conversion circuit 9 is the same as the configuration of the image data VI conversion circuit 8, and is connected to one end of a pair of wirings 5a and 5b. One of the pair of wirings 5a and 5b is connected to a ground electrode (not shown) and the other is in a floating state.

  The source driver 2 includes an image data IV conversion circuit 21, a clock signal IV conversion circuit 22, a shift register 23, a data latch circuit 24, a gradation selection circuit 25, and an output circuit 26.

  As shown in FIG. 3, in the image data IV conversion circuit 21, the bias terminal T2, the input terminal T3 connected to the wiring 4a, the input terminal T4 connected to the wiring 4b, and the input connected to the wiring 11 are used. A terminal T5 and an output terminal T6 are provided. The image data IV conversion circuit 21 includes P-channel MOS transistors Qp1 to Qp6, N-channel MOS transistors Qn1 to Qn8, two-output NAND gates NAND1 and NAND2, and an inverter INV3. The transistor Qp5 constitutes a current detection unit 27, the transistors Qp6, Qn7, and Qn8 constitute a potential control unit 28, the transistors Qp1, Qn1, Qp3, and Qn3 constitute a first current supply unit, and the transistors Qp2, Qn2, Qp4 , Qn4 constitutes a second current supply unit. Each of the transistors Qp1 to Qp4 constitutes a constant current source, and each of the transistors Qn1 to Qn4 constitutes a switching transistor. In other words, each current supply unit is provided with a pair of constant current sources and a switching transistor. The RS latch circuit 29 is configured by the NAND gates NAND1 and NAND2 and the inverter INV3.

  The source of the transistor Qp5 and the gates of the transistors Qn7 and Qn8 are connected to the power supply electrode VDD1. The gates of the transistors Qp5, Qn5, and Qn6 are connected to the bias terminal T2. The drain of the transistor Qp5 and the sources of the transistors Qp1 to Qp4 and Qp6 are connected to the node Nc.

  The sources of the transistors Qn5, Qn6, and Qn8 and the gate of the transistor Qp6 are connected to the switch S1, and the switch S1 is connected to the ground electrode GND3 or the power supply electrode VDD2. That is, the switch S1 selects whether the source of the transistor Qn8 is connected to the ground electrode GND3 or the power supply electrode VDD2 based on the receiver control signal input through the wiring 11 and the input terminal T5. By connecting the source of the transistor Qn8 to the ground electrode GND3, the first current supply unit and the second current supply unit function, and a current flows through either the first current supply unit or the second current supply unit. By connecting the source of the transistor Qn8 to the power supply electrode VDD2, the functions of the first current supply unit and the second current supply unit are stopped, and no current flows through both the first current supply unit and the second current supply unit. There are other methods for stopping the functions of the first current supply unit and the second current supply unit. For example, the node Nd may be connected to the ground electrode, and the bias terminal T2 may be connected to the power supply electrode.

  The drains of the transistors Qp1 and Qn1 are connected to the gates of the transistors Qp1 and Qp2. The gates of the transistors Qn1 to Qn4 and the drains of the transistors Qp6 and Qn7 are connected to the node Nd. The sources of the transistors Qn1 and Qn3 and the drain of the transistor Qn5 are connected to the input terminal T3. The sources of the transistors Qn2 and Qn4 and the drain of the transistor Qn6 are connected to the input terminal T4. The drains of the transistors Qp2 and Qn2 and one input terminal of the NAND gate NAND1, which is a reset input of the RS latch circuit 29, are connected to the node Na.

  The drains of the transistors Qp3 and Qn3 and one input terminal of the NAND gate NAND2 which is the set input of the RS latch circuit 29 are connected to the node Nb. The drains of the transistors Qp4 and Qn4 are connected to the gates of the transistors Qp3 and Qp4. The source of the transistor Qn7 is connected to the drain of the transistor Qn8. The output terminal of the NAND gate NAND1 is connected to the other input terminal of the NAND gate NAND2 and the input terminal of the inverter INV3, and the output terminal of the NAND gate NAND2 is connected to the other input terminal of the NAND gate NAND1. The output terminal of the inverter INV3, which is the output terminal of the RS latch circuit 29, is the output terminal T6 of the image data IV conversion circuit 21. Note that the potentials of the nodes Na, Nb, Nc, and Nd are potentials Va, Vb, Vc, and Vd, respectively.

  The configuration of the clock signal IV conversion circuit 22 shown in FIG. 1 is the same as the configuration of the image data IV conversion circuit 21, and is connected to a pair of wires 5 a and 5 b and a wire 11.

  The shift register 23 receives the clock signal from the clock signal IV conversion circuit 22 and sequentially outputs pulse signals from a plurality of output terminals (not shown) to the data latch circuit 24. The shift register 23 is also supplied with a signal STH for starting the capture of the clock signal. The data latch circuit 24 captures a plurality of image data from the image data IV conversion circuit 21 in synchronization with the pulse signal, and outputs the plurality of image data to the gradation selection circuit 25 simultaneously. . The gradation selection circuit 25 is a DA converter, which D / A converts the output signal of the data latch circuit 24 to generate a gradation signal that is an analog voltage signal and outputs it to the output circuit 26. is there. The voltage of the gradation signal is a voltage applied to each pixel of the liquid crystal panel 3. The output circuit 26 amplifies the current of the gradation signal to generate a drive signal and outputs it to each pixel of the liquid crystal panel 3.

  Further, in the liquid crystal panel 3, two transparent substrates (not shown) arranged opposite to each other, a liquid crystal layer (not shown) sandwiched between the transparent substrates, and the rear of the two transparent substrates. And a backlight (not shown). In the liquid crystal panel 3, pixels (not shown) are arranged in a matrix. One pixel is formed by, for example, three RBG cells.

  Next, a method for driving the liquid crystal display device according to this embodiment will be described. FIG. 4 is a timing chart showing a driving method of the liquid crystal display device according to the present embodiment, and FIG. 5 is an image data VI conversion circuit 8 and an image data IV conversion of the liquid crystal display device according to the present embodiment. 3 is a timing chart showing the operation of the circuit 21.

  As shown in FIGS. 1 and 4, first, image data that is a binary voltage signal is input to the display data memory 6 of the display controller 1, and the display data memory 6 holds, for example, image data for one screen. The mode register 10 receives a signal indicating an image display mode, and the mode register 10 outputs a control signal to the display data memory 6 and the timing control circuit 7 in accordance with the display mode. The display mode includes a normal mode for displaying an image with 260,000 colors and a color reduction mode for displaying an image with 8 colors, for example.

  Next, the timing control circuit 7 reads out image data for one line from the display data memory 6 based on the control signal output from the mode register 10, and uses a clock signal as a binary voltage signal for the clock signal. Output to the VI conversion circuit 9. The timing control circuit 7 sequentially outputs image data to the image data V-I conversion circuit 8 in synchronization with the clock signal. As shown in FIG. 4, when the display mode is the normal mode, the timing control circuit 7 sequentially outputs image data for 260,000 colors, and when the display mode is, for example, an 8-color subtractive color mode, the timing control circuit 7 The image data for the colors are output together, and the output of the clock signal and the image data is stopped for the remaining time. Then, the timing control circuit 7 outputs a receiver control signal indicating whether or not the clock signal and the image data are output to the source driver 2 through the wiring 11. This receiver control signal is a binary voltage signal, and is, for example, low (L) when a clock signal and image data are output, and high (H) when not output. .

  Next, as shown in FIGS. 2 and 5, the image data V-I conversion circuit 8 grounds one of the pair of wires 4a and 4b based on the image data input from the timing control circuit 7. While connecting to the electrode, the other is in a floating state. For example, when the image data input to the input terminal T1 is high, the output terminal of the inverter INV1 becomes low, the gate of the transistor Qn9 becomes low, and the source-drain of the transistor Qn9 is turned off. Thereby, the wiring 4a is in a floating state. Further, the output terminal of the inverter INV2 becomes high, the gate of the transistor Qn10 becomes high, and the source and drain of the transistor Qn10 are turned on. Thereby, the wiring 4b is connected to the ground electrode GND2. Similarly, when the image data is low, the wiring 4a is connected to the ground electrode GND1, and the wiring 4b is in a floating state.

  Further, the clock signal VI conversion circuit 9 connects one of the pair of wirings 5a and 5b to the ground electrode based on the clock signal, and puts the other in a floating state. The operation of the clock signal VI conversion circuit 9 is the same as the operation of the image data VI conversion circuit 8.

  As shown in FIGS. 3 and 5, in the image data IV conversion circuit 21, when the clock signal and the image data are output from the timing control circuit 7, the switch S1 is connected to the ground electrode GND3. When the image data is low, the wiring 4a is connected to the ground electrode GND1 and becomes a ground potential, and the wiring 4b is in a floating state and becomes a floating potential, the gate-source voltages of the transistors Qn1 and Qn3 become Vd and turn on. In addition, the current driving ability based on the voltage Vd is exhibited. Thus, the transistors Qp1 and Qp3 cause a current to flow toward the ground electrode GND1 of the image data V-I conversion circuit 8 via the input terminal T3 and the wiring 4a by a constant current operation based on the voltage Vc. At this time, the voltage Vb becomes low. On the other hand, no current flows through the wiring 4b. That is, the first current supply unit supplies current to the wiring 4a, and the second current supply unit stops supplying current to the wiring 4b. At this time, the potential of the wiring 4a is a ground potential, and the potential of the wiring 4b is a floating potential but is about 100 to 200 mV higher than the ground potential.

  The transistors Qn2 and Qn4 are turned off when the gate-source voltage becomes zero. The transistors Qp2 and Qp4 raise the potential Va by constant current operation. As a result, in the RS latch circuit 29, the set input becomes high and the reset input becomes low.

  A bias voltage Vs having a predetermined value is applied to the bias terminal T2. As a result, the transistors Qp5, Qn5, and Qn6 are turned on when the gate-source voltage becomes Vs, and exhibit the current drive capability based on the voltage Vs.

  On the other hand, when the image data is high, the wiring 4a is in a floating state and becomes a floating potential, and the wiring 4b is connected to the ground electrode GND2 and becomes the ground potential, the transistors Qn1 and Qn3 have zero gate-source voltage. Turn off. The transistors Qp1 and Qp3 bring the potential Vb to a high level by a constant current operation. Further, the transistors Qp2 and Qn4 are turned on when the gate-source voltage becomes Vd, and exhibit current driving ability based on the voltage Vd. Thus, the transistors Qp2 and Qp4 cause a current to flow toward the ground electrode GND2 of the image data V-I conversion circuit 8 via the input terminal T4 and the wiring 4b by a constant current operation based on the voltage Vc. On the other hand, no current flows through the wiring 4a. That is, the first current supply unit stops supplying current to the wiring 4a, and the second current supply unit supplies current to the wiring 4b. At this time, the potential of the wiring 4b is a ground potential, and the potential of the wiring 4a is a floating potential, but is about 100 to 200 mV higher than the ground potential. At this time, the voltage Va is low. As a result, in the RS latch circuit 29, the set input becomes low and the reset input becomes high.

  Thus, when a current flows through the wiring 4a or 4b based on the image data, a complementary current signal based on the image data is generated in the pair of wirings 4a and 4b. As a result, the image data, which is a binary voltage signal input to the V-I conversion circuit 8 for image data, is converted into a complementary current signal, and this current signal is imaged via a pair of wires 4a and 4b. The data is transmitted from the data V-I conversion circuit 8 to the image data I-V conversion circuit 21. For example, when the image data is high, no current flows through the wiring 4a, but a current flows through the wiring 4b. When the image data is low, a current flows through the wiring 4a and no current flows through the wiring 4b.

  The RS latch circuit 29 determines a value to be held when the set input or the reset input changes from the high level to the low level. When the set input changes from low to high, the value of the output terminal T6 becomes high, and when the reset input changes from low to high, the value of the output terminal T6 becomes low. As a result, the image data IV conversion circuit 21 converts the current signal flowing through the pair of wirings 4a and 4b into a binary voltage signal, and regenerates the image data. The regenerated image data is output to the data latch circuit 24.

  When the clock signal and the image data are not output from the timing control circuit 7, the switch S1 is connected to the power supply electrode VDD2. Thereby, the functions of the first current supply unit and the second current supply unit are stopped, and no current flows through any of the wirings 4a and 4b.

  When the frequency of the image data to be transmitted is determined, the necessary amount of current is determined. This current amount is controlled by the current detector 27 based on a bias signal input through the bias terminal T2.

  Further, the clock signal IV conversion circuit 22 causes a current to flow through the wiring connected to the ground electrode of the pair of wirings 5a and 5b by the same operation as the image data IV conversion circuit 21. On the other hand, no current flows through the floating wiring. As a result, the clock signal, which is a voltage signal, is converted into a complementary pair of current signals and transmitted from the clock signal VI conversion circuit 9 to the clock signal IV conversion circuit 22. Then, the clock signal IV conversion circuit 22 reconverts the current signal into a binary voltage signal, regenerates the clock signal, and outputs the clock signal to the shift register 23. When the clock signal and the image data are not output from the timing control circuit 7, the clock signal IV conversion circuit 22 does not pass a current through any of the wirings 5a and 5b.

  Then, the shift register 23 takes in the clock signal from the clock signal IV conversion circuit 22 and sequentially outputs pulse signals to the data latch circuit 24 from a plurality of output terminals. The data latch circuit 24 takes in a plurality of image data from the image data IV conversion circuit 21 in synchronization with the pulse signal, and outputs the plurality of image data to the gradation selection circuit 25 simultaneously. Next, the gradation selection circuit 25 D / A converts this output signal to generate a gradation signal that is an analog voltage signal, and outputs it to the output circuit 26. Next, the output circuit 26 amplifies the current of the gradation signal to generate a drive signal and applies it to each pixel of the liquid crystal panel 3.

  On the other hand, in the liquid crystal panel 3, the backlight irradiates each pixel with light. Then, a drive signal is applied to each pixel. As a result, the liquid crystal layer of each pixel changes the light transmittance according to the voltage of the drive signal, and the liquid crystal panel 3 as a whole forms an image.

  In this embodiment, transmission of image data and a clock signal between the display controller 1 and the source driver 2 is performed by a current signal. For this reason, it is possible to increase the speed of signal transmission by suppressing the influence of the parasitic capacitance of the wiring. As a result, in the conventional voltage transmission method, for example, 18 wires are required to transmit 18-bit image data, and a total of 19 wires are combined with one wire for clock signal transmission. However, according to the present embodiment, since the transmission of the image data and the clock signal can be speeded up, a pair of wiring for image data transmission and a pair of wiring for clock signal transmission Image data and clock signals can be transmitted with only a total of four wires. As a result, the number of wirings can be reduced, and the circuit portion of the liquid crystal display device can be reduced in size.

  Further, as described above, in the wiring pairs 4a and 4b and 5a and 5b, since the voltage amplitude is as small as about 100 to 200 mV, the noise accompanying the signal transmission is small. Further, since the power source is provided on the receiving side, that is, the source driver 2 instead of the transmitting side, that is, the display controller 1, it is not necessary to change the specifications of the display controller even if the number of the source drivers 2 changes. The controller design is easy.

  Furthermore, in the present embodiment, the display controller 1 is provided with the mode register 10 and outputs a receiver control signal indicating whether or not the image data and the clock signal are output from the timing control circuit 7. When the clock signal is not output, the image data IV conversion circuit 21 and the clock signal IV conversion circuit 22 stop supplying current to the wirings 4a and 4b and the wirings 5a and 5b. Accordingly, when a display mode with a small amount of image data such as a color reduction mode is employed, it is possible to stop the current from flowing through the wiring during a period in which the image data is not transmitted. As a result, power consumption can be reduced.

  Next, a second embodiment of the present invention will be described. FIG. 6 is a block diagram showing the liquid crystal display device according to this embodiment. As shown in FIG. 6, in the liquid crystal display device according to this embodiment, the timing controller 7 in the display controller 1a is replaced with the liquid crystal display device according to the first embodiment (see FIG. 1). Are provided with a timing control circuit 7a, and a CLK stop detection circuit 30 is provided in the source driver 2a. Further, the wiring 11 is not provided. The other configuration of the liquid crystal display device of this embodiment is the same as that of the liquid crystal display device according to the first embodiment described above.

  The timing control circuit 7a is different from the timing control circuit 7 of the first embodiment in that it does not output a receiver control signal. Other configurations and operations are the same as those of the timing control circuit 7. The CLK stop detection circuit 30 is connected to the clock signal IV conversion circuit 22 and detects whether or not a current signal based on the clock signal is input to the clock signal IV conversion circuit 22. The result is output to the image data IV conversion circuit 21 and the clock signal IV conversion circuit 22 as a receiver control signal. When the current signal based on the clock signal is not input to the clock signal IV conversion circuit 22, the image data IV conversion circuit 21 stops the current from flowing through the wirings 4a and 4b. .

  Next, a method for driving the liquid crystal display device according to this embodiment will be described. FIG. 7 is a timing chart showing a driving method of the liquid crystal display device according to this embodiment. Note that the detailed description of the same portions of the driving method of the present embodiment as those of the driving method of the first embodiment is omitted.

  First, as shown in FIGS. 6 and 7, the display data memory 6 holds image data which is a binary voltage signal, as in the first embodiment. The mode register 10 outputs a control signal to the display data memory 6 and the timing control circuit 7a according to the display mode.

  Next, the timing control circuit 7a reads image data for one line from the display data memory 6 based on this control signal, and converts the clock signal, which is a binary voltage signal, to the clock signal VI conversion circuit 9. Output for. The timing control circuit 7a sequentially outputs image data to the image data V-I conversion circuit 8 in synchronization with the clock signal. At this time, when the display mode is, for example, an 8-color subtractive color mode, as shown in FIG. 7, the image data for 8 colors are output together, and the output of the clock signal and the image data is stopped for the remaining time. . The timing control circuit 7a does not output a receiver control signal, unlike the timing control circuit 7 of the first embodiment.

  Next, the image data V-I conversion circuit 8 connects one of the pair of wirings 4a and 4b to the ground electrode based on the image data input from the timing control circuit 7a, and the other is in a floating state. And Similarly, the clock signal VI conversion circuit 9 connects one of the pair of wirings 5a and 5b to the ground electrode based on the clock signal, and puts the other in a floating state.

  In the image data IV conversion circuit 21, the switch S1 is connected to the ground electrode GND3 when the clock signal and the image data are output from the timing control circuit 7a. Then, a current is passed through the wiring connected to the ground electrode among the wirings 4a and 4b by the same operation as in the first embodiment. As a result, the image data, which is a voltage signal, is converted into a pair of complementary current signals and received, and the current signal is converted again into a voltage signal to regenerate the image data. Similarly, the clock signal IV conversion circuit 22 receives the clock signal and regenerates it.

  At this time, the CLK stop detection circuit 30 detects whether or not a current signal based on the clock signal is input to the clock signal IV conversion circuit 22, and uses the result as a receiver control signal for the image data IV. Output to the switch S1 (see FIG. 3) of the conversion circuit 21. When no current signal is input to the clock signal IV conversion circuit 22, the switch S1 (see FIG. 3) of the image data IV conversion circuit 21 is switched to supply power to the transistor Qn8. Connect to electrode VDD2. As a result, the image data IV conversion circuit 21 stops supplying current to the wirings 4a and 4b. In order for the CLK stop detection circuit 30 to detect whether or not a current signal based on the clock signal is input to the clock signal IV conversion circuit 22, the clock signal IV conversion circuit 22 includes a wiring A current is always supplied to either 5a or 5b.

  Subsequent steps are the same as those in the first embodiment. That is, the shift register 23 captures the clock signal, the data latch circuit 24 captures the image data, and outputs this image data to the gradation selection circuit 25. Next, the gradation selection circuit 25 D / A converts this output signal to generate a gradation signal that is an analog voltage signal, and outputs it to the output circuit 26. Next, the output circuit 26 amplifies the current of the gradation signal to generate a drive signal and applies it to each pixel of the liquid crystal panel 3. Then, the liquid crystal panel 3 displays an image.

  In this embodiment, the CLK stop detection signal 30 is provided on the receiving side, that is, the source driver 2a, and the CLK stop detection signal 30 determines whether or not the clock signal is stopped. This eliminates the need to transmit the receiver control signal between the display controller 1a and the source driver 2a. As a result, in this embodiment, in addition to the effect of the first embodiment described above, there is an effect that a wiring for transmitting the receiver control signal (corresponding to the wiring 11 shown in FIG. 1) becomes unnecessary.

  Next, a third embodiment of the present invention will be described. FIG. 8 is a block diagram showing a liquid crystal display device according to this embodiment. As shown in FIG. 8, in the liquid crystal display device according to the present embodiment, the timing controller 7 has a timing control circuit 7 as compared with the liquid crystal display device according to the first embodiment (see FIG. 1). Instead, a timing control circuit 7b is provided, and a data comparison circuit 12 is provided. Further, no mode register is provided. The other configuration of the liquid crystal display device of this embodiment is the same as that of the liquid crystal display device according to the first embodiment described above.

  The data comparison circuit 12 is connected to the display data memory 6 and the timing control circuit 7b, holds the image data read from the display data memory 6 by the timing control circuit 7b, and this image data and the timing control circuit 7b are the next. The image data read from the display data memory 6 is compared, and the result is output to the timing control circuit 7b. Further, the timing control circuit 7b receives the output signal of the data comparison circuit 12 as compared with the timing control circuit 7 of the first embodiment, and stops outputting the image data and the clock signal based on this. Is different. Other configurations and operations are the same as those of the timing control circuit 7.

  Next, a method for driving the liquid crystal display device according to this embodiment will be described. FIG. 9 is a timing chart showing a driving method of the liquid crystal display device according to this embodiment. Note that the detailed description of the same portions of the driving method of the present embodiment as those of the driving method of the first embodiment is omitted.

  First, as shown in FIGS. 8 and 9, the display data memory 6 holds image data that is a binary voltage signal. Next, the timing control circuit 7 b reads a certain amount of image data from the display data memory 6. At this time, the image data is also output to the data comparison circuit 12, and the data comparison circuit 12 stores the image data. Then, when the timing control circuit 7b next reads a certain amount of image data from the display data memory 6, the data comparison circuit 12 compares this image data with the stored previous image data, The result is output to the timing control circuit 7b. At this time, the data comparison circuit 12 compares, for example, image data for one pixel with image data of a pixel adjacent to this pixel, and determines whether or not they are equal to each other.

  When the data comparison circuit 12 determines that the image data of adjacent pixels are not equal to each other, the timing control circuit 7b outputs a clock signal to the clock signal V-I conversion circuit 9, and this clock. Image data is sequentially output to the image data V-I conversion circuit 8 in synchronization with the signal. When the data comparison circuit 12 determines that the image data of adjacent pixels are equal to each other, the timing control circuit 7b stops outputting the clock signal and the image data. Further, the timing control circuit 7 b outputs a receiver control signal indicating whether or not a clock signal and image data are output to the source driver 2 through the wiring 11.

  Subsequent steps are the same as those in the first embodiment. That is, the image data V-I conversion circuit 8 connects one of the pair of wirings 4a and 4b to the ground electrode based on the image data, and puts the other in a floating state. Similarly, the clock signal VI conversion circuit 9 connects one of the pair of wirings 5a and 5b to the ground electrode based on the clock signal, and puts the other in a floating state.

  Then, the source driver 2 generates a pair of current signals based on the image data and a pair of current signals based on the clock signal. At this time, when the timing control circuit 7b does not output the image data and the clock signal based on the receiver control signal, the generation of the current signal is stopped. Based on these current signals, a driving signal for the liquid crystal panel 3 is generated and output. When the generation of the current signal is stopped, the same drive signal as the previous drive signal is output. Then, the liquid crystal panel 3 displays an image based on this drive signal. For example, if one pixel is composed of three RGB display elements, the data for driving each display element is 6 bits, and the data for one pixel is 18 bits, the data latch circuit 24 is 18 bits of data. The gradation selection circuit 25 generates three analog signals from RGB 6-bit data, and the output circuit 26 drives the three RGB display elements.

  Thus, in this embodiment, when the image data is the same between adjacent pixels, the pixel data can be compressed and the transmission of the image data can be stopped. Further, when the image data is not transmitted, the generation of the current signal is stopped. This reduces the amount of image data to be transmitted when displaying a uniform image such as an all-white display, and suppresses power consumption associated with image data transmission by stopping the current when image data is not transmitted. be able to.

  In the present embodiment, an example in which image data between adjacent pixels is compared is shown, but the present invention is not limited to this. For example, image data of a pixel group composed of a plurality of pixels may be compared with image data of a pixel group composed of the same number of pixels as this pixel group and adjacent to this pixel group. The image data for the next line adjacent to may be compared. Further, in the present embodiment, the example in which the timing control circuit 7b stops outputting the image data and the clock signal when the image data between adjacent pixels is the same is shown, but the present invention is not limited to this. For example, when the image data of a certain pixel is equal to the image data obtained by inverting the image data of the pixel adjacent to this pixel, the timing control circuit 7b may stop outputting the image data and the clock signal. . As a result, the amount of image data can be reduced in the monochrome mode. Alternatively, the pixel data may be encoded by a method other than this to compress the image data, and the output of the image data and the clock signal may be stopped at the remaining time.

  Next, a fourth embodiment of the present invention will be described. FIG. 10 is a block diagram showing a liquid crystal display device according to this embodiment. As shown in FIG. 10, in the liquid crystal display device according to the present embodiment, the timing controller circuit 7 includes a timing control circuit 7 as compared with the liquid crystal display device according to the first embodiment (see FIG. 1). Instead, a timing control circuit 7c is provided. The receiver control signal output from the timing control circuit 7c is input to the bias terminal T2 (see FIG. 3) of the image data IV conversion circuit 21 and the bias terminal of the clock signal IV conversion circuit 22. It is like that. The other configuration of the liquid crystal display device of this embodiment is the same as that of the liquid crystal display device according to the first embodiment described above.

  The timing control circuit 7c reads a fixed amount of image data from the display data memory 6 based on the control signal output from the mode register 10, and outputs a clock signal to the clock signal VI conversion circuit 9, A predetermined amount of image data is sequentially output to the image data V-I conversion circuit 8 based on the control signal in synchronization with the clock signal. At this time, the timing control circuit 7 c adjusts the frequencies of the image data and the clock signal based on the control signal output from the mode register 10. That is, when the display mode is the subtractive color mode and the amount of image data is smaller than that in the normal mode, the frequencies of the image data and the clock signal are lowered. The timing control circuit 7 c outputs a receiver control signal indicating the frequency of the image data and the clock signal to the source driver 2 through the wiring 11. Further, the image data IV conversion circuit 21 and the clock signal IV conversion circuit 22 adjust the magnitude of the current flowing through the wirings 4a, 4b, 5a, and 5b based on the receiver control signal.

  Next, a method for driving the liquid crystal display device according to this embodiment will be described. FIG. 11 is a timing chart showing a driving method of the liquid crystal display device according to the present embodiment. FIG. 12 shows the maximum frequency fmax of the current signal transmitted on the horizontal axis and the current signal of the maximum frequency transmitted on the vertical axis. It is a graph which shows the relationship between the maximum frequency of a current signal, and a required current, taking the constant current value required to do. Note that the detailed description of the same portions of the driving method of the present embodiment as those of the driving method of the first embodiment is omitted.

  First, as shown in FIGS. 10 and 11, the display data memory 6 holds image data which is a binary voltage signal, as in the first embodiment. The mode register 10 outputs a control signal to the display data memory 6 and the timing control circuit 7c according to the display mode.

  Next, the timing control circuit 7 c reads out a predetermined amount of image data from the display data memory 6 based on this control signal, and outputs a clock signal to the clock signal VI conversion circuit 9. The timing control circuit 7c sequentially outputs image data to the image data V-I conversion circuit 8 in synchronization with the clock signal. At this time, the frequency of the image data and the clock signal is adjusted according to the amount of image data. That is, when the display mode is, for example, an 8-color subtractive color mode, the frequency is lowered so that image data for 8 colors can be sent using the transfer period to the maximum, that is, the surplus time is minimized. To do.

  Next, based on the image data input from the timing control circuit 7c, the image data V-I conversion circuit 8 connects one of the pair of wirings 4a and 4b to the ground electrode, and the other is in a floating state. And Similarly, the clock signal VI conversion circuit 9 connects one of the pair of wirings 5a and 5b to the ground electrode based on the clock signal, and puts the other in a floating state.

  In the image data IV conversion circuit 21, the switch S1 is fixed so that the source of the transistor Qn8 is always connected to the ground electrode GND3. Then, a current is passed through the wiring connected to the ground electrode among the wirings 4a and 4b by the same operation as in the first embodiment. As a result, the image data, which is a voltage signal, is converted into a pair of complementary current signals and received, and the current signal is converted again into a voltage signal to regenerate the image data. Similarly, the clock signal IV conversion circuit 22 receives the clock signal and regenerates it.

  At this time, as shown in FIG. 11, the frequency of the image data and the clock signal varies depending on the amount of image data to be transmitted. For example, in the color reduction mode, the frequency is reduced. As shown in FIG. 12, if the frequency of the current signal to be transmitted is low, the constant current value necessary for transmitting this current signal is low. In the present embodiment, when the display mode is a mode with a small amount of image data such as a subtractive color mode, the image data IV conversion circuit 21 and the clock signal IV conversion circuit 22 are determined by the receiver control signal. Reduce the current value. For example, in the image data IV conversion circuit 21, the receiver control signal is input to the current detection unit 27 via the bias terminal T2. Thus, the constant current value of the image data IV conversion circuit 21 can be adjusted. Subsequent steps are the same as those in the first embodiment.

  In the present embodiment, the timing control circuit 7c adjusts the frequency of the image data and the clock signal according to the amount of image data, and based on this frequency, the image data IV conversion circuit 21 and the clock signal IV When the conversion circuit 22 adjusts the constant current value, the constant current value can be lowered when the amount of image data is small. Thereby, power consumption can be reduced.

  In this embodiment, as shown in the third embodiment, the image data amount may be reduced by encoding the image data.

  Next, a fifth embodiment of the present invention will be described. FIG. 13 is a block diagram illustrating the liquid crystal display device according to the present embodiment. As shown in FIG. 13, the present embodiment is an example in which a plurality of source drivers 2d are provided in one liquid crystal display device. The present applicant has developed a technique for sequentially transmitting a drive signal between receivers as a technique for efficiently driving a plurality of receivers, and disclosed in Japanese Patent Application Laid-Open No. 2002-026231. The present embodiment is an example in which this technique is combined with the present invention. In the liquid crystal display device according to the present embodiment, one display controller 1, a plurality of source drivers 2d, and one liquid crystal panel 3 are provided. In addition, although wiring 4a, 4b, 5a, 5b, 11 is provided between the display controller 1 and the source driver 2d, in FIG. 13, only wiring 4a and 11 are shown, and wiring 4b, 5a, Illustration of 5b is omitted. The arrangement positions of the wirings 4b, 5a, and 5b are the same as those of the wiring 4a. Each source driver 2d drives pixels in a column of the liquid crystal panel 3 and displays an image. The display controller 1 outputs image data, a clock signal, and a receiver control signal to the plurality of source drivers 2d in parallel. Further, the display controller 1 outputs a signal STH for starting the operation of the shift resist 23 (see FIG. 1) only to the source driver 2d disposed at the position closest to the display controller 1. The source driver 2d to which the signal STH is input outputs the signal STH to the source driver 2d arranged next to the source driver 2d. In this way, the signal STH is sequentially input to all the source drivers 2d. The other configuration of the liquid crystal display device according to the present embodiment is the same as that of the liquid crystal display device according to the first embodiment.

  Next, a method for driving the liquid crystal display device according to this embodiment will be described. Based on the image data, the display controller 1 makes one of the wirings 4a and 4b float and connects the other to the ground electrode by the same method as in the first embodiment. Further, based on the clock signal, one of the wirings 5a and 5b is brought into a floating state, and the other is connected to the ground electrode. Thereby, the display controller 1 outputs image data and a clock signal simultaneously to all the source drivers 2d.

  Further, the display controller 1 outputs a signal STH to the 1 source driver 2d. Then, the source driver 2d to which the signal STH is input starts its operation and displays an image on a predetermined column of the liquid crystal panel 3 based on the input image data. At this time, the other source driver 2d is in a stopped state and does not drive the liquid crystal panel 3 even if image data is input.

  When all the necessary image data is input to the one source driver 2d, the source driver 2d outputs a signal STH to the other one source driver 2d arranged adjacent to the source driver 2d. To stop. As a result, the source driver 2d to which the signal STH is newly input starts its operation, and drives the liquid crystal panel 3 based on the image data. Further, the signal STH is output to the adjacent source driver 2d, and the operation stops itself. In this way, all the source drivers 2d are sequentially operated one by one to drive the liquid crystal panel 3. Thereby, an image is displayed as the whole liquid crystal panel 3. Operations other than those described above in the present embodiment are the same as those in the first embodiment described above.

  In the present embodiment, even when a plurality of source drivers are provided, a correct image can be displayed without the same image data being taken into the plurality of source drivers. The effects of the present embodiment other than those described above are the same as the effects of the first embodiment described above.

  Next, a sixth embodiment of the present invention will be described. FIG. 14 is a block diagram showing a plasma display panel (PDP) according to the present embodiment. In this embodiment, the present invention is applied to a PDP.

  As shown in FIG. 14, in the PDP according to the present embodiment, a video signal processing circuit 51, a data driver 52, and a panel 53 are provided. A pair of wirings 54 a and 54 b is provided between the video signal processing circuit 51 and the data driver 52. In the video signal processing circuit 51, an inverse gamma processing block 32, an error diffusion or dither block 33, an average luminance level calculation block 34, an SF coding block 35, a frame memory 36, a drive control block 37, and a VI conversion circuit 43 are provided. It has been. In the data driver 52, an IV conversion circuit 44 and an internal circuit 45 are provided. The VI conversion circuit 43 is connected to one ends of the wirings 54a and 54b, and the IV conversion circuit 44 is connected to the other ends of the wirings 54a and 54b. The configuration of the VI conversion circuit 43 is the same as that of the image data VI conversion circuit 8 (see FIG. 2) in the first embodiment, and the configuration of the IV conversion circuit 44 is the same as that of the first embodiment. This is the same as the image data IV conversion circuit 21 (see FIG. 3) in the first embodiment. Further, the output signal of the drive control block 37 is input to the panel 53.

Next, a method for driving the PDP according to the present embodiment will be described. First, as shown in FIG. 14, image data 31 that is a video signal such as a TV video or a PC screen is input to an inverse gamma processing block 32. The inverse gamma processing block 32 increases the gradation resolution of this video signal. For example, the video signal is input to the inverse gamma processing block 32 as a signal having gradations of 8 bits for R, B, and G, and the inverse gamma processing block 32 nonlinearly converts the video signal into a form of y = x ^2.2. Convert. At this time, if the input gradation accuracy and the output gradation accuracy are the same, the input image with a small gradation value, for example, gradation values 0, 2, 5, etc. are all 0, and the gradation difference can be expressed. Therefore, gradation degradation occurs. In order to prevent this gradation deterioration, the output of the inverse gamma processing block 32 is generally 10 bits. The inverse gamma processing block 32 outputs the output signal (10 bits) to the error diffusion or dither block 33. For example, the error diffusion or dither block 33 spatially diffuses the lower 2 bits of the 10-bit gradation resolution of the input video signal and outputs the result as an 8-bit signal. The video signal that has been subjected to inverse gamma processing and error diffusion or dither processing is input to an average luminance level calculation block 34, which calculates an average picture level (APL) value 38 of the video. And output to the drive control block 37 and the SF coding block 35.

  The drive control block 37 converts the APL value 8 into the number of sustain pulses that determines the luminance of the video, and outputs the sustain pulse output 41 to the panel 53. Further, the subfield (SF) coding block 35 converts the video signal into SF coding data and outputs it to the frame memory 36 in order to perform gradation expression on the panel 53. Generally, an 8-bit video signal is converted into 12 SF data. The frame memory 36 converts the 12 SF data into a video signal output 42 and outputs the video signal output 42 to the V-I conversion circuit 43. Based on the video signal output 42 which is a binary voltage signal, the VI conversion circuit 43 connects one of the pair of wirings 54a and 54b to a ground electrode (not shown) and the other is in a floating state. And

  The IV conversion circuit 44 of the data driver 52 allows a current to flow through the wiring connected to the ground electrode among the pair of wirings 54a and 54b. As a result, the IV conversion circuit 44 converts the video signal output 42 into a pair of complementary current signals and receives them, converts the current signals into voltage signals, and regenerates the video signal output 42. When the video signal output 42 is not transmitted, the current signal is stopped. Then, the IV conversion circuit 44 outputs the regenerated video signal output 42 to the internal circuit 45.

  Next, the internal circuit 45 adjusts the transfer timing and transfer speed of the video signal output 42 and transfers it to a data driver (not shown) of the panel 53. As a result, the panel 53 generates a write discharge in each display cell (not shown) of the panel 53 based on the video signal output 42 to write the wall charges, thereby emitting / not emitting light from each display cell. decide. On the other hand, sustain pulse output 41 is transferred to a sustain driver (not shown) of panel 53 to determine the number of sustain discharge pulses after write discharge in each display cell. Usually, since the pulse interval is constant, the number of pulses of each SF (subfield) corresponds to the light emission time of each SF. Thereby, the luminance of each display cell is controlled. In this manner, the panel 53 is driven by the video signal output 42 and the sustain pulse output 41 to display the video.

  In this embodiment, the V-I conversion circuit and the I-V conversion circuit, which are the features of the present invention, are used for transferring the video signal output from the video signal processing circuit 51 to the data driver 52. As a result, high-speed data transfer can be realized and power consumption can be reduced. Unlike the liquid crystal display device, the data writing time does not contribute to the luminance of the PDP, so that the data writing can be speeded up within a range where no writing failure occurs. That is, the data writing speed can be increased until a writing failure to the panel occurs, and the data writing speed is determined by the performance of the panel. However, in the low order SF, even if there are some write defects, it is not noticeable, so that write defects can be allowed to some extent and high speed writing can be performed.

  In the PDP, unlike the liquid crystal display device, data is transferred for each SF. Therefore, by using the method shown in the third embodiment, data for 1SF can be compared and encoded to reduce the amount of data. In particular, the data of the upper SF does not change greatly even in a natural image, so that the data amount can be effectively reduced.

  In the PDP, the writing time (transfer time) and the light emission time are set separately. Therefore, data transfer is not performed in a time other than the transfer time, that is, in the sustain period and the preliminary discharge period. Therefore, since the receiver (IV conversion circuit) can be stopped during these times, the effect of reducing power consumption is great.

  In the PDP, the number of pixels driven by one data driver is usually 256 or 192, for example. If the number of pixels in one line of the panel is 640 × 3 colors, ten data drivers for driving 192 pixels are required. Therefore, it is preferable to transfer data in parallel to the ten data drivers by the method shown in the fifth embodiment.

  In the first to sixth embodiments described above, an example in which the present invention is applied to a liquid crystal display device or a PDP has been shown. However, the present invention is not limited to this, and other matrix type displays such as an organic EL display panel. It is also possible to apply to an apparatus.

1 is a block diagram illustrating a liquid crystal display device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a V-I conversion circuit for image data of the liquid crystal display device shown in FIG. FIG. 2 is a circuit diagram showing an image data IV conversion circuit of the liquid crystal display device shown in FIG. 1. 4 is a timing chart illustrating a driving method of the liquid crystal display device according to the embodiment. 4 is a timing chart showing operations of an image data V-I conversion circuit and an image data I-V conversion circuit of the liquid crystal display device according to the embodiment. It is a block diagram which shows the liquid crystal display device based on the 2nd Example of this invention. 4 is a timing chart illustrating a driving method of the liquid crystal display device according to the embodiment. It is a block diagram which shows the liquid crystal display device which concerns on the 3rd Example of this invention. 4 is a timing chart illustrating a driving method of the liquid crystal display device according to the embodiment. It is a block diagram which shows the liquid crystal display device which concerns on the 4th Example of this invention. 4 is a timing chart illustrating a driving method of the liquid crystal display device according to the embodiment. The maximum frequency fmax of the current signal to be transmitted is taken on the horizontal axis, and the constant current value necessary for transmitting the current signal of this maximum frequency is taken on the vertical axis to show the relationship between the maximum frequency of the current signal and the necessary current. FIG. It is a block diagram which shows the liquid crystal display device which concerns on the 5th Example of this invention. It is a block diagram which shows the plasma display panel (PDP) based on the 6th Example of this invention. It is a block diagram which shows the conventional liquid crystal display device to which CMADS is applied.

Explanation of symbols

1, 1a, 1b, 1c; Display controller 2, 2a, 2d; Source driver 3; Liquid crystal panel 4a, 4b, 5a, 5b, 11; Wiring 6; Display data memory 7, 7a, 7b, 7c; Timing control circuit 8 Image data VI conversion circuit 9; clock signal VI conversion circuit 10; mode register 12; data comparison circuit 21; image data IV conversion circuit 22; clock signal IV conversion circuit 23; Shift register 24; data latch circuit 25; gradation selection circuit 26; output circuit 27; current detection unit 28; potential control unit 29; RS latch circuit 30; CLK stop detection circuit 31; Error diffusion or dither block 34; average luminance level calculation block 35; SF coding block 36; Memory 37; drive control block 38; average picture level (APL) value 41; sustain pulse output 42; video signal output 43; V-I conversion circuit 44; IV conversion circuit 45; internal circuit 51; Signal processing circuit 52; data driver 53; panels 54a and 54b; wiring 101; display controller 102; source driver 103; liquid crystal panels 104a, 104b, 105a and 105b; wiring 106; display data memory 107; timing control circuit 108; VI conversion circuit 109; clock signal VI conversion circuit 121; image data IV conversion circuit 122; clock signal IV conversion circuit 123; shift register 124; data latch circuit 125; gradation selection Circuit 126; output circuit GND1, GND , GND3; ground electrodes INV1, INV2, INV3; inverters NAND1, NAND2; NAND gates Na, Nb, Nc, Nd; nodes Qn1-Qn10; N-channel MOS transistors Qp1-Qp8; P-channel MOS transistors S1; switch STH; Signal T1, T3, T4, T5; input terminal T2; bias terminal T6; output terminals VDD1, VDD2; power supply electrode

Claims (1)

A drive signal is generated based on image data wiring, a display controller connected to one end of the image data wiring, and image data connected to the other end of the image data wiring and sent to the image data wiring A display driver that displays an image based on the drive signal, and the display controller normally displays the image based on the image data having a predetermined amount of data for each pixel. The frequency of the image data is adjusted according to the image display mode that designates the mode or the color reduction mode in which the image display is performed based on the image data in which the data amount for each pixel is smaller than the normal mode. The display controller outputs a control signal in accordance with an image display mode; and the image data is based on the control signal. A timing control circuit that sequentially outputs at an adjusted frequency and outputs a receiver control signal indicating the display mode of the image, and the source driver is based on the display mode of the image indicated by the receiver control signal. A drive signal is generated, and one or more pairs of the image data wirings are provided, and the display controller connects one of each pair of the image data wirings to a reference potential terminal based on the image data. And an image data switching control circuit in which the other is in a floating state, and the source driver causes a pair based on the image data to flow through a wiring connected to the reference potential terminal among the wiring for the image data. Alternatively, a plurality of pairs of complementary current signals are generated, a drive signal is generated based on these current signals, and the reception signal is generated. Display device comprising in accordance with the display mode of the image control signal indicates is for controlling the magnitude of current to be supplied to the image data lines.

Images