JP4699029B2 - 自動試験装置のためのシリコン・オン・インシュレータ・チャネルアーキテクチャ - Google Patents
自動試験装置のためのシリコン・オン・インシュレータ・チャネルアーキテクチャ Download PDFInfo
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- JP4699029B2 JP4699029B2 JP2005000111A JP2005000111A JP4699029B2 JP 4699029 B2 JP4699029 B2 JP 4699029B2 JP 2005000111 A JP2005000111 A JP 2005000111A JP 2005000111 A JP2005000111 A JP 2005000111A JP 4699029 B2 JP4699029 B2 JP 4699029B2
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- 238000012360 testing method Methods 0.000 title claims description 50
- 239000012212 insulator Substances 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 14
- 230000004044 response Effects 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 4
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- 230000015556 catabolic process Effects 0.000 description 7
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
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Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31924—Voltage or current aspects, e.g. driver, receiver
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Description
また、デューティサイクル補償回路は、以下のより詳細な説明および添付図面を参照してよりよく理解されるであろう。
Claims (11)
- 自動試験装置で用いるためのチャネルアーキテクチャであって、
パターン発生回路と、
該パターン発生回路に応答して、タイミング信号を生成するタイミング回路と、
該タイミング回路の出力に結合され、パルス波形を生成するフォーマッティング回路と、
該フォーマッティング回路に応答して、前記自動試験装置を被試験デバイスにインタフェースするピンエレクトロニクス回路と、を備え、
前記パターン発生回路、前記タイミング回路、前記フォーマッティング回路、および前記ピンエレクトロニクス回路が、共通バルク接続のないスタックされたトランジスタを用いて、同じ集積回路チップ上に形成され、
電源電圧が前記スタックされたトランジスタ間に均等に分割される、
チャネルアーキテクチャ。 - 前記集積回路は、シリコン・オン・インシュレータプロセスによって形成される請求項1に記載のチャネルアーキテクチャ。
- 前記パターン発生回路、前記タイミング回路、および前記フォーマッティング回路は、1ボルトを超えない電圧レベルで動作する低電圧デジタル回路から構成される請求項1または2に記載のチャネルアーキテクチャ。
- 前記ピンエレクトロニクス回路は、1ボルトを超える電圧で動作する高電圧アナログ回路から構成される請求項1〜3のいずれかに記載のチャネルアーキテクチャ。
- 前記トランジスタが、二酸化シリコンの薄い層の上部に形成されるソース端子、ゲート端子、およびドレーン端子を含む半導体層を有する、請求項1に記載のチャネルアーキテクチャ。
- 半導体デバイスを試験する自動試験装置であって、
コントローラと、
複数のチャネルカードを収容するように適応された試験ヘッドであって、各チャネルカードが複数の集積回路チップを備え、各チップが、請求項1〜5のいずれかに記載のチャネルアーキテクチャを有する試験ヘッドと、
を備えた自動試験装置。 - 半導体デバイスを製造する方法において、
集積回路チップを形成するステップであって、各集積回路チップが共通バルク接続のないスタックされたトランジスタを含み、該スタックされたトランジスタが、パターン発生回路と、該パターン発生回路に応答してタイミング信号を生成するタイミング回路と、該タイミング回路の出力に結合されてパルス波形を生成するフォーマッティング回路と、該フォーマッティング回路に応答して前記自動試験装置を被試験デバイスにインタフェースするピンエレクトロニクス回路と、を形成し、電源電圧が前記スタックされたトランジスタ間に均等に分割され、
コントローラと、複数のチャネルカードを収容するように適応された試験ヘッドとを備える自動試験装置を選択するステップであって、各チャネルカードは複数の集積回路チップ備える、ステップと、
前記半導体デバイスを前記選択された自動試験装置を用いて試験するステップと、
を含む半導体デバイスを製造する方法。 - 各チップは、シリコン・オン・インシュレータプロセスによって形成される請求項7に記載の半導体デバイスを製造する方法。
- 前記パターン発生回路、タイミング回路、およびフォーマッティング回路を形成して、1ボルトを超えない電圧レベルで動作可能な低電圧デジタル回路を構成することを更に含む、請求項7に記載の半導体デバイスを製造する方法。
- 前記ピンエレクトロニクス回路を形成して、1ボルトを超える電圧レベルで動作可能な高電圧アナログ回路を構成することを更に含む、請求項8に記載の半導体デバイスを製造する方法。
- 前記集積回路チップのそれぞれを形成して、二酸化シリコンの薄い層の上部に形成されるソース端子、ゲート端子、およびドレーン端子を含む半導体層を有するトランジスタを含む、請求項7に記載の半導体デバイスを製造する方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/749,266 US6853181B1 (en) | 2003-12-31 | 2003-12-31 | Silicon-on-insulator channel architecture for automatic test equipment |
US10/749266 | 2003-12-31 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005195599A JP2005195599A (ja) | 2005-07-21 |
JP4699029B2 true JP4699029B2 (ja) | 2011-06-08 |
Family
ID=34104875
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Application Number | Title | Priority Date | Filing Date |
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JP2005000111A Active JP4699029B2 (ja) | 2003-12-31 | 2005-01-04 | 自動試験装置のためのシリコン・オン・インシュレータ・チャネルアーキテクチャ |
Country Status (4)
Country | Link |
---|---|
US (2) | US6853181B1 (ja) |
JP (1) | JP4699029B2 (ja) |
MY (1) | MY139343A (ja) |
TW (1) | TWI262540B (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6853181B1 (en) * | 2003-12-31 | 2005-02-08 | Teradyne, Inc. | Silicon-on-insulator channel architecture for automatic test equipment |
TWI336061B (en) * | 2006-08-10 | 2011-01-11 | Au Optronics Corp | Display apparatus and enable circuit thereof |
US7768278B2 (en) * | 2007-02-14 | 2010-08-03 | Verigy (Singapore) Pte. Ltd. | High impedance, high parallelism, high temperature memory test system architecture |
US7348791B1 (en) | 2007-03-14 | 2008-03-25 | Silicon Test System, Inc. | High voltage, high frequency, high reliability, high density, high temperature automated test equipment (ATE) switch design |
US9577818B2 (en) * | 2015-02-04 | 2017-02-21 | Teradyne, Inc. | High speed data transfer using calibrated, single-clock source synchronous serializer-deserializer protocol |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001512838A (ja) * | 1997-08-05 | 2001-08-28 | テラダイン・インコーポレーテッド | 高いチャネル密度を有する低コストcmosテスタ |
JP2002214306A (ja) * | 2001-01-15 | 2002-07-31 | Hitachi Ltd | 半導体集積回路 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3129077B2 (ja) * | 1994-03-07 | 2001-01-29 | 株式会社日立製作所 | 半導体試験装置 |
EP0811167B1 (en) | 1995-02-23 | 2001-09-05 | Aesop Inc. | Manipulator for automatic test equipment test head |
US6469493B1 (en) * | 1995-08-01 | 2002-10-22 | Teradyne, Inc. | Low cost CMOS tester with edge rate compensation |
US6023173A (en) | 1997-04-30 | 2000-02-08 | Credence Systems Corporation | Manipulator with expanded range of motion |
US6005408A (en) * | 1997-07-31 | 1999-12-21 | Credence Systems Corporation | System for compensating for temperature induced delay variation in an integrated circuit |
US6853181B1 (en) * | 2003-12-31 | 2005-02-08 | Teradyne, Inc. | Silicon-on-insulator channel architecture for automatic test equipment |
US6671845B1 (en) * | 1999-10-19 | 2003-12-30 | Schlumberger Technologies, Inc. | Packet-based device test system |
US6567031B1 (en) * | 1999-11-17 | 2003-05-20 | Ikanos Communication, Inc. | A/D multi-channel architecture |
US6660598B2 (en) * | 2002-02-26 | 2003-12-09 | International Business Machines Corporation | Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region |
-
2003
- 2003-12-31 US US10/749,266 patent/US6853181B1/en not_active Expired - Lifetime
-
2004
- 2004-12-10 US US11/009,928 patent/US7088092B2/en not_active Expired - Lifetime
- 2004-12-21 TW TW093139805A patent/TWI262540B/zh active
- 2004-12-24 MY MYPI20045354A patent/MY139343A/en unknown
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2005
- 2005-01-04 JP JP2005000111A patent/JP4699029B2/ja active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001512838A (ja) * | 1997-08-05 | 2001-08-28 | テラダイン・インコーポレーテッド | 高いチャネル密度を有する低コストcmosテスタ |
JP2002214306A (ja) * | 2001-01-15 | 2002-07-31 | Hitachi Ltd | 半導体集積回路 |
Also Published As
Publication number | Publication date |
---|---|
US20050158890A1 (en) | 2005-07-21 |
JP2005195599A (ja) | 2005-07-21 |
MY139343A (en) | 2009-09-30 |
US6853181B1 (en) | 2005-02-08 |
TWI262540B (en) | 2006-09-21 |
TW200534344A (en) | 2005-10-16 |
US7088092B2 (en) | 2006-08-08 |
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