JP4697668B2 - Ferroelectric memory device, display driver IC and electronic device - Google Patents

Description

  The present invention relates to a ferroelectric memory device, a display driving IC, and an electronic device.

  Ferroelectric Random Access Memory (FeRAM) devices store information using hysteresis characteristics that are found between the polarization and electric field of ferroelectric materials, and have high speed and low power consumption. It attracts attention from the viewpoints of safety and non-volatility.

  In such a ferroelectric memory device, like other memory devices, high integration or downsizing of memory cells is a permanent issue.

For example, the following Patent Document 1 (Japanese Patent Laid-Open No. 2002-170935) describes a ferroelectric memory in which active regions connected to a predetermined bit line are arranged in a line along the bit line. Further, a technique for reducing the area of the ferroelectric memory cell by devising the shape and arrangement of the word line and the active region is disclosed.
JP 2002-170935 A

  However, the conventional ferroelectric memory configuration has a problem that the length of the bit line (direction) becomes long and the size of the ferroelectric memory becomes large.

  On the other hand, the ferroelectric memory has come to be used in various electronic devices due to its characteristics such as high speed, low power consumption and non-volatility. For example, in a display driver IC used in a display device, as will be described in detail later, the wiring interval is larger than a normal design rule (for example, the minimum wiring interval) due to the connection with a display body or the like. May be set.

  Accordingly, it is necessary to increase the integration density of memory cells while complying with an allowable wiring interval as well as to increase the integration density or reduce the size of the ferroelectric memory device.

  Accordingly, an object of the present invention is to provide a ferroelectric memory device, a display driving IC, and the like that can solve the above-described problems.

  That is, it is an object to achieve high integration or downsizing of the ferroelectric memory device. In particular, an object is to provide a ferroelectric memory device having a high degree of integration in the bit line direction. Another object of the present invention is to achieve high integration or downsizing (optimization of layout) of a ferroelectric memory device used in a display driving IC (integrated circuit). In particular, it is an object to improve the degree of integration in the bit line direction of a ferroelectric memory device used in a display driver IC.

  This object is achieved by a combination of the features described in the claims.

  To achieve the above object, a ferroelectric memory device according to a first aspect of the present invention includes a first word line extending in a first direction and a second word line extending in a first direction. And an element region disposed between the first word line and the second word line, a bit line extending in a second direction orthogonal to the first direction and connected to the element region, The first word line has a first branch line extending in the direction of the second word line, and the second word line extends in the direction of the first word line A first branch line including a first gate electrode of a transistor disposed in the element region; a second branch line including a second gate electrode of the transistor disposed in the element region; The first word line side end of the element region intersecting with the first gate electrode is defined as the first end, and the element region intersecting with the first gate electrode The end on the second word line side of the region is the second end, the distance from the first end to the first word line is the first distance, and the second word from the second end When the distance to the line is the second distance, the first distance is smaller than the second distance, and the end of the element region intersecting the second gate electrode on the second word line side is the third distance. The end of the element region intersecting the second gate electrode on the first word line side is the fourth end, and the distance from the third end to the second word line is the third And the distance from the fourth end to the first word line is the fourth distance, the third distance is smaller than the fourth distance, and the element region has a stepped shape in plan view. The first end portion and the fourth end portion are shifted from each other in the second direction, form a step shape in plan view, and the second end portion and the third end portion are the second end portions. In the direction of It is arranged, and wherein the forming a stepped shape in plan view.

  According to the above aspect, since the distance between the word lines in the second direction can be shortened, a ferroelectric memory device having a short length in the second direction can be provided.

  The ferroelectric memory device according to the second aspect of the present invention includes a first word line extending in a first direction, a second word line extending in the first direction, and a first word line. An element region disposed between the first word line and the second word line, and a bit line extending in a second direction orthogonal to the first direction and connected to the element region, the first word The line has a first branch line extending in the direction of the second word line, the second word line has a second branch line extending in the direction of the first word line, The second branch line includes a first gate electrode of the transistor disposed in the element region, and the second branch line includes a second gate electrode of the transistor disposed in the element region, and intersects with one side of the element region. The second word line of the second gate electrode that intersects one side, with the end of the first gate electrode on the second word line side being the first end Is the second end, the distance from the first end to the second word line is the first distance, and the distance from the second end to the second word line is the second distance. In the case of the distance, the first distance is larger than the second distance, and the second word line has a bent shape that bypasses the first branch line.

  According to the above aspect, since the distance between the word lines in the second direction can be reduced, it is possible to provide a ferroelectric memory device having a shorter length in the second direction.

  The ferroelectric memory device includes a first transistor including a first gate electrode and a second transistor including a second gate electrode as transistors in the element region, the first transistor including: One of the source and the drain is connected to the bit line, the other of the source and the drain of the first transistor is connected to the first ferroelectric capacitor, and one of the source and the drain of the second transistor is connected to the bit line. The other of the source and the drain of the second transistor is connected to the second ferroelectric capacitor.

  In the above ferroelectric memory device, it is preferable that the first ferroelectric capacitor and the second ferroelectric capacitor have a width in the first direction larger than a width in the second direction.

  According to the above configuration, since the first and second ferroelectric capacitors have a pattern in which the width in the first direction is larger than the width in the second direction, the amount of charge that can be accumulated in the ferroelectric capacitor is increased. Write and read margins are increased. In addition, writing and reading characteristics are improved.

  The ferroelectric memory device may further include a plate line connected to either the first ferroelectric capacitor or the second ferroelectric capacitor.

  According to the above configuration, the first ferroelectric capacitor and the second ferroelectric capacitor connected to one plate line are driven by different word lines, so that the length in the second direction is long. A ferroelectric memory device capable of accessing a desired ferroelectric capacitor while reducing the length can be provided.

  In the above ferroelectric memory device, the plate line extends in the first direction, and the first element region and the second element region are arranged as element regions on both sides of the first word line. The first ferroelectric capacitor connected to the first element region and the second ferroelectric capacitor connected to the second element region are connected to the same plate line. Also good.

  According to the above configuration, the first ferroelectric capacitor and the second ferroelectric capacitor connected to one plate line are driven by different word lines, and the plate lines can be provided in a substantially linear shape. Therefore, the load on the plate wire can be reduced.

  In the ferroelectric memory device, the plate line extends in the second direction, and the first element region and the second element region are arranged as element regions on both sides of the first word line. In addition, the first ferroelectric capacitor connected to the first element region and the second ferroelectric capacitor connected to the second element region may be connected to the same plate line.

  According to the above configuration, since the plate line is extended in the second direction with respect to the ferroelectric memory device having a short length in the second direction, the plate line becomes short and the load on the plate line can be reduced. it can.

  A display driver IC according to the present invention provides a display driver IC comprising the ferroelectric memory device. The display driving IC refers to all devices that drive a display device such as a liquid crystal display device.

  An electronic apparatus according to the present invention comprises the ferroelectric memory device described above. The electronic device generally refers to a device having a certain function provided with the ferroelectric memory device according to the present invention, and its configuration is not particularly limited. For example, a computer device generally provided with the ferroelectric memory device is generally described. Any device that requires a storage device, such as a mobile phone, PHS, PDA, electronic notebook, and IC card, is included.

  Hereinafter, the present invention will be described through embodiments of the invention with reference to the drawings. However, the following embodiments do not limit the invention according to the scope of claims, and will be described in the embodiments. Not all of the feature combinations described are essential for the solution of the invention. In addition, the same or related code | symbol is attached | subjected to what has the same function, and the repeated description is abbreviate | omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a display driving IC according to the present embodiment. The display driving IC includes a ferroelectric memory device, a latch circuit 150, and a display driving circuit 160. The ferroelectric memory device includes a memory cell array 110, a plurality of word lines WL, a plurality of plate lines PL, a plurality of bit lines BL, a word line control unit 120, a plate line control unit 130, and a bit line control. Unit 140.

  As will be described later, the memory cell array 110 includes a plurality of memory cells MC arranged in an array. Each memory cell MC is connected to one of the word lines WL, the plate line PL, and the bit line BL. Then, the word line control unit 120 and the plate line control unit 130 control the voltages of the plurality of word lines WL and the plurality of plate lines PL, read the data stored in the memory cells MC to the plurality of bit lines BL, and The data supplied from the outside is stored in the memory cell MC through the bit line BL. The latch circuit 150 latches data read from the memory cell MC, and the display driving circuit 160 drives an external display body based on the data latched by the latch circuit 150.

  Here, the external display body is, for example, a display device such as a liquid crystal display device. For example, each cell constituting a display body of a liquid crystal display device has a switching transistor (TFT: thin film transistor) and a pixel electrode sandwiching liquid crystal, and is arranged in an array. Therefore, in order to drive these cells (pixels), a driving IC connected to the gate line or source line of each TFT is required. The wiring interval of such gate lines and source lines is often set wider than the bit line interval of a normal memory cell array. For example, the interval is 1 to 1.3 times.

  Here, it is conceivable to directly connect a plurality of wirings of the display body to a plurality of wiring parts having a smaller interval in the memory cell array, but wiring of the wirings for connection becomes complicated, and wiring connection failure may occur. . Further, when the bit lines are formed in accordance with the plurality of wiring pitches of the display body, the wiring connection defects are reduced, but the memory cell array becomes larger as the bit line interval is increased. In view of this, it is important to provide a technology for achieving high integration of memory cells while complying with an allowable wiring interval.

  FIG. 2 is a circuit diagram showing a configuration of the memory cell array 110 of the present embodiment. FIG. 2 shows a configuration of the memory cells MC1 to MC4 which are repetitive units in the memory cell array 110. In the memory cell array 110, memory cells MC1 to MC4 are repeatedly arranged in the extending direction of the word lines WL and the extending direction of the bit lines BL.

  Each of the memory cells MC1 to MC4 includes a ferroelectric capacitor 170 and an NMOS (n-channel MOS: Metal Oxide Semiconductor, n-channel MISFET: Metal Insulator Semiconductor Field Effect Transistor) 172. In the memory cells MC1 to MC4, the NMOS 172 has one of its source and drain regions connected to the bit line BL, and the other connected to one end of the ferroelectric capacitor 170. Note that a source / drain region refers to a region which serves as a source or a drain of a transistor.

  The NMOS 172 has a gate connected to the word line WL, and switches whether to connect one end of the ferroelectric capacitor 170 to the corresponding bit line BL according to the voltage of the word line WL. The other end of the ferroelectric capacitor 170 is connected to the corresponding plate line PL.

  Specifically, in the memory cell MC1, the NMOS 172 has one of its source and drain regions connected to the bit line BL1, its gate connected to the word line WL1, and the other end of the ferroelectric capacitor 170 connected to the plate. Connected to line PL1. In the memory cell MC2, the NMOS 172 has one of its source and drain regions connected to the bit line BL1, its gate connected to the word line WL3, and the other end of the ferroelectric capacitor 170 connected to the plate line PL2. It is connected. In the memory cell MC3, the NMOS 172 has one of its source and drain regions connected to the bit line BL2, its gate connected to the word line WL1, and the other end of the ferroelectric capacitor 170 connected to the plate line PL2. It is connected. In the memory cell MC4, the NMOS 172 has one of its source and drain regions connected to the bit line BL2, its gate connected to the word line WL2, and the other end of the ferroelectric capacitor 170 connected to the plate line PL1. It is connected.

  FIG. 3 is a plan view showing the memory cell array 110 of the present embodiment. FIG. 4 is a cross-sectional view of a main part of the memory cell array 110 according to the present embodiment. 4A shows the AA cross section in FIG. 3, and FIG. 4B shows the BB cross section in FIG. 5 to 9 are main part plan views showing partial patterns of the layout of the memory cell array 110 shown in FIG.

  Hereinafter, the configuration of the memory cell array of the present embodiment will be described in detail with reference to FIGS. 3 to 9. First, main features of the present embodiment will be described with reference to FIG. FIG. 10 is a schematic plan view showing the memory cell array 110 of the present embodiment.

  As shown in FIG. 10, the element region 112 is a substantially rectangular region having a long side in the x direction, and a plurality of the element regions 112 are arranged at a constant interval in the x direction. In this element region, two memory cells (two transistors and two ferroelectric capacitors) are formed.

  The plurality of element regions 112 are so-called staggered. In other words, when a plurality of element regions 112 arranged in the x direction are element region rows, the element region rows in the A arrangement and the element region rows in the B arrangement are alternately arranged in the y direction. The element region row of A arrangement means, for example, an element region row including the element region 112 in which the memory cell MC2 of FIG. 10 is formed, and the element region row of B arrangement is arranged with a starting point shifted by a predetermined distance. Means an element region row (for example, an element region row including the element region 112 in which the memory cell MC3 is formed).

  Here, the trunk lines of the word lines WL are arranged in the x direction between the element region rows. As will be described in detail later, this word line WL has a branch line, and this branch line extends in the y direction on the element region 112 from the main line.

  The bit line BL extends in a direction (y direction) orthogonal to each element region 112 and is connected to the source and drain regions of the NMOS 172 constituting the memory cell MC.

  In the present embodiment, since the two NMOS 172 and the two ferroelectric capacitors 170 are formed in the element region 112, the element region 112 is substantially connected to the common source and drain regions of the two NMOS 172. Bit lines BL are arranged so as to cross over the central portion.

  Here, the memory cells MC arranged on the right side of the bit line BL in each element region row are connected to the same word line WL (word line WL located in the lower part of the drawing), and the bit line BL is shown in FIG. The memory cells arranged in the middle left are connected to the same word line WL (word line WL located in the upper part in the drawing).

  In other words, the word line WL between the element region rows is connected to one (for example, the left side in the drawing) of the memory cells MC formed in the element region 112 on both sides (upper and lower in the drawing). Further, the word line WL adjacent to the word line WL is connected to the other (for example, the right side in the figure) among the memory cells MC formed in the element regions 112 on both sides (upper and lower parts in the figure). .

  In other words, adjacent memory cells (for example, MC2 and MC3) between the same bit lines BL are driven by different word lines WL.

  Here, the main features of the present embodiment are summarized.

  First, the first feature is that the longitudinal direction of the element region 112 is arranged in a direction orthogonal to the bit line BL (x direction, parallel to the word line WL). In addition, two memory cell columns are arranged between the bit lines BL. Further, the memory cell columns are arranged on both sides of the bit line BL. The memory cell column means a plurality of memory cells arranged in the y direction. For example, on both sides of the bit line BL, a memory cell column including the memory cell MC2 and a memory cell column including the memory cell MC1 are arranged. A memory cell column including the memory cell MC2 and a memory cell column including the memory cell MC3 are arranged between the bit lines.

  Thus, according to the present embodiment, memory cells can be efficiently arranged between the bit lines BL. In particular, when the space between the bit lines BL is wider than usual, the memory cells can be arranged efficiently.

  A second feature of the present embodiment is that a branch line is provided for the word line WL and connected to a memory cell on the element region 112. Even if the longitudinal direction of the element region is arranged in parallel with the word line WL, the memory cell can be driven by the branch line of the word line WL.

  The third feature of the present embodiment is that the element regions are arranged in a staggered manner as described above. By staggered arrangement, the element regions in the y direction can be reduced. In addition, it is possible to secure an arrangement area for the word line (main line) WL.

  In addition, as described above, the fourth feature of the present embodiment is that the connection between each memory cell and the word line WL is devised. As will be described later, 1) the word line WL is extended while being bent. 2) Or, by making the shape of the element region Z-shaped, the space between the element regions in the y direction can be further reduced. That is, the arrangement of each memory cell can be optimized.

  Next, the configuration of the memory cell array according to the present embodiment will be described in detail with reference to FIGS. In addition, in order to make the drawings easy to understand, the plan view is also appropriately hatched.

  As shown in FIG. 3 and the like, the memory cell array 110 includes a plurality of element regions 112, a plurality of word lines WL, a plurality of plugs, a plurality of ferroelectric capacitors 170, a plurality of bit lines BL, and a plurality of plate lines PL. Has been placed.

  (1) As shown in FIG. 5, the element region 112 is a region that is long in the x direction, and has a substantially Z shape (or an inverted Z shape) in the present embodiment. A plurality of element regions 112 are arranged in the x direction, and the interval is DAcx. The distance in the y direction between the element regions 112 adjacent in the y direction is DAcy. In addition, the element regions 112 constituting the adjacent two element region rows are alternately arranged in the x direction. In other words, a staggered arrangement. In FIG. 5, the element regions 112 are arranged so as not to overlap in the x direction.

  The element region 112 is a region where the NMOS 172 (see FIG. 2) constituting the memory cells MC1 to MC4 is formed. In each element region 112, two NMOSs 172 (the branch lines 124 of the word lines WL) are formed. As shown in the lower right part of FIGS. 4 and 5, the element region 112 has active regions 114, 116, and 118 which are examples of one end, the other end, and an intermediate portion. In the element region 112, the active regions 114, 116, and 118 are the source and drain regions of the NMOS 172, respectively, and function as the source or drain. Further, the branch line 124 of the word line WL functions as the gate of the NMOS 172. The element regions 112 are insulated (element isolation) from each other via the insulating layer 70 (see FIG. 4).

  Here, the element region 112 has a substantially Z shape (or a substantially inverted Z shape). In other words, as shown in the lower right element region 112 in FIG. 5, the width of the active region 118 in the y direction is wider than the width of the active regions 114 and 116 in the y direction. Specifically, the element region 112 has a stepped shape in which the x direction is the longitudinal direction and is shifted in the y direction. That is, in the element region 112, the active regions 114 and 116 are arranged so as to be shifted in opposite directions in the y direction.

  Thus, by devising the shape of the element region 112, the space between the element regions in the y direction can be reduced. That is, as described with reference to FIG. 10, when the element region 112 has a substantially rectangular shape, a large space between the element regions in the y direction must be secured. This is because, for example, as shown in FIG. 11A, it is necessary to secure a distance (DW) between the branch line 124 of the word line WL and the trunk line 122 of another adjacent word WL. FIG. 11 is a partial plan view for explaining the effect of the present embodiment.

  As shown in FIG. 11A, one end of the element region 112 is bent in a crank shape in the word line WL direction (downward in the drawing) in which the device is driven, thereby adjoining the branch line 124 of the word line WL. The distance between the trunk lines 122 of the other word lines WL is increased, and the distance between the word line WL and the element region 112 can be reduced accordingly. As a result, the space between the element regions in the y direction can be reduced. In other words, the memory cell formed on one end of the element region 112 is arranged close to the trunk line 122 of the word line WL to which the memory cell is driven, and the distance is D1. On the other hand, the main line 122 of the word line WL that is not driven by itself is arranged at a distance D2 (> D1).

  In addition, as shown in FIG. 11B, in the adjacent element regions 112, the adjacent sides are bent in the same direction, and the width (DAcy2) between the element regions is ensured. That is, an element region (for example, an element region in which the memory cell MC2 is formed) 112 arranged on one side of each word line WL is an element region (for example, in which the memory cell C3 is formed) arranged on the other side. The direction in which the (region) 112 and the active regions 114 and 116 are displaced is opposite to each other. In other words, the element region 112 (for example, the element region in which the memory cell MC2 is formed) 112 arranged on one side of each word line WL is substantially Z-shaped, whereas the element region is arranged on the other side. The arrayed element region (for example, the element region in which the memory cell C3 is formed) 112 has an inverted Z shape.

  Thus, by devising the shape and arrangement of the element regions 112, the space between the element regions in the y direction can be reduced.

  The element regions 112 are arranged in the x direction between adjacent word lines WL. That is, in the memory cell array 110, the word lines WL and the columns of the element regions 112 are alternately arranged in the y direction. The element regions 112 are alternately arranged in the x direction on both sides of each word line WL. In other words, a staggered arrangement. In the present embodiment, the element region 112 arranged on one side of each word line WL and the element region 112 arranged on the other side are arranged so as not to overlap in the x direction.

  (2) As shown in FIG. 6, each word line WL is composed of a main line 122 extending in the x direction and a branch line 124 extending in the y direction substantially orthogonal to the x direction. It is extended. The trunk line 122 bends between a plurality of element regions 112 adjacent to the trunk line 122 and extends in the x direction. Specifically, the trunk line 122 bends in the x direction and the y direction according to the shape and arrangement of the adjacent element regions 112 and extends so as to pass between the element regions 112. ing.

  Further, the trunk line 122 is bent further in accordance with the arrangement of the branch lines 124 of other adjacent word lines WL. Specifically, the branch line 124 branches from the trunk line 122 and is arranged from one side of the element region 112 to the other side of the element region 112 across the element region 112 in the y direction. Protruding from. This is because the entire width in the y direction of the element region 112 is used as a channel to improve the driving capability of the transistor. Further, by forming the protruding portion, it is possible to reduce defects due to mask displacement and manufacturing variations.

  Further, the branch line 124 passes through between the active regions 114 and 118 (to be described later) and between the active regions 116 and 118 in the element region 112 (see FIG. 4), and an end portion thereof extends from the element region 112. It protrudes. The trunk line 122 is bent so as to be arranged at a predetermined distance from the end of the branch line 124 of another adjacent word line WL.

  By extending the word line WL between the element regions in this way, the element region in the y direction can be reduced. That is, as described with reference to FIG. 10, when the element region 112 has a substantially rectangular shape, a large space between the element regions in the y direction must be secured. This is because, for example, as shown in FIG. 12, it is necessary to secure a distance (DW) between the branch line 124 of the word line WL and the trunk line 122 of another adjacent word line WL. FIG. 12 is a partial plan view for explaining the effect of the present embodiment.

  As shown in FIG. 12, the trunk line 122 of the word line WL is disposed close to the element region 112 side where the branch line 124 extends, that is, spaced apart by a distance D3 (<D4). Further, the trunk line 122 of the word line WL is arranged at a distance D4 (> D3) away from the element region 112 side facing the branch line 124 of the other word line WL.

  In this manner, the space between the word line WL and the element region 112 can be reduced by arranging the main line 122 of the word line WL so as to be repeatedly moved away from the element regions 112 on both sides thereof. As a result, the space between the element regions in the y direction can be reduced.

  (3) As shown in FIG. 7 and the like, the ferroelectric capacitor 170 is formed on one end and the other end (active regions 114 and 116) of the element region 112 (see FIGS. 4 and 5). ). As shown in FIG. 4, the ferroelectric capacitor 170 has a laminated structure of a lower electrode 50, a ferroelectric layer 52, and an upper electrode 54, and is provided in an upper layer at both ends of the element region 112 in the x direction. ing. In the ferroelectric capacitor 170, the lower electrode 50 is connected to the active regions 114 and 116 via the plug 56, respectively.

  In the present embodiment, the memory cell array 110 includes a word line WL that drives the ferroelectric capacitor 170 connected to the active region 114 and a word line WL that drives the ferroelectric capacitor 170 connected to the active region 116. And are arranged alternately. The plurality of branch lines 124 branched from the predetermined word line WL drive only the ferroelectric capacitor 170 (see FIGS. 4 and 7) connected to either the active region 114 or the active region 116. Has been placed. In FIG. 3, the word line WL1 drives the ferroelectric capacitor 170 connected to the active region 114, and the word lines WL2 and WL3 adjacent to the word line WL1 are connected to the active region 116. It is arranged to drive 170. Note that the plurality of branch lines 124 may be arranged so as to drive the ferroelectric capacitor 170 connected to both the active region 114 and the active region 116.

  (4) As shown in FIG. 8 and the like, the bit lines BL extend substantially linearly in the y direction with a certain distance from each other in the x direction. As described above, the element regions 112 are alternately arranged on both sides of each word line WL in the x direction, and are arranged so as to intersect with the bit lines BL as shown in FIG. As shown in FIG. 4 and the like, each bit line BL is connected to the element region 112 in the active region 118 through the plug 56. When a predetermined voltage is supplied to the branch line 124 (word line WL), each NMOS 172 forms a channel below the branch line 124 in the element region 112, and the bit line BL and the lower electrode of the ferroelectric capacitor 170 are formed. 50 is connected.

  Further, as shown in FIG. 8 and the like, the wiring 72 is provided in the same layer as the bit line BL, and from the active region 114 of the predetermined element region 112 to another element region 112 adjacent to the active region 114. The active region 116 is provided. Further, as shown in FIG. 4B and the like, a ferroelectric capacitor 170 connected to the active region 114 and a ferroelectric substance connected to the active region 116 of another element region 112 adjacent to the active region 114. The capacitor 170 is connected. That is, each is connected to the upper electrode 54 of the ferroelectric capacitor 170 through the plug 60.

  (5) As shown in FIGS. 3, 4, 9, etc., the plate lines PL extend substantially linearly in the x direction with a certain interval in the y direction. Each plate line PL is arranged so as to overlap the element region 112 along the arrangement of the element regions 112. Each plate line PL is connected only to the ferroelectric capacitor 170 connected to the active region 114 among the plurality of ferroelectric capacitors 170 arranged below the plate line PL, and the plate line PL Of the ferroelectric capacitors arranged below the other plate lines PL adjacent to PL, only the ferroelectric capacitor 170 connected to the active region 116 is connected. That is, the ferroelectric capacitor 170 connected to the active region 114 provided on one side of the predetermined word line WL and the ferroelectric capacitor 170 connected to the active region 116 provided on the other side are Are connected to the same plate line PL.

  As described in detail above, according to the present embodiment, each word line WL drives the ferroelectric capacitor 170 connected to the plurality of element regions 112 arranged on both sides thereof. A short ferroelectric memory device can be provided. In particular, according to the present embodiment, the length in the y direction can be reduced as compared with a ferroelectric memory device in which a plurality of element regions 112 are arranged on both sides of the bit line BL.

  According to the present embodiment, at least two ferroelectric capacitors 170 are connected to the predetermined element region 112, and the word line WL that drives each ferroelectric capacitor 170 is connected to the predetermined element region 112. Since they are arranged on both sides, a ferroelectric memory device having a high degree of integration and a short length in the y direction can be provided.

  According to the present embodiment, since the plurality of element regions 112 are alternately arranged in the x direction between the word lines WL, the distance between the element regions 112 in the y direction is further reduced and the length in the y direction is increased. A ferroelectric memory device having a shorter length can be provided.

  According to the present embodiment, since the channel width of the NMOS 172 can be widened in the element region 112, the driving capability of the NMOS 172 formed in the element region 112 is sufficiently ensured even if the length in the y direction is shortened. can do. As a result, a sufficient access speed to the ferroelectric capacitor 170 can be ensured.

  According to the present embodiment, the element region 112 can have a sufficient width while further reducing the distance between the element regions 112 in the y direction, so that the driving capability of the NMOS 172 formed in the element region 112 can be increased. It can be secured sufficiently. As a result, a sufficient access speed to the ferroelectric capacitor 170 can be ensured.

  According to the present embodiment, since each word line WL is bent, the distance between the element regions 112 in the y direction can be further reduced, and a ferroelectric memory device having a shorter length in the y direction is provided. Can do.

  According to the present embodiment, a plurality of ferroelectric capacitors 170 connected to the same plate line PL can be driven by different word lines WL, so that the length in the y direction can be shortened and desired. A ferroelectric memory device that can access the ferroelectric capacitor 170 can be provided.

  According to the present embodiment, in a configuration in which a plurality of ferroelectric capacitors 170 connected to the same plate line PL are driven by different word lines WL, each plate line PL can be provided in a substantially linear shape. Therefore, the load on the plate line PL can be reduced.

(Embodiment 2)
FIG. 13 is a plan view showing the memory cell array 110 of the present embodiment. FIG. 14 is a fragmentary cross-sectional view of the memory cell array 110 of the present embodiment. 14A shows an AA section in FIG. 13, and FIG. 14B shows a BB section in FIG. In the following, portions corresponding to those in the first embodiment are denoted by the same reference numerals, detailed description thereof will be omitted, and differences from the first embodiment will be mainly described.

  In the present embodiment, as shown in FIG. 13, each plate line PL extends in the x direction and is connected to a plurality of element regions 112 arranged on both sides of the word line WL. A dielectric capacitor 170 is connected. Specifically, the plate line PL is provided at a ratio of one to two word lines WL, and a plurality of plate lines PL are connected to the active regions 114 and 116 disposed on both sides of the corresponding word line WL. The ferroelectric capacitor 170 is connected.

  In the present embodiment, as shown in FIG. 14, the bit line BL is arranged in an upper layer than the plate line PL. Specifically, the plate line PL is connected to the upper electrode 54 of the ferroelectric capacitor 170 through the plug 60, and the bit line BL is the pad 74 disposed in the same layer as the plug 62 and the plate line PL. And the plug 56 are connected to the active region 118.

  According to the present embodiment, since each plate line PL is connected to the plurality of ferroelectric capacitors 170 arranged on both sides of the word line WL, the length in the y direction is added to the effect of the first embodiment. However, it is possible to provide a ferroelectric memory device having a shorter length. Further, according to the present embodiment, since the number of plate lines PL can be reduced, the area of the configuration of the plate line control unit can also be reduced (see FIG. 1).

  In the present embodiment, the bit line BL is positioned below the plate line PL, but the bit line BL may be positioned above the plate line PL.

(Embodiment 3)
15 and 16 are plan views showing the memory cell array 110 according to the present embodiment. FIG. 16 is a plan view clearly showing the relationship between the bit line BL and the plate line PL in FIG. FIG. 17 is a circuit diagram showing a configuration of the memory cell array 110 of the present embodiment.

  In the following, portions corresponding to those in the first embodiment are denoted by the same reference numerals, detailed description thereof will be omitted, and differences from the first embodiment will be mainly described.

  In the present embodiment, as shown in FIGS. 15 and 16, each plate line PL extends in the y direction. In other words, each plate line PL extends between the bit lines BL substantially in parallel with the bit lines BL.

  Specifically, the plate line PL is provided so as to extend from the active region 114 of the predetermined element region 112 to the active region 116 of another element region 112 adjacent to the active region 114. The plate line PL connects the ferroelectric capacitor 170 connected to the active region 114 and the ferroelectric capacitor 170 connected to the active region 116 of another element region 112 adjacent to the active region 114. .

  According to the present embodiment, as described in the first embodiment, since the length in the extending direction (y direction) of the bit line BL of the memory cell array 110 is shortened, the plate line is extended in the x direction. The plate line PL becomes shorter than the case where it exists, and the load of the plate line PL can be reduced.

  According to the present embodiment, since the plate line PL and the bit line BL are extended in the same direction, the plate line PL and the bit line BL can be formed in the same layer. In this case, the plate line PL is positioned at the position of the wiring 72 in FIGS. 4 (a) and 4 (b).

  FIG. 17 shows the configuration of the memory cells MC1 to MC4 which are repetitive units in the memory cell array 110 of the present embodiment. In the memory cell array 110, memory cells MC1 to MC4 are repeatedly arranged in the extending direction of the word lines WL and the extending direction of the bit lines BL.

  Each of the memory cells MC1 to MC4 includes a ferroelectric capacitor 170 and an NMOS 172. In the memory cells MC1 to MC4, the NMOS 172 has one of the source and drain regions connected to the bit line BL and the other connected to one end of the ferroelectric capacitor 170. The NMOS 172 has a gate connected to the word line WL, and switches whether to connect one end of the ferroelectric capacitor 170 to the corresponding bit line BL according to the voltage of the word line WL. The other end of the ferroelectric capacitor 170 is connected to the corresponding plate line PL.

  Specifically, in the memory cell MC1, the NMOS 172 has one of the source and drain regions connected to the bit line BL1, the gate connected to the word line WL1, and the other end of the ferroelectric capacitor 170 connected to the plate line. Connected to PL1. In the memory cell MC2, the NMOS 172 has one of the source and drain regions connected to the bit line BL1, the gate connected to the word line WL3, and the other end of the ferroelectric capacitor 170 connected to the plate line PL2. Has been. In the memory cell MC3, the NMOS 172 has one of the source and drain regions connected to the bit line BL2, the gate connected to the word line WL1, and the other end of the ferroelectric capacitor 170 connected to the plate line PL2. Has been. In the memory cell MC4, the NMOS 172 has one of the source and drain regions connected to the bit line BL2, the gate connected to the word line WL2, and the other end of the ferroelectric capacitor 170 connected to the plate line PL3. Has been.

(Embodiment 4)
18 and 19 are plan views showing the memory cell array 110 of the present embodiment. FIG. 19 is a plan view showing the arrangement of the ferroelectric capacitors 170 and the bit lines BL in FIG. In the following, portions corresponding to those in the first embodiment are denoted by the same reference numerals, detailed description thereof will be omitted, and differences from the first embodiment will be mainly described.

  In this embodiment, as shown in FIGS. 18 and 19, the formation area of the ferroelectric capacitor 170 is larger than in the first embodiment (FIG. 7) or the like.

  Specifically, as shown in FIG. 19 and the like, the ferroelectric capacitor 170 has a substantially rectangular shape having a long side in the x direction. As shown in the figure, the formation region of the ferroelectric capacitor 170 is secured long in the direction of the bit line BL adjacent to the bit line BL to be driven.

  As a result, in addition to the effects described in the first embodiment, the amount of charge that can be accumulated in the ferroelectric capacitor 170 increases, and the write / read margin increases. In addition, writing and reading characteristics are improved.

  Further, the area occupied by the ferroelectric capacitor 170 is increased, and a step due to the presence or absence of the ferroelectric capacitor 170 can be reduced.

  The configuration of the plate line PL may be the shape described in the second or third embodiment.

  In the first and third embodiments, the bit line BL is positioned below the plate line PL. However, the bit line BL is positioned above the plate line PL as in the second embodiment. It is good.

  In the first to third embodiments, the active region has a substantially rectangular shape, but may have another shape (for example, an elliptical shape). In the first to third embodiments, two cells (two transistors and two capacitors) are formed on one active region. However, the present invention is not limited to this, and one cell (1 The present invention may be applied to a ferroelectric memory device or the like in which one transistor and one capacitor are formed.

  In the first to third embodiments, the description has been made on the assumption that the bit lines are formed in accordance with the plurality of wiring pitches of the display body. However, the plurality of wiring intervals of the display body and the bit line interval are the same. There is no need. This is because the connection of these wirings becomes easier and the connection failure between the wirings can be reduced even if the difference between the intervals is reduced. Therefore, the memory cell structure of the above embodiment may be provided at least in the memory cell region.

(Description of electro-optical device and electronic equipment)
Next, an electro-optical device and an electronic apparatus in which such a display body is used will be described.

  The present invention is used, for example, as a drive circuit for an electro-optical device (display device). FIG. 20 illustrates an example of an electronic device using a display body. FIG. 20A shows an application example to a mobile phone, and FIG. 20B shows an application example to a video camera. 20C illustrates an example of application to television (TV), and FIG. 20D illustrates an example of application to roll-up television.

  As shown in FIG. 20A, the cellular phone 530 includes an antenna portion 531, an audio output portion 532, an audio input portion 533, an operation portion 534, and an electro-optical device (display portion, display body) 500. The present invention can be applied to this electro-optical device.

  As shown in FIG. 20B, the video camera 540 includes an image receiving unit 541, an operation unit 542, an audio input unit 543, and the electro-optical device 500. The present invention can be applied to this electro-optical device.

  As illustrated in FIG. 20C, the television 550 includes an electro-optical device 500. The present invention can be applied to this electro-optical device. The present invention can also be applied to a monitor device used for a personal computer or the like.

  As shown in FIG. 20D, the roll-up television 560 includes an electro-optical device 500. The present invention can be applied to this electro-optical device.

  In addition to the above, the electronic apparatus having the electro-optical device includes a fax machine with a display function, a digital camera finder, a portable TV, an electronic notebook, an electric bulletin board, a display for advertisements, and the like.

  Further, in the first to third embodiments, the case of the memory cell array connected to the drive circuit of the display body has been described. However, the present invention is not limited to this application, and various types including the ferroelectric memory device itself and the ferroelectric memory. Widely applicable to electronic devices.

  In addition, the examples and application examples described through the above-described embodiments of the invention can be used in appropriate combination depending on the application, or can be used with modifications or improvements. The present invention is described in the above-described embodiments. It is not limited to. It is apparent from the description of the scope of claims that the embodiments added with such combinations or changes or improvements can be included in the technical scope of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a display drive IC according to the first embodiment. 2 is a circuit diagram illustrating a configuration of a memory cell array 110 according to the first embodiment. FIG. 1 is a plan view showing a memory cell array 110 of Embodiment 1. FIG. 3 is a main-portion cross-sectional view of the memory cell array 110 of Embodiment 1. FIG. FIG. 3 is a plan view of a principal part showing a partial pattern of the memory cell array 110 of the first embodiment. FIG. 3 is a plan view of a principal part showing a partial pattern of the memory cell array 110 of the first embodiment. FIG. 3 is a plan view of a principal part showing a partial pattern of the memory cell array 110 of the first embodiment. FIG. 3 is a plan view of a principal part showing a partial pattern of the memory cell array 110 of the first embodiment. FIG. 3 is a plan view of a principal part showing a partial pattern of the memory cell array 110 of the first embodiment. 1 is a schematic plan view showing a memory cell array 110 of Embodiment 1. FIG. FIG. 6 is a partial plan view for explaining an effect of the first embodiment. FIG. 6 is a partial plan view for explaining an effect of the first embodiment. FIG. 6 is a plan view showing a memory cell array 110 according to the second embodiment. FIG. 6 is a cross-sectional view of a main part of a memory cell array 110 according to the second embodiment. FIG. 6 is a plan view showing a memory cell array 110 according to a third embodiment. FIG. 6 is a plan view showing a memory cell array 110 according to a third embodiment. FIG. 6 is a circuit diagram showing a configuration of a memory cell array 110 according to the third embodiment. FIG. 6 is a plan view showing a memory cell array 110 according to a fourth embodiment. FIG. 6 is a plan view showing a memory cell array 110 according to a fourth embodiment. It is a figure which shows the example of the electronic device using a display body.

Explanation of symbols

50 ... Lower electrode, 52 ... Ferroelectric layer, 54 ... Upper electrode, 56, 60, 62 ... Plug, 70 ... Insulating layer, 72 ... Wiring, 74 ... Pad, 110 ... Memory cell array, 112 ... Each element region, 112 Element region 114, 116, 118 Active region 120 Word line control unit 122 Trunk line 124 Branch line 130 Plate line control unit 140 Bit line control unit 150 Latch circuit 160 Display Drive circuit, 170 ... ferroelectric capacitor, 172 ... NMOS, 500 ... electro-optical device, 530 ... mobile phone, 531 ... antenna unit, 532 ... audio output unit, 533 ... audio input unit, 534 ... operation unit, 540 ... video Camera, 541 ... Image receiving unit, 542 ... Operation unit, 543 ... Audio input unit, 550 ... Television, 560 ... Roll-up television, BL ... Bit line MC ... memory cell, PL ... plate line, WL ... word line

Claims (9)

A first word line extending in a first direction;
A second word line extending in the first direction;
An element region disposed between the first word line and the second word line;
A bit line extending in a second direction orthogonal to the first direction and connected to the element region;
Including
The first word line has a first branch line extending in a direction of the second word line;
The second word line has a second branch line extending in the direction of the first word line;
The first branch line includes a first gate electrode of a transistor disposed in the element region,
The second branch line includes a second gate electrode of a transistor disposed in the element region,
An end portion on the first word line side of the element region intersecting the first gate electrode is defined as a first end portion,
The second word line side end of the element region intersecting the first gate electrode is defined as a second end,
When the distance from the first end to the first word line is the first distance and the distance from the second end to the second word line is the second distance, The first distance is smaller than the second distance,
The second word line side end of the element region intersecting the second gate electrode is defined as a third end,
An end of the element region intersecting the second gate electrode on the first word line side is a fourth end;
When the distance from the third end to the second word line is the third distance and the distance from the fourth end to the first word line is the fourth distance, The third distance is smaller than the fourth distance,
The element region has a step shape in plan view,
The first end portion and the fourth end portion are arranged so as to be shifted in the second direction, and form a step shape in a plan view.
2. The ferroelectric memory device according to claim 1, wherein the second end portion and the third end portion are arranged so as to be shifted in the second direction and have a step shape in plan view. A first word line extending in a first direction;
A second word line extending in the first direction;
An element region disposed between the first word line and the second word line;
A bit line extending in a second direction orthogonal to the first direction and connected to the element region;
Including
The first word line has a first branch line extending in a direction of the second word line;
The second word line has a second branch line extending in the direction of the first word line;
The first branch line includes a first gate electrode of a transistor disposed in the element region,
The second branch line includes a second gate electrode of a transistor disposed in the element region,
An end on the second word line side of the first gate electrode intersecting with one side of the element region is defined as a first end,
The second word line side end of the second gate electrode intersecting the one side is defined as a second end,
When the distance from the first end to the second word line is a first distance and the distance from the second end to the second word line is a second distance, The first distance is greater than the second distance,
2. The ferroelectric memory device according to claim 1, wherein the second word line has a bent shape that bypasses the first branch line. In the element region,
As the transistor, a first transistor including the first gate electrode, and a second transistor including the second gate electrode,
One of a source and a drain of the first transistor is connected to the bit line, and the other of the source and the drain of the first transistor is connected to a first ferroelectric capacitor;
One of a source and a drain of the second transistor is connected to the bit line, and the other of the source and the drain of the second transistor is connected to a second ferroelectric capacitor;
The ferroelectric memory device according to claim 1 or 2. The first ferroelectric capacitor and the second ferroelectric capacitor are formed such that the width in the first direction is larger than the width in the second direction.
The ferroelectric memory device according to claim 3. A plate line connected to either the first ferroelectric capacitor or the second ferroelectric capacitor;
The ferroelectric memory device according to claim 3 or 4 . The plate line extends in the first direction;
A first element region and a second element region are arranged as the element regions on both sides of the first word line,
The first ferroelectric capacitor connected to the first element region and the second ferroelectric capacitor connected to the second element region are connected to the same plate line;
The ferroelectric memory device according to claim 5. The plate line extends in the second direction;
A first element region and a second element region are arranged as the element regions on both sides of the first word line,
The first ferroelectric capacitor connected to the first element region and the second ferroelectric capacitor connected to the second element region are connected to the same plate line;
The ferroelectric memory device according to claim 5.   A display driving IC comprising the ferroelectric memory device according to claim 1.   An electronic apparatus comprising the ferroelectric memory device according to claim 1.

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