JP4694379B2 - Flat light source and manufacturing method thereof - Google Patents

Flat light source and manufacturing method thereof Download PDF

Info

Publication number
JP4694379B2
JP4694379B2 JP2006020821A JP2006020821A JP4694379B2 JP 4694379 B2 JP4694379 B2 JP 4694379B2 JP 2006020821 A JP2006020821 A JP 2006020821A JP 2006020821 A JP2006020821 A JP 2006020821A JP 4694379 B2 JP4694379 B2 JP 4694379B2
Authority
JP
Japan
Prior art keywords
substrate
dielectric
light source
flat light
phosphor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006020821A
Other languages
Japanese (ja)
Other versions
JP2007200816A (en
Inventor
張昭仁
丁初稷
李素秋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chunghwa Picture Tubes Ltd
Original Assignee
Chunghwa Picture Tubes Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chunghwa Picture Tubes Ltd filed Critical Chunghwa Picture Tubes Ltd
Priority to JP2006020821A priority Critical patent/JP4694379B2/en
Publication of JP2007200816A publication Critical patent/JP2007200816A/en
Application granted granted Critical
Publication of JP4694379B2 publication Critical patent/JP4694379B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Manufacture Of Electron Tubes, Discharge Lamp Vessels, Lead-In Wires, And The Like (AREA)

Description

この発明は、平板光源とその製造方法に関する。より詳細には、この発明は高輝度の平板光源とその製造方法に関する。   The present invention relates to a flat light source and a method for manufacturing the same. More specifically, the present invention relates to a high-luminance flat light source and a method for manufacturing the same.

近年、液晶表示パネル(LCDパネル)が、表示画面において主要な役割を果たしている。しかし、LCDパネル自体は発光できないので、LCDパネルの下 にバックライト・モジュールを配置して、光源を提供し、表示機能を実現しなければならない。バックライト・モジュールの光源は通常、ランプによって提供さ れる。ランプが出射した光は、バックライト・モジュールの光学フィルムを通過し、散乱された後、LCDパネルの照射に適した面光源を構成する。   In recent years, liquid crystal display panels (LCD panels) have played a major role in display screens. However, since the LCD panel itself cannot emit light, a backlight module must be placed under the LCD panel to provide a light source and realize a display function. The light source of the backlight module is usually provided by a lamp. The light emitted from the lamp passes through the optical film of the backlight module, and after being scattered, constitutes a surface light source suitable for irradiation of the LCD panel.

平板光源を直接用いることができれば、面光源の光利用効率と均一性を向上できる。さらに、平板光源は、LCDパネルのバックライト源以外に、他の様々な分野で用いることもできる。従って、平板光源の開発には利点がある。   If a flat light source can be used directly, the light use efficiency and uniformity of the surface light source can be improved. Further, the flat light source can be used in various other fields besides the backlight source of the LCD panel. Therefore, there is an advantage in developing a flat light source.

一般に、平板光源はプラズマ発光素子であり、主に電極対の間に高電圧を印加して、高エネルギ電子を生成し、高エネルギ電子を不活性ガスに衝突させて、い わゆるプラズマを形成する。それから、プラズマ内の励起原子がUV光を放射することでエネルギを開放し、放出されたUV光がさらに平板光源の蛍光体を励起 し、可視光を出射する。   In general, a flat light source is a plasma light-emitting device. A high voltage is mainly applied between electrode pairs to generate high-energy electrons, and the high-energy electrons collide with an inert gas to form a so-called plasma. To do. Then, the excited atoms in the plasma release UV light to release the energy, and the emitted UV light further excites the phosphor of the flat light source to emit visible light.

既存の平板光源の活発な開発の一つの鍵となっているのは、どのように輝度を向上させ、出射光の均一性を改善するかということである。   One key to the active development of existing flat light sources is how to improve brightness and improve uniformity of emitted light.

従って、この発明の目的は、高輝度および高発光均一性を備えた平板光源を提供することである。   Accordingly, an object of the present invention is to provide a flat light source having high luminance and high light emission uniformity.

この発明の別の目的は平板光源の製造方法を提供することであり、製造された平板光源は高輝度および高発光均一性を有する。   Another object of the present invention is to provide a method of manufacturing a flat light source, and the manufactured flat light source has high luminance and high light emission uniformity.

この発明は、第一基板、第二基板、シール部、複数組の誘電体パターンおよび蛍光体層を有する平板光源を提供する。第一基板上には電極を有する。シール部 は第一基板と第二基板の間に配置し、第一基板、第二基板およびシール部の間に空隙部を形成する。前記複数組の誘電体パターンは、第一基板と第二基板の間の 空隙部に形成する。誘電体パターンの各組は互いに平行な少なくとも二つの誘電体ストリップを有し、各誘電体ストリップは対応する電極の一つを被覆する。各誘電体スト リップは上面と二つの側面を有し、上面は長手方向に沿った凸部と凹部を有している。蛍光体層は各組の誘電体パターンの誘電体ストリップの間に配置し、さらに蛍光体層は誘 電体ストリップの上面に配置する。 The present invention provides a flat light source having a first substrate, a second substrate, a seal portion, a plurality of sets of dielectric patterns and a phosphor layer. An electrode is provided on the first substrate. The seal portion is disposed between the first substrate and the second substrate, and a gap is formed between the first substrate, the second substrate, and the seal portion. The plurality of sets of dielectric patterns are formed in a gap between the first substrate and the second substrate. Each set of dielectric patterns has at least two dielectric strips parallel to each other, each dielectric strip covering one of the corresponding electrodes. Each dielectric strip has an upper surface and two side surfaces, and the upper surface has a convex portion and a concave portion along the longitudinal direction . The phosphor layer is disposed between the dielectric strips of each set of dielectric patterns, and the phosphor layer is disposed on the top surface of the dielectric strip.

この発明の一実施例では、上記の蛍光体層はさらに、二つの隣接する誘電体パターンの組の間に配置する。   In one embodiment of the present invention, the phosphor layer is further disposed between two adjacent sets of dielectric patterns.

この発明の一実施例では、平板光源はさらに、第一基板と第二基板の間の空隙部に配置した複数の隔壁を有する。一実施例では、蛍光体層はさらに隔壁の表面上に塗布する。別の実施例では、誘電体ストリップの高さは隔壁の高さと同じである。さらに別の実施例では、誘電体ストリップの高さは隔壁より低い。   In one embodiment of the present invention, the flat light source further includes a plurality of partition walls arranged in a gap between the first substrate and the second substrate. In one embodiment, the phosphor layer is further applied on the surface of the barrier rib. In another embodiment, the height of the dielectric strip is the same as the height of the partition. In yet another embodiment, the height of the dielectric strip is lower than the bulkhead.

この発明の一実施例では、誘電体ストリップの高さは第一基板と第二基板の間のギャップと同じである。   In one embodiment of the invention, the height of the dielectric strip is the same as the gap between the first substrate and the second substrate.

この発明の一実施例では、平板光源はさらに第一基板の表面上に配置した反射層を有する。   In one embodiment of the present invention, the flat light source further includes a reflective layer disposed on the surface of the first substrate.

この発明の一実施例では、平板光源はさらに第二基板上に配置した別の蛍光体層を有する。   In one embodiment of the present invention, the flat light source further includes another phosphor layer disposed on the second substrate.

この発明はさらに、平板光源の製造方法を提供する。この方法では、第一基板を提供する。次に、第一基板上に複数の電極を形成する。それから、第一基板上 に複数組の誘電
体パターンを形成する。各組の誘電体パターンは互いに平行な少なくとも二つの誘電体ストリップを有し、各誘電体ストリップは対応する電極の一つを被覆 し、形成した前記誘
電体ストリップは各々上面と二つの側面を備え、上面は長手方向に沿った凸部と凹部を有する。その後、各組の誘電体パターンの誘電体ストリップの間と誘 電体ストリップの上面に蛍光体層を形成する。第二基板を提供し、第一基板と第二基板の間にシール部を形成し、第一基板と第二基板を共に接続する。
The present invention further provides a method of manufacturing a flat light source. In this method, a first substrate is provided. Next, a plurality of electrodes are formed on the first substrate. Then, a plurality of sets of dielectric patterns are formed on the first substrate. Each set of dielectric patterns has at least two dielectric strips parallel to each other, each dielectric strip covering one of the corresponding electrodes, each formed dielectric strip having an upper surface and two side surfaces. The upper surface has a convex part and a concave part along the longitudinal direction . Thereafter, a phosphor layer is formed between the dielectric strips of each set of dielectric patterns and on the top surface of the dielectric strip. A second substrate is provided, a seal is formed between the first substrate and the second substrate, and the first substrate and the second substrate are connected together.

この発明の一実施例では、誘電体ストリップの形成方法には、スクリーン印刷工程、エッチング工程またはサンドブラスト工程が含まれる。   In one embodiment of the present invention, the method of forming a dielectric strip includes a screen printing process, an etching process, or a sandblasting process.

この発明の一実施例では、蛍光体層を形成するステップではさらに、隣接する誘電体パターンの組の間に蛍光体層を塗布する。   In one embodiment of the present invention, the step of forming the phosphor layer further applies a phosphor layer between adjacent sets of dielectric patterns.

この発明の一実施例では、前記方法でさらに、第一基板と第二基板の接続前に、第一基板と第二基板の間に複数の隔壁を形成する。一実施例では、蛍光体層は さらに隔壁の表面上に塗布する。別の実施例では、誘電体ストリップの高さは隔壁の高さと同じである。さらに別の実施例では、誘電体ストリップの高さは隔壁 より低い。   In one embodiment of the present invention, a plurality of partition walls are formed between the first substrate and the second substrate before the connection between the first substrate and the second substrate by the above method. In one embodiment, the phosphor layer is further applied on the surface of the barrier rib. In another embodiment, the height of the dielectric strip is the same as the height of the partition. In yet another embodiment, the height of the dielectric strip is lower than the partition.

この発明の一実施例では、上記の誘電体ストリップの高さは第一基板と第二基板の間のギャップと同じである。   In one embodiment of the invention, the height of the dielectric strip is the same as the gap between the first substrate and the second substrate.

この発明の一実施例では、前記方法でさらに、第一基板上に電極を形成する前に第一基板上に反射層を形成する。   In one embodiment of the present invention, the reflective layer is formed on the first substrate before forming the electrode on the first substrate by the above method.

この発明の一実施例では、前記方法でさらに、第二基板上に別の蛍光体層を形成する。   In one embodiment of the present invention, another phosphor layer is further formed on the second substrate by the above method.

各誘電体ストリップの上面は長手方向に沿った凸部と凹部を有するように設計されているので、蛍光体層の塗布領域を増大でき、平板光源の輝度を向上できる。 Since the upper surface of each dielectric strip is designed to have a convex portion and a concave portion along the longitudinal direction, the application area of the phosphor layer can be increased, and the luminance of the flat light source can be improved.

図1Aは、この発明の好ましい実施例による平板光源の概略断面図である。図1Aを参照すると、この発明の平板光源は、第一基板100、第二基板120、シール部104、複数の電極102、複数組の誘電体パターン108および蛍光体層110を有する。   FIG. 1A is a schematic cross-sectional view of a flat light source according to a preferred embodiment of the present invention. Referring to FIG. 1A, the flat light source of the present invention includes a first substrate 100, a second substrate 120, a seal portion 104, a plurality of electrodes 102, a plurality of sets of dielectric patterns 108, and a phosphor layer 110.

電極102は、第一基板100上に配置する。各電極102はストリップ状で、これらの電極102は第一基板100上に互いに平行に配置する。シール部104は第一基板100と第二基板120の間に配置し、第一基板100、第二基板120 およびシール部104の間に空隙部106を形成する。シール部104は第一基板100と第二基板120を共に接続し、二枚の基板100、120の間に ギャップを残すために用いられる。誘電体パターン108は、第一基板100上の空隙部106内に配置する。各組の誘電体パターン108は少なくとも二つの 誘電体ストリップ108a、108bを有し、各誘電体ストリップ108a、108bは対応する電極102の一方を被覆する。従って、一組の誘電体パターン 108の二つの誘電体ストリップ108a、108bが被覆する二つの電極102は電極対である。   The electrode 102 is disposed on the first substrate 100. Each electrode 102 has a strip shape, and these electrodes 102 are arranged on the first substrate 100 in parallel with each other. The seal portion 104 is disposed between the first substrate 100 and the second substrate 120, and a gap portion 106 is formed between the first substrate 100, the second substrate 120, and the seal portion 104. The seal portion 104 is used to connect the first substrate 100 and the second substrate 120 together and leave a gap between the two substrates 100 and 120. The dielectric pattern 108 is disposed in the gap 106 on the first substrate 100. Each set of dielectric patterns 108 has at least two dielectric strips 108 a, 108 b, and each dielectric strip 108 a, 108 b covers one of the corresponding electrodes 102. Accordingly, the two electrodes 102 covered by the two dielectric strips 108a and 108b of the set of dielectric patterns 108 are an electrode pair.

特に、この発明の誘電体ストリップ108a、108bは特別な輪郭を有する。図4を参照すると、それは第一基板100上の複数組の誘電体パターン108 の三次元概略図を示している。各誘電体ストリップ108a、108bは上面202と二つの側面204、206を有し、上面202は不均一な輪郭を有する。 言い換えると、各誘電体ストリップ108a、108bは長手方向に沿った凸部と凹部を有し、不均一な構造または段差構造を構成する。 In particular, the dielectric strips 108a, 108b of the present invention have a special contour. Referring to FIG. 4, it shows a three-dimensional schematic view of multiple sets of dielectric patterns 108 on the first substrate 100. Each dielectric strip 108a, 108b has a top surface 202 and two side surfaces 204, 206, with the top surface 202 having a non-uniform contour. In other words, each dielectric strip 108a, 108b has a convex part and a concave part along the longitudinal direction, and forms a non-uniform structure or a step structure.

さらに、図1Aを参照すると、蛍光体層110は各組の誘電体パターン108の二つの誘電体ストリップ108a、108bの間に配置し、さらに蛍光体層 110は誘電体ストリップ108a、108bの上面202に配置し、ここで上面202の輪郭は不均一である。図5に示したように、それは誘電体ストリップ 108a、108bの延長方向に沿った断面図である。蛍光体層110はさらに、誘電体ストリップ108a、108bの上面202に塗布されている。   Further, referring to FIG. 1A, the phosphor layer 110 is disposed between the two dielectric strips 108a, 108b of each set of dielectric patterns 108, and the phosphor layer 110 further includes the upper surface 202 of the dielectric strips 108a, 108b. Where the contour of the upper surface 202 is non-uniform. As shown in FIG. 5, it is a cross-sectional view along the extension direction of the dielectric strips 108a, 108b. The phosphor layer 110 is further applied to the upper surface 202 of the dielectric strips 108a, 108b.

この発明の別の実施例によると、第一基板100上にさらに反射層112を形成する。反射層112は第一基板100の上面に配置することもでき、電極 102は反射層112上に配置する。反射層112は、第一基板100の下面に配置することもできる(図示せず)。反射層112を第一基板100の上面に配 置しようと、第一基板100の下面に配置しようと、反射層112は非導電性材料から構成できる。   According to another embodiment of the present invention, a reflective layer 112 is further formed on the first substrate 100. The reflective layer 112 can also be disposed on the upper surface of the first substrate 100, and the electrode 102 is disposed on the reflective layer 112. The reflective layer 112 can also be disposed on the lower surface of the first substrate 100 (not shown). Whether the reflective layer 112 is disposed on the upper surface of the first substrate 100 or the lower surface of the first substrate 100, the reflective layer 112 can be made of a non-conductive material.

この発明の一実施例によると、蛍光体層114はさらに第二基板120上に配置できる。従って、平板光源の蛍光体層の塗布領域をさらに増大できる。   According to one embodiment of the present invention, the phosphor layer 114 can be further disposed on the second substrate 120. Therefore, the coating area of the phosphor layer of the flat light source can be further increased.

この発明の平板光源の蛍光体層110は、二つの誘電体ストリップ108a、108bの間に塗布するだけでなく、誘電体ストリップ108a、108bの上 面202にも塗布し、ここで上面202は長手方向に沿った凸部と凹部を有する。従って、既存の平板光源に比べて、この発明の平板光源の蛍光体層の塗布領域はより大きくな り、誘電体ストリップ108a、108bの凹部でクロストーク現象が生じ、それによって以前は発光できなかった部分がクロストーク現象のために発光でき る。従って、平板光源の輝度を向上できる。 The phosphor layer 110 of the flat light source of the present invention is applied not only between the two dielectric strips 108a and 108b but also on the upper surface 202 of the dielectric strips 108a and 108b, where the upper surface 202 is elongated. It has a convex part and a concave part along the direction . Therefore, compared with the existing flat light source, the coated area of the phosphor layer of the flat light source of the present invention becomes larger, and the crosstalk phenomenon occurs in the recesses of the dielectric strips 108a and 108b, and thus it cannot emit light before. The flashing part can emit light due to the crosstalk phenomenon. Therefore, the brightness of the flat light source can be improved.

この発明の好ましい実施例によると、図1Aに示したように、平板光源は第一基板100と第二基板120の空隙部106内に配置した複数の隔壁116を有 し、第一基板100と第二基板120の間のギャップの高さを保持する。この発明の別の好ましい実施例では、上記の蛍光体層110はさらに、図1Bに示した ように隔壁116の表面にも塗布できる。従って、蛍光体層の塗布領域をさらに増大し、それによって平板光源の輝度および発光均一性を向上できる。   According to a preferred embodiment of the present invention, as shown in FIG. 1A, the flat light source has a plurality of partition walls 116 disposed in the gap 106 between the first substrate 100 and the second substrate 120, and The gap height between the second substrates 120 is maintained. In another preferred embodiment of the present invention, the phosphor layer 110 can be further applied to the surface of the barrier rib 116 as shown in FIG. 1B. Therefore, the coating area of the phosphor layer can be further increased, thereby improving the luminance and light emission uniformity of the flat light source.

隔壁116が(図1Aと1Bに示したように)平板光源に含まれる場合、誘電体パターン108の高さは隔壁116より低くできる。誘電体パターン108の 高さは、図1Cに示したように、隔壁116の高さと確実に同じにすることもできる。従って、隔壁116と誘電体パターン108は二枚の基板100、120 を支持し、二枚の基板100、120の間のギャップの高さを保持できる。   When the barrier rib 116 is included in the flat light source (as shown in FIGS. 1A and 1B), the height of the dielectric pattern 108 can be lower than that of the barrier rib 116. The height of the dielectric pattern 108 may be the same as the height of the partition wall 116 as shown in FIG. 1C. Therefore, the partition wall 116 and the dielectric pattern 108 support the two substrates 100 and 120 and can maintain the height of the gap between the two substrates 100 and 120.

しかし、この発明は、隔壁を平板光源内に配置しなければならないことには限定されない。この発明の別の実施例では、図2に示したように隔壁は平板光源内 には含まれない。隔壁が平板光源内に含まれないので、二枚の基板100、120の間のギャップの高さを保持するために、誘電体パターン108の組の高さは 好ましくは隔壁116の高さと同じにする。一方、図2の実施例では、蛍光体層110は各組の誘電体パターン108の二つの誘電体ストリップ108a、 108bの間、および誘電体ストリップ108a、108bの凸部と凹部を有する上面に塗布するだけでなく、二つの隣接する誘電体パターン108の組の間にも塗 布する。従って、蛍光体層の塗布領域をさらに増大し、それによって平板光源の輝度が向上される。 However, this invention is not limited to having to arrange | position a partition in a flat light source. In another embodiment of the present invention, the partition is not included in the flat light source as shown in FIG. Since the partition walls are not included in the flat light source, the height of the set of dielectric patterns 108 is preferably the same as the height of the partition walls 116 in order to maintain the height of the gap between the two substrates 100 and 120. To do. On the other hand, in the embodiment of FIG. 2, the phosphor layer 110 is applied between the two dielectric strips 108a and 108b of each set of dielectric patterns 108 and on the upper surface of the dielectric strips 108a and 108b having the convex and concave portions. In addition, it is applied between a pair of two adjacent dielectric patterns 108. Therefore, the application area | region of a fluorescent substance layer is further increased and the brightness | luminance of a flat light source is improved by it.

上記の図1A〜1Cと図2の実施例では、各組の誘電体パターン108は二つの誘電体ストリップ108a、108b(電極対)を備えているが、この発明は これには限定されない。この発明の平板光源の構造では、各組の誘電体パターン108は、図3に示したように三つ以上の誘電体ストリップ108a、108b および108c(3つの電極102)を有することもできる。特に、誘電体ストリップ108a、108bおよび108cの上面の輪郭は不均一であり、蛍光体 層110は誘電体ストリップ108a、108bおよび108cの間を被覆するだけでなく、誘電体ストリップ108a、108bおよび108cの上面を被覆 する。一方、平板光源にさらに隔壁116が含まれる場合、さらに蛍光体層110は隔壁116の表面上を被覆する。   1A to 1C and FIG. 2, each set of dielectric patterns 108 includes two dielectric strips 108a and 108b (electrode pairs), but the present invention is not limited to this. In the structure of the flat light source of the present invention, each set of dielectric patterns 108 may have three or more dielectric strips 108a, 108b and 108c (three electrodes 102) as shown in FIG. In particular, the contours of the top surfaces of the dielectric strips 108a, 108b and 108c are non-uniform, and the phosphor layer 110 not only covers between the dielectric strips 108a, 108b and 108c, but also the dielectric strips 108a, 108b and 108c. Cover the top surface of. On the other hand, when the flat plate light source further includes a partition wall 116, the phosphor layer 110 further covers the surface of the partition wall 116.

上記の平板光源の製造方法は、次のように示される。まず、図1A、1Bまたは1Cを参照すると、第一基板100が提供されている。それから、成膜および エッチング工程またはスクリーン印刷工程等の既知の方法で、第一基板100上に複数の電極102を形成する。一実施例では、この方法でさらに第一基板 100上に反射層112を形成する。   The manufacturing method of said flat light source is shown as follows. First, referring to FIG. 1A, 1B, or 1C, a first substrate 100 is provided. Then, a plurality of electrodes 102 are formed on the first substrate 100 by a known method such as a film formation and etching process or a screen printing process. In one embodiment, the reflective layer 112 is further formed on the first substrate 100 by this method.

次に、第一基板上に複数組の誘電体パターン108を形成し、ここで各組の誘電体パターン108は少なくとも二つの誘電体ストリップ108a、108bを 有し、各誘電体ストリップ108a、108bは対応する電極102の一方を被覆する。特に、形成した誘電体ストリップ108a、108bは各々上面202 と二つの側面204、206を有し、上面202は図4に示したように長手方向に沿った凸部と凹部を有する。誘電体ストリップ108a、108bの形成方法には、スクリー ン印刷工程、エッチング工程またはサンドブラスト工程が含まれる。 Next, a plurality of sets of dielectric patterns 108 are formed on the first substrate, wherein each set of dielectric patterns 108 has at least two dielectric strips 108a, 108b, each dielectric strip 108a, 108b being One of the corresponding electrodes 102 is coated. In particular, the formed dielectric strips 108a and 108b each have an upper surface 202 and two side surfaces 204 and 206, and the upper surface 202 has convex portions and concave portions along the longitudinal direction as shown in FIG. The method of forming the dielectric strips 108a and 108b includes a screen printing process, an etching process or a sand blasting process.

その後、各組の誘電体パターン108の誘電体ストリップ108a、108bの間に蛍光体層110を形成し、蛍光体層110はさらに(図5に示したよう に)、誘電体ストリップ108a、108bの上面202にも塗布する。それから、第二基板120が提供される。好ましい実施例では、第二基板120上に別 の蛍光体層114を形成する。シール部104は第一基板100と第二基板120の間に形成し、第一基板100と第二基板120は共に接続して、第一基板 100と第二基板120およびシール部104の間に空隙部106を形成する。その後、空隙部106に不活性ガスを充填する。電源をオンにすると、電極 102の間に生じた高エネルギ電子が不活性ガスに衝突し、プラズマを形成する。   Thereafter, a phosphor layer 110 is formed between the dielectric strips 108a and 108b of each set of dielectric patterns 108, and the phosphor layer 110 is further formed (as shown in FIG. 5), and the dielectric strips 108a and 108b. It is also applied to the upper surface 202. Then, a second substrate 120 is provided. In a preferred embodiment, another phosphor layer 114 is formed on the second substrate 120. The seal portion 104 is formed between the first substrate 100 and the second substrate 120, and the first substrate 100 and the second substrate 120 are connected together, and between the first substrate 100, the second substrate 120, and the seal portion 104. A gap 106 is formed. Thereafter, the void 106 is filled with an inert gas. When the power supply is turned on, high-energy electrons generated between the electrodes 102 collide with the inert gas and form plasma.

好ましい実施例によると、基板100、120の接続前、特に蛍光体層110の塗布前に、この方法ではさらに第一基板100または第二基板120上に隔壁 116を形成する。隔壁116を平板光源内に形成する場合、より詳細には、蛍光体層110の塗布工程中に隔壁116の表面にさらに蛍光体層110を塗布す る。平板光源内に隔壁を形成しない場合、図2に示したように蛍光体層110の塗布工程中に、二つの隣接する誘電体パターン108の組の間にさらに蛍光体層110を塗布する。   According to a preferred embodiment, the barrier wall 116 is further formed on the first substrate 100 or the second substrate 120 in this method before the connection of the substrates 100, 120, in particular, before the phosphor layer 110 is applied. When the barrier ribs 116 are formed in a flat light source, more specifically, the phosphor layer 110 is further applied to the surface of the barrier ribs 116 during the step of applying the phosphor layer 110. When the barrier rib is not formed in the flat light source, the phosphor layer 110 is further applied between two adjacent dielectric patterns 108 during the phosphor layer 110 application step as shown in FIG.

以上の観点から、この発明の平板光源およびその製造方法において形成された誘電体ストリップは不均一な輪郭としての凸部と凹部を備えた上面を有するので、蛍光体層は二つの 誘電体ストリップの間に塗布されるだけでなく、誘電体ストリップの上面の凸部と凹部にも塗布される。従って、既存の平板光源に比べて、この発明の平板光 源の蛍光体層の塗布領域はより大きくなり、誘電体ストリップの凹部でクロストーク現象が発生でき、それによって以前は発光できなかったこの部分がクロス トーク現象のために発光できるようになる。こうして、平板光源の輝度を向上できる。 From the above viewpoint, since the dielectric strip formed in the flat light source and the manufacturing method thereof according to the present invention has an upper surface with a convex portion and a concave portion as a non-uniform contour, the phosphor layer is formed of two dielectric strips. In addition to being applied in between, it is also applied to the protrusions and recesses on the top surface of the dielectric strip. Therefore, compared with the existing flat light source, the coating area of the phosphor layer of the flat light source of the present invention is larger, and the crosstalk phenomenon can occur in the concave portion of the dielectric strip, thereby preventing the light emission that could not be emitted before. The part can emit light due to the crosstalk phenomenon. Thus, the luminance of the flat light source can be improved.

さらに、蛍光体層は、隔壁の表面または二つの隣接する誘電体パターンの組の間等、従来技術では蛍光体層を塗布していなかった他の部分にも塗布される。こ うして、蛍光体層の塗布領域を増大し、それによって平板光源の輝度を向上できる。さらに、平板光源の全体の発光均一性が改善される。   Furthermore, the phosphor layer is also applied to other portions where the phosphor layer was not applied in the prior art, such as between the surface of the barrier ribs or between two sets of adjacent dielectric patterns. In this way, the coating area of the phosphor layer can be increased, thereby improving the luminance of the flat light source. Furthermore, the overall light emission uniformity of the flat light source is improved.

この発明は以上の好ましい実施例において開示されてきたが、それらには限定されない。当業者には明らかなように、この発明の精神と範囲から逸脱すること なく、いくつかの修正および革新を行うことができる。従って、この発明の範囲は、添付の請求によって定義されるべきである。   While this invention has been disclosed in the above preferred embodiments, it is not limited thereto. It will be apparent to those skilled in the art that several modifications and innovations can be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention should be defined by the appended claims.

添付の図面は、発明をさらに理解するために含められ、この明細書に組み込まれ、その一部を構成する。図面は発明の実施例を示し、開示内容と共に、発明の原理の説明に役立つ。   The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the disclosure, serve to explain the principles of the invention.

この発明の複数の実施例による平板光源の概略断面図である。It is a schematic sectional drawing of the flat light source by several Example of this invention. この発明の複数の実施例による平板光源の概略断面図である。It is a schematic sectional drawing of the flat light source by several Example of this invention. この発明の複数の実施例による平板光源の概略断面図である。It is a schematic sectional drawing of the flat light source by several Example of this invention. この発明の別の実施例による平板光源の概略断面図である。It is a schematic sectional drawing of the flat light source by another Example of this invention. この発明のさらに別の実施例による平板光源の概略断面図である。It is a schematic sectional drawing of the flat light source by another Example of this invention. この発明の好ましい実施例による平板光源の誘電体パターンの三次元概略図である。FIG. 3 is a three-dimensional schematic diagram of a dielectric pattern of a flat light source according to a preferred embodiment of the present invention. この発明の好ましい実施例による平板光源の誘電体ストリップの一つの延長方向に沿った断面図である。FIG. 3 is a cross-sectional view along one extension direction of a dielectric strip of a flat light source according to a preferred embodiment of the present invention.

100 第一基板
102 電極
104 シール部
106 空隙部
108 誘電体パターン
108a〜108c 誘電体ストリップ
110 蛍光体層
112 反射層
114 蛍光体層
116 隔壁
120 第二基板
202 上面
204 側面
DESCRIPTION OF SYMBOLS 100 1st board | substrate 102 Electrode 104 Sealing part 106 Space | gap part 108 Dielectric pattern 108a-108c Dielectric strip 110 Phosphor layer 112 Reflecting layer 114 Phosphor layer 116 Partition 120 Second board 202 Upper surface 204 Side surface

Claims (13)

その上に電極を配置した第一基板と、
第二基板と、
第一基板と第二基板の間に配置し、第一基板と第二基板の間に空隙部を形成するシール部と、
第一基板と第二基板の間の空隙部に形成し、その各組が互いに平行な少なくとも二つの誘電体ストリップを備え、各誘電体ストリップが対応する電極の一つを被覆し、前記誘電体ストリップが各々上面と二つの側面を有し、上面が長手方向に沿った凸部と凹部を有した複数組の誘電体パターンと、
第一基板と第二基板の間の空隙部内に設置され、第一基板と第二基板のギャップの高さを保持し、二つの隣接する誘電体パターンの組の間に位置する複数の隔壁と、
各組の誘電体パターンの誘電体ストリップの間に配置した蛍光体層を有し、さらに前記誘電体ストリップの凸部及び凹部上に蛍光体層を配置した平板光源。
A first substrate having an electrode disposed thereon;
A second substrate;
A seal portion disposed between the first substrate and the second substrate, and forming a gap between the first substrate and the second substrate;
Forming a gap between the first substrate and the second substrate, each set comprising at least two dielectric strips parallel to each other, each dielectric strip covering one of the corresponding electrodes, Each of the strips has an upper surface and two side surfaces, and the upper surface has a plurality of sets of dielectric patterns having protrusions and recesses along the longitudinal direction ;
It is installed in a gap portion between the first substrate and the second substrate, holding the height of the first substrate and the gap of the second substrate, a plurality of partition walls located between two adjacent dielectric pattern set ,
A flat plate light source having a phosphor layer arranged between dielectric strips of each set of dielectric patterns, and further arranging a phosphor layer on the convex and concave portions of the dielectric strip.
隣接する誘電体パターンの組の間に、さらに蛍光体層を配置した請求項1記載の平板光源。   The flat light source according to claim 1, wherein a phosphor layer is further arranged between adjacent sets of dielectric patterns. 隔壁の表面に、さらに蛍光体層を塗布した請求項1記載の平板光源。   The flat light source according to claim 1, wherein a phosphor layer is further applied to the surface of the partition wall. 誘電体ストリップの高さが、隔壁より低い請求項1記載の平板光源。   The flat light source according to claim 1, wherein the height of the dielectric strip is lower than that of the partition wall. さらに、第一基板の表面に配置した反射層を有する請求項1記載の平板光源。   The flat light source according to claim 1, further comprising a reflective layer disposed on the surface of the first substrate. さらに、第二基板上に配置した別の蛍光体層を有する請求項1記載の平板光源。   Furthermore, the flat light source of Claim 1 which has another fluorescent substance layer arrange | positioned on the 2nd board | substrate. 第一基板を提供し、
第一基板上に複数の電極を形成し、
第一基板上に複数組の誘電体パターンを形成し、各組の誘電体パターンが互いに平行な少なくとも二つの誘電体ストリップを備え、各誘電体ストリップが対応する電極の一つを
被覆し、形成した誘電体ストリップが各々上面と二つの側面を備え、上面が長手方向に沿った凸部と凹部を有し、
各組の誘電体パターンの誘電体ストリップの間と誘電体ストリップの凸部及び凹部上に蛍光体層を形成し、
第二基板を提供し、
第一基板と第二基板の間の空隙部内に、第一基板と第二基板のギャップの高さを保持し、二つの隣接する誘電体パターンの組の間に位置する複数の隔壁を設置し、
第一基板と第二基板の間にシール部を形成し、第一基板と第二基板を共に接続する平板光源の製造方法。
Providing the first substrate,
Forming a plurality of electrodes on the first substrate;
Forming a plurality of sets of dielectric patterns on the first substrate, each set of dielectric patterns comprising at least two dielectric strips parallel to each other, each dielectric strip covering and forming one of the corresponding electrodes The dielectric strips each have an upper surface and two side surfaces, the upper surface has a convex part and a concave part along the longitudinal direction ,
Forming a phosphor layer between the dielectric strips of each set of dielectric patterns and on the convex and concave portions of the dielectric strip;
Providing a second substrate,
In the gap portion between the first substrate and the second substrate, holding the height of the first substrate and the gap of the second substrate, and installing a plurality of partition walls located between two adjacent dielectric pattern set ,
A method of manufacturing a flat light source, wherein a seal portion is formed between a first substrate and a second substrate, and the first substrate and the second substrate are connected together.
誘電体ストリップの形成に、スクリーン印刷工程、エッチング工程またはサンドブラスト工程を行うことが含まれる請求項記載の平板光源の製造方法。 The method of manufacturing a flat light source according to claim 7 , wherein the formation of the dielectric strip includes performing a screen printing process, an etching process, or a sandblasting process. 蛍光体層を形成するステップでさらに、隣接する誘電体パターンの組の間に蛍光体層を塗布する請求項記載の平板光源の製造方法。 8. The method of manufacturing a flat light source according to claim 7 , further comprising applying a phosphor layer between adjacent pairs of dielectric patterns in the step of forming the phosphor layer. さらに、隔壁の表面に蛍光体層を塗布する請求項記載の平板光源の製造方法。 Furthermore, the manufacturing method of the flat light source of Claim 7 which apply | coats a fluorescent substance layer on the surface of a partition. 誘電体ストリップの高さが、隔壁より低い請求項記載の平板光源の製造方法。 The method of manufacturing a flat light source according to claim 7 , wherein the height of the dielectric strip is lower than that of the partition wall. さらに、第一基板上に反射層を形成する請求項記載の平板光源の製造方法。 Furthermore, the manufacturing method of the flat light source of Claim 7 which forms a reflection layer on a 1st board | substrate. さらに、第二基板上に別の蛍光体層を形成する請求項記載の平板光源の製造方法。 Furthermore, the manufacturing method of the flat light source of Claim 7 which forms another fluorescent substance layer on a 2nd board | substrate.
JP2006020821A 2006-01-30 2006-01-30 Flat light source and manufacturing method thereof Expired - Fee Related JP4694379B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006020821A JP4694379B2 (en) 2006-01-30 2006-01-30 Flat light source and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006020821A JP4694379B2 (en) 2006-01-30 2006-01-30 Flat light source and manufacturing method thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2010228826A Division JP5128648B2 (en) 2010-10-08 2010-10-08 Flat light source and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2007200816A JP2007200816A (en) 2007-08-09
JP4694379B2 true JP4694379B2 (en) 2011-06-08

Family

ID=38455201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006020821A Expired - Fee Related JP4694379B2 (en) 2006-01-30 2006-01-30 Flat light source and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4694379B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011018658A (en) * 2010-10-08 2011-01-27 Chunghwa Picture Tubes Ltd Planar light source, and manufacturing method of the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002298743A (en) * 2001-03-30 2002-10-11 Toray Ind Inc Manufacturing method of base board for plasma display
JP2004241379A (en) * 2003-01-15 2004-08-26 Toray Ind Inc Plasma display member and plasma display, as well as manufacturing method of plasma display member
JP2005032722A (en) * 2003-07-12 2005-02-03 Samsung Electronics Co Ltd Planar light source device, manufacturing method of the same, backlight assembly utilizing the same, and liquid crystal display device having the backlight assembly
JP2005276808A (en) * 2004-03-22 2005-10-06 Lg Philips Lcd Co Ltd Flat plate light-emitting lamp device and manufacturing method therefor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002298743A (en) * 2001-03-30 2002-10-11 Toray Ind Inc Manufacturing method of base board for plasma display
JP2004241379A (en) * 2003-01-15 2004-08-26 Toray Ind Inc Plasma display member and plasma display, as well as manufacturing method of plasma display member
JP2005032722A (en) * 2003-07-12 2005-02-03 Samsung Electronics Co Ltd Planar light source device, manufacturing method of the same, backlight assembly utilizing the same, and liquid crystal display device having the backlight assembly
JP2005276808A (en) * 2004-03-22 2005-10-06 Lg Philips Lcd Co Ltd Flat plate light-emitting lamp device and manufacturing method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011018658A (en) * 2010-10-08 2011-01-27 Chunghwa Picture Tubes Ltd Planar light source, and manufacturing method of the same

Also Published As

Publication number Publication date
JP2007200816A (en) 2007-08-09

Similar Documents

Publication Publication Date Title
US6744195B2 (en) Flat luminescence lamp
US6583554B2 (en) Flat luminescent lamp and method for manufacturing the same
KR100602873B1 (en) Back-Light Unit utilizing Flat Fluorescent Lamp
JP4694379B2 (en) Flat light source and manufacturing method thereof
KR100359737B1 (en) Flat fluorescent lamp
JP5128648B2 (en) Flat light source and manufacturing method thereof
KR100437953B1 (en) Flat fluorescent lamp and lamp assembly utilizing the same
CN100464232C (en) Plane lamp source
JPH117895A (en) Plasma display panel and forming method of its partition wall
KR100444903B1 (en) Flat Fluorescent Lamp and Back-light Unit Utilizing Flat Fluorescent Lamp
US7710011B2 (en) Flat light source
CN100562965C (en) Planar lamp source and manufacture method thereof
US7671524B2 (en) Flat light source having phosphor patterns in an edge region
KR20000005671A (en) Flat fluorescent lamp
KR20010004118A (en) Method for forming seal layer of plasma display panel
JPH10288842A (en) Exposure device and formation of fluorescent surface
TWI286251B (en) Flat light source and fabricating method thereof
KR100263850B1 (en) Plasma display panel
KR100626047B1 (en) Flat type lamp
KR100606248B1 (en) flat-format fluorescent lamp
US20080106179A1 (en) Flat light module and manufacturing method thereof
KR100698638B1 (en) Surface light source for illumination
KR20060122511A (en) Surface light source lamp and backlight device providing with the same
KR20000030746A (en) Protrude Electrode Type Flat Fluorescent Lamp
KR20060072818A (en) Manufacturing method of plasma display panel

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20081031

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090109

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090330

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091106

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20091112

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100202

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100610

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101008

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20101203

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110121

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110121

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110209

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110223

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140304

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4694379

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees