JP4687750B2 - Digital camera and image signal processing storage medium - Google Patents

Description

  The present invention relates to a digital camera that stores a subject as electronically compressed image data and a storage medium that stores an image signal processing program.

  2. Description of the Related Art Conventionally, a finder device in which a subject image passing through a photographing lens is guided by a quick return mirror, an imaging device such as a CCD that is arranged at the rear stage of the quick return mirror and outputs image data, and an imaging device Processing circuit that performs image processing such as white balance and gamma correction on the image data output from the image data, and a compression circuit that compresses the image-processed data using a method such as JPEG and stores it in a storage medium such as a flash memory There is known an electronic still camera including a monitor for displaying data after image processing. In the image processing circuit, parameters such as an R gain and B gain for white balance adjustment or a gradation curve for γ correction are calculated by a predetermined algorithm based on image data output from the imaging apparatus. Further, the image data is converted into 8 × 8 luminance data Y and color difference data Cr and Cb, respectively, for compression by the JPEG method.

  In such a conventional electronic still camera imaging device, image preprocessing such as white balance and γ correction, and image postprocessing that formats the data after image preprocessing to JPEG compression follow the reading of the CCD. Each line is processed. For this reason, in a high-quality electronic still camera in which the number of pixels of the CCD exceeds 2 million pixels, the capacity of the line buffer memory used for pipeline operations and the like becomes enormous, resulting in an expensive camera. is there. This problem can be explained as follows.

  That is, conventionally, when signal processing is performed on the output from the solid-state image sensor, N × M single-screen image data output from the image sensor is output point-sequentially for each line, so pixel interpolation processing, filter processing, etc. For example, when performing 5 × 5 filter processing, a line buffer memory for 4 lines is required. In other words, processing is possible only after image data for four lines is stored in the memory. This line buffer memory is required for four lines for each of various processes such as filter processing and interpolation processing.

  As described above, if a line buffer memory of 4 lines is provided for each processing such as the above-described filter processing and interpolation processing, the proportion occupied by the memory increases, and the number of gates of the one-chip processing IC increases. Will increase and the cost will increase. In particular, in a high-pixel type image sensor that exceeds 2 million pixels, the number of pixels in one line increases, and the cost is particularly high. Further, when the line buffer memory is installed outside the one-chip processing IC, if the input / output pin is 10 bits, 20 pins are required, and each line buffer memory needs 20 input / output pins. The package of the processing IC becomes large.

An object of the present invention is to provide a digital camera that can reduce the cost without increasing the capacity of the buffer memory even when the number of pixels increases.
Another object of the present invention is to provide a storage medium storing a program for performing signal processing that can reduce the capacity of a buffer memory even for image data captured by an image sensor having a large number of pixels.

The present invention will be described with reference to FIGS. 1 and 2 showing an embodiment.
(1) According to the first aspect of the present invention, the imaging device 73 (26) that captures a subject image passing through the photographing lens 91 and outputs the image data, and the N rows and M columns of image data output from the imaging device 26 A first image processing circuit 29 that performs line-sequential preprocessing for the first image data, and a first storage device 30 that temporarily stores the first image data for at least one frame; A block of n rows and m columns (n is a positive integer satisfying N> n ≧ 3 and m is a positive integer satisfying M> m ≧ 3) is input from the first image data. Then, by performing formatting processing including at least two stages of filter processing in which the block size is sequentially reduced in units of blocks without using the M column line buffer memory, (n−i) rows (m−j ) Column (i satisfies n> i ≧ 2) A second image processing circuit 29 for generating second image data having a size of a positive integer, j being a positive integer satisfying m> j ≧ 2, and (n−i) rows (m−j) And a recording processing circuit 33 that sequentially compresses and records the second image data in the column, and the second image data in the (ni) row (m−j) column has a size necessary for the compression recording processing. It is characterized by being.
(2) According to the invention of claim 2, in the digital camera of claim 1, the first image data includes color component data, and the second image processing circuit reads the common image read from the first image data. Luminance block processing for generating a luminance block of (n−i) rows (m−j) columns based on data of blocks of n rows and m columns, and (n−i) first of the rows (m−j) columns. And color difference block processing for generating a color difference block and a second color difference block.
(3) The invention of claim 3 further comprises a second storage device for temporarily storing the second image data in the digital camera of claim 1 or 2, wherein the recording processing circuit is a second storage device. The second image data stored in the recording process is recorded .
(4) According to a fourth aspect of the invention, in the digital camera of the third aspect, the first storage device and the second storage device are the same storage device .
(5) According to the invention of claim 5, in the digital camera of claim 1, (n−i1) rows (m−j1) columns (i1 is extracted from the first image data of a block of n rows and m columns) Median processing is performed on image data of a positive integer satisfying i> i1 ≧ 1, and j1 is a positive integer satisfying j> j1 ≧ 1 .
(6) The invention of claim 6 is the digital camera according to any one of claims 1 to 5, wherein the image pickup device picks up a subject image and outputs an analog image signal; And an A / D conversion circuit for converting the image data .
(7) The invention of claim 7 is the digital camera according to any one of claims 1 to 6, wherein the first image processing circuit performs white balance adjustment on the image data output from the imaging device. The second image processing circuit further includes a white balance fine adjustment coefficient calculation circuit that includes a balance adjustment means and calculates a white balance fine adjustment coefficient based on image data after white balance adjustment output from the white balance adjustment means. And white balance fine adjustment means for performing white balance fine adjustment processing on the first image data using a white balance fine adjustment coefficient .

  In the section of the means for solving the above-described problem to explain the configuration of the present invention, the drawings of the embodiments are used for easy understanding of the present invention, but the present invention is thereby limited to the embodiments. It is not something.

  According to the present invention, pre-processing such as γ correction and white balance correction is performed on the image data output from the imaging apparatus in line order for each row, and n rows and m columns are performed on the pre-processed image data. Since the recording process and the formatting process before the compression process are performed for each block in sequence, the buffer is used especially when processing a high-quality type image captured by an imaging apparatus having more than 2 million pixels. Costs can be reduced without increasing the memory capacity. In addition, when the processing chip is created by hardware, it is possible to realize a small section and cost reduction.

  Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 1, the single-lens reflex electronic still camera according to this embodiment includes a camera body 70, a finder device 80 attached to and detached from the camera body 70, a photographing lens 91, and a diaphragm 92. And an interchangeable lens 90 to be attached and detached. The subject light enters the camera body 70 through the interchangeable lens 90 and is guided to the finder device 80 by the quick return mirror 71 located at the position indicated by the dotted line before the release, and forms an image on the finder mat 81. The subject image is further guided to the eyepiece lens 83 by the pentaprism 82. After the release, the quick return mirror 71 rotates to the position indicated by the solid line, and the subject light forms an image on the imaging device 73 via the shutter 72. Before the release, the subject image enters the white balance sensor 86 through the prism 84 and the imaging lens 85, and the color temperature of the subject image is detected.

  FIG. 2 is a circuit block diagram of the embodiment. The CPU 21 receives a half-press signal and a full-press signal from a half-press switch 22 and a full-press switch 23 that are linked to the release button. In response to a command from the CPU 21, the CCD 26 of the imaging device 73 is driven and controlled via the timing generator 24 and the driver 25. The timing generator 24 controls the operation timing of the analog processing circuit 27 and the A / D conversion circuit 28. Further, the white balance detection processing circuit 35 starts to be driven by a signal from the CPU 21.

  When the full-push switch 23 is turned on following the half-push switch 22 being turned on, the quick return mirror 71 is rotated upward, and the subject light from the interchangeable lens 90 forms an image on the light receiving surface of the CCD 26. The CCD 26 stores signal charges corresponding to the brightness of the subject image. The signal charges accumulated in the CCD 26 are discharged by the driver 25 and input to an analog signal processing circuit 27 including an AGC circuit and a CDS circuit. The analog signal processing circuit 27 performs analog processing such as gain control and noise removal on the analog image signal, and then the digital signal is converted by the A / D conversion circuit 28. The digitally converted signal is guided to an image processing circuit 29 configured as, for example, an ASIC, where image preprocessing such as white balance adjustment, contour compensation, and gamma correction is performed.

  The white balance detection processing circuit 35 includes a white balance sensor 35A (a white balance sensor 86 in FIG. 1) that is a color temperature sensor, an A / D conversion circuit 35B that uses an analog signal from the white balance sensor 35A as a digital signal, and a digital And a CPU 35C that generates a white balance adjustment signal based on the color temperature signal. The white balance sensor 35A includes a plurality of photoelectric conversion elements having sensitivity to red R, blue B, and green G, for example, and receives an optical image of the entire object scene. The CPU 35C calculates the R gain and the B gain based on the outputs of the plurality of photoelectric conversion elements. These gains are transferred to a predetermined register of the CPU 21 and stored. Further, the white balance sensor 86 of FIG. 1 can also be constituted by a two-dimensional CCD of 24 columns × 20 rows. In this case, the CCD is divided into 16 regions, and a plurality of elements having sensitivity to RGB are provided in each region. Array.

  The image data that has undergone image pre-processing is further subjected to format processing (image post-processing) for JPEG compression, and then the image data is temporarily stored in the buffer memory 30.

  The image data stored in the buffer memory 30 is processed into display image data by the display image creation circuit 31, and is displayed as a photographing result on an external monitor 32 such as an LCD. The image data stored in the buffer memory 30 is subjected to data compression at a predetermined ratio by the compression circuit 33 using the JPEG method, and is recorded in a storage medium (PC card) 34 such as a flash memory.

  3 and 4 are block diagrams showing details of the image processing circuit 29. FIG. FIG. 3 shows a line processing circuit 100 that performs signal processing on the image data from the CCD 26 for each line, and performs the above-described image preprocessing. FIG. 4 is a block processing circuit that performs signal processing on the image data signal-processed by the line processing circuit 100 in units of blocks of 20 × 20 pixel region, 16 × 16 pixel region, 12 × 12 pixel region, or 8 × 8 pixel region. 200, and the image post-processing described above is performed. The image processing circuit 29 is realized as software using a plurality of processors. However, in this specification, it will be described as hardware for convenience.

  The line processing circuit 100 shown in FIG. 3 performs various signal processing to be described later on the 12-bit R, G, and B signals output from the A / D conversion circuit 28. It has a clamp circuit 102, a gain circuit 103, a white balance circuit 104, a black level circuit 105, a γ correction circuit 106, and an average value and histogram calculation circuit 107.

  The defect correction circuit 101 corrects data from a defective pixel (specified in advance and its address is set in a register) dot-sequentially for each line with respect to the output of the CCD 26. The digital clamp circuit 102 subtracts a weighted average of a plurality of pixel data used as so-called optical black from each pixel data of the line in a dot sequential manner for each line with respect to the output of the CCD 26. The gain circuit 103 applies a predetermined gain to each of the R, G, and B signals output from the CCD 26 in a dot-sequential manner with respect to the output of the CCD 26, and corrects variations in sensitivity of the CCD 26. Is performed on the G signal, and variation in the sensitivity ratio of the CCD 26 is performed on the R and B signals.

  The white balance circuit 104 performs R and B gains, which are white balance adjustment coefficients determined in advance as described above and stored in the register of the CPU 21, in a dot-sequential manner with respect to the output of the CCD 26, as described above. Multiply by B signal. In the present invention, as described later, the white balance fine adjustment gain is further calculated based on the image data corrected by the white balance circuit 104 to finely adjust the white balance. The black level circuit 105 adds the values determined in advance and stored in the register of the CPU 21 to the R, G, and B signals dot-sequentially for each line with respect to the output of the CCD 26. The γ correction circuit 106 performs γ correction on the output of the CCD 26 in a dot-sequential manner for each line using a gradation lookup table. Note that 12-bit R, G, and B signals are converted into 8-bit data by γ correction.

  The average value and histogram calculation circuit 107 extracts, for example, image data of a 512 × 512 region centered on the central portion of the focus detection region from the image data after γ correction, and performs white balance fine adjustment for the R signal. The adjustment gain RFgain and the B signal white balance fine adjustment gain BFgain are calculated by the following equations (1) and (2), for example. The gains RFgain and BFgain are stored in a register. For example, when a color filter is arranged on a 512 × 512 pixel area as shown in FIG. 5, the average values of the R, G, B signals are calculated by equations (3) to (5), and (1) , (2), the white balance fine adjustment gain from the ratio between the average value Gave of the G signal and the average value Rave of the R signal and the ratio of the average value Gave of the G signal and the average value Bave of the B signal. Calculate RFgain and BFgain.

このような平均値方式によると、画像データのＲＧＢの各信号の階調の平均値を求めたことになり、経験的にホワイトバランスの調整結果（全体的なホワイトバランス）が良好となる。

According to such an average value method, the average value of the gradations of the RGB signals of the image data is obtained, and the white balance adjustment result (overall white balance) is empirically improved.

Based on the average value and the histogram of the luminance levels of the R, G, and B signals calculated by the histogram calculation circuit 107, the white balance fine adjustment RFgain and BFgain may be calculated as follows. The average value and histogram calculation circuit 107 calculates a histogram of luminance levels of R, G, and B signals. That is, the number of each color for each luminance level is calculated, and histograms as shown in FIGS. 6A to 6C are calculated. Here, if the 95% level value of each color of R, G, B is R = 180, B = 200, G = 190, RFgain and BFgain are RFgain = 190/180, BFgain for white balance fine adjustment = It can be calculated as 190/200. The 95% level value is a luminance level value of the number of dots that is 95% of the largest number of dots.
According to such a histogram method, the histogram has a shape including the dispersion of the gradation distribution of each RGB signal of the image data, and if the white balance fine adjustment gain is obtained from the shape, it is concentrated on a predetermined portion (white point portion). Thus, the white balance can be adjusted, and the white balance adjustment result is empirically improved. Note that the average value method and the histogram method may be combined.

  The block processing circuit 200 shown in FIG. 4 includes a white balance fine adjustment circuit 210 and an interpolation / contour processing circuit 220, and performs various signal processing for each n × m pixel data, that is, for each block. The white balance fine adjustment circuit 210 performs processing up to the γ correction circuit 106 and stores the R signal and the B signal stored in the buffer memory 30 for each R and B signal in the 20 × 20 pixel region. The white balance fine adjustment gain RFgain and BFgain calculated by the average value circuit 107 are respectively multiplied to perform fine adjustment of the white balance.

The interpolation / contour processing circuit 220 includes a G interpolation circuit 221, a bandpass filter (BPF) 222, a clip circuit 223, a gain circuit 224, a low-pass filter (LPF) 225, a color difference signal generation circuit 226, an interpolation / A low-pass filter (LPF) circuit 228, a matrix circuit 229, an adder 230, and a median circuit 232 are provided. The image data after white balance fine adjustment is subjected to JPEG method for each block data of 20 × 20 pixel area. Format processing for data compression is performed to generate an 8 × 8 pixel area Y signal and an 8 × 8 pixel area Cb signal and Cr signal. The luminance signal Y includes a low-frequency component luminance signal Y1 and a high-frequency component contour signal Y2 as will be described later.

  A block signal of a 20 × 20 pixel area is input from the white balance adjustment circuit 210 to the G interpolation circuit 221, and the G component is applied to the pixel area of the R signal or the B signal for the data of the center 16 × 16 pixel area. Calculate by interpolation. That is, as shown in FIG. 7, with respect to the input data D20 of the 20 × 20 pixel region, the vacant point (3 × 3) in the center of the 5 × 5 pixel region data D51 (1 row 1 column to 5 rows 5 columns) The G component of the pixel and the B signal is obtained), and this value is replaced with the G component of the 3 × 3 pixel of the output data D16 in the 16 × 16 pixel area (B is surrounded by a circle). To do.

  Next, with respect to the input data D20 of the 20 × 20 pixel region, the vacant point (the pixel of 4 rows and 4 columns) at the center of the 5 × 5 pixel region data D52 (2 rows 2 columns to 6 rows 6 columns), the R signal is The obtained G component is calculated, and this value is replaced with the G component of the 4 × 4 pixel (R surrounded by ○) of the output data D16 in the 16 × 16 pixel region. By repeating such processing, G interpolation processing is performed for all vacancies in the 16 × 16 pixel region, and output data D16 is obtained. Then, the output data D12 of the 12 × 12 pixel area is output to the band pass filter 222 and the low pass filter 225, while the output data D16 of the 16 × 16 pixel area is output to the color difference signal generation circuit 226.

  The band-pass filter 222 is an intermediate frequency component (however, a high-frequency component that can extract the contour of the subject) of the G signal in the 12 × 12 pixel region output from the G interpolation circuit 221. Call out). That is, as shown in FIG. 8, the BPF output data is obtained by multiplying the 5 × 5 pixel region data D5 (5 rows 5 columns to 9 rows 9 columns) by the band pass filter coefficient for the input data D12 of the 12 × 12 pixel region. Then, the value is replaced as 7 × 7 data (bold G) in the output data D8 of the 8 × 8 pixel area. By repeating such processing, all the pixel data in the 8 × 8 pixel region are replaced with G data after BPF, and output data D8 is generated.

  The clip circuit 223 clips and cuts each 8 × 8 pixel area data D8 output from the bandpass filter 222 at a set level. The gain circuit 224 multiplies the output of the clip circuit 223 by a predetermined gain.

  The low-pass filter 225 extracts a low-frequency component from the G signal in the 12 × 12 pixel area output from the G interpolation circuit 221. That is, as shown in FIG. 9, the LPF output data is obtained by multiplying the 5 × 5 pixel region data D5 (5 rows 5 columns to 9 rows 9 columns) by the low pass filter coefficient for the input data D12 of the 12 × 12 pixel region. The value is replaced with 7 × 7 data (hatching area) of the output data D8 of the 8 × 8 pixel area. By repeating such processing, all pixel data in the 8 × 8 pixel region is replaced with G data after LPF, and output data D8 is generated.

  As shown in FIG. 10, the color difference signal generation circuit 226 includes RGB signal input data D16-1 in the 16 × 16 pixel region that is the output of the white balance fine adjustment circuit 210 and 16 × 16 pixels that is the output of the G interpolation circuit 221. Based on the G signal input data D16-2 in the region, intermediate data D16-3 including the (BG) signal and the (RG) signal is generated. Further, the intermediate data D16-3 is separated into (BG) color difference signal output data D16-4 and (RG) color difference signal output data D16-5.

  The interpolation / LPF circuit 228 inputs the 8-bit (B−G) signal and the (R−G) signal of the 16 × 16 pixel region from the color difference signal generation circuit 226, and outputs (B -G) and (RG) signal are respectively interpolated and low-pass filtering processing for extracting a low-band signal is also performed. As a result, the (B-G) signal and (R- G) The signal is output to the Cb / Cr matrix portion of the matrix circuit 229. Further, the (B−G) signal and the (R−G) signal in the 8 × 8 pixel region are output to the Y matrix portion of the matrix circuit 229.

When the (R−G) data of the 5 × 5 pixel region is expressed as shown in FIG. 11, the interpolation calculation and the low-pass filtering calculation are expressed by the following equation (6).

  In general, when an interpolation filter and a band-limited LPF are applied simultaneously, there are the following filter coefficient restrictions. For simplicity, it will be described in one dimension. Consider a case where there are actual sample points in N cycles among the sample points after interpolation. For example, a, a, b, b, a, a, b, b,... (Where a is an actual sample point and b is a sample point to be interpolated. In this example, 4 is used. Period). When this is interpolated with an odd-order symmetric digital filter of (2n + 1) th order (where (2n + 1) is greater than N), if the actual sample points are uniform, the sample points after interpolation must also be uniform. Therefore, there are the following filter coefficient restrictions.

ただし、ｉはフィルタ係数が（２ｎ＋１）以下に収まる０以上の整数
ｋはｎ未満の０以上の整数 If C (k) is the k-th filter coefficient, the sum of the N coefficient sets must be equal to each other as follows.

Where i is an integer greater than or equal to 0 so that the filter coefficient falls within (2n + 1)
k is an integer greater than or equal to 0 and less than n

In the two-dimensional case, a two-dimensional filter may be configured by multiplying the same restriction filter in the horizontal direction and the vertical direction. In this embodiment, as shown in FIG. 5 and FIG. 11, sample points having a period of two pixels are interpolated, so that N = 2, and the filter coefficients must be equal to the even-order sum and the odd-order sum. That is,
ΣC (2 * i) = ΣC (2 * i + 1)
In the case of a 5th order × 5th order symmetric filter such as the above equation (6) in two dimensions,
4 * kc1 + 2 * kc3 + 4 * kc5 + 2 * kc7 + kc9
= 4 * kc2 + 4 * kc4 + 2 * kc6 + 2 * kc8
It becomes.

  For example, (R−G) signal interpolation / LPF processing will be described with reference to FIG. For the (R−G) signal of the input data D16 in the 16 × 16 pixel region, the 5 × 5 pixel region data D5 (3 rows 3 columns to 7 rows 7 columns) is multiplied by the interpolation / LPF filter coefficient, and the center region (5 (R−G) data of (row 5 columns) is calculated, and this is replaced with data of 5 rows and 5 columns of the output data D12 of the 12 × 12 pixel region. By repeating such processing, all the pixel data in the 12 × 12 pixel region is subjected to interpolation / LPF processing for the (R−G) signal, and output data D12 is obtained. Similar processing is performed on the (B−G) signal to generate output data of a 12 × 12 pixel region.

The matrix circuit 229 includes a Y matrix portion, a Cb matrix portion, and a Cr matrix portion. The Y matrix unit inputs the (B−G) signal and the (R−G) signal of the 8 × 8 pixel region from the interpolation / LPF circuit 228 and also inputs the G signal of the 8 × 8 pixel region from the low-pass filter 225. Then, the luminance signal Y1 of the low frequency component of the 8 × 8 pixel region is generated by the following equation (7).

The Cb matrix portion and the Cr matrix portion respectively receive the (B−G) signal and the (R−G) signal of the 12 × 12 pixel region from the interpolation / LPF circuit 228, and the following equations (8) and (9) A Cb signal and a Cr signal of a 12 × 12 pixel region are generated.

The adder 230 adds the luminance signal Y1 of the low frequency component of the 8 × 8 pixel region output from the matrix circuit 229 and the contour extraction signal Y2 of the high frequency component of the 8 × 8 pixel region output from the gain circuit 224. . The contour extraction signal Y2 output from the gain circuit 224 is obtained by extracting a high frequency component from the G signal of the 12 × 12 pixel region subjected to G interpolation, that is, by extracting the contour. Accordingly, the luminance / contour extraction signal Y (Y1 + Y2) of the entire image is calculated by adding the luminance signal Y1 calculated by the equation (7) by the adder 230 and the contour extraction signal Y2 calculated by the gain circuit 224. The This addition result is stored in the buffer memory 30.

  The median circuit 233 receives the Cb signal and Cr signal of the 12 × 12 pixel area from the matrix circuit 229, performs median processing using 9 points of 3 × 3 pixels included in the 5 × 5 pixel area, and performs 8 × The 8-pixel Cr signal and Cb signal are output.

  In the median processing of this embodiment, as shown in FIG. 13, 3 × 3 pixels (5 rows and 5 columns to 5 × 5 pixels) included in the 5 × 5 pixel region of the data D12 (data is a black dot) of 12 × 12 pixels. The median filter process is performed on nine data (x mark) of data D3-5 in (9 rows and 9 columns). That is, nine data are sorted in ascending or descending order, and the median value is used as median processing data. Then, the obtained median processing data is replaced with 7 × 7 data of 8 × 8 pixel output data D8. By repeating such an operation, output data D8 of 8 × 8 pixels is generated for each of the Cb and Cr signals. The output data D8 of the Cr signal and the Cb signal is stored in the buffer memory 30.

As described above, the JPEG compression circuit 33 applies the 8 × 8 pixel Y signal generated by the addition circuit 230 to the input data for each 20 × 20 pixel region input to the block processing circuit 200, and the median circuit 232. Based on the 8 × 8 pixel Cr signal and Cb signal generated by, the YCrCb signal formatted as 8 × 8 pixel of JPEG compression method is extracted as one unit, and it is repeatedly compressed by a well-known procedure Go and compress all images. The compressed image data is stored in the PC card 34 via the CPU 21.

  The operation of the electronic still camera configured as described above will be described. When the full-press switch 23 is operated, the quick return mirror jumps up and the shooting sequence program shown in FIG. 14 is started. In step S21, each pixel of the CCD 26 accumulates a light reception signal, and after the accumulation is completed, the accumulated charges of all the pixels are sequentially discharged. In step S 22, the discharged image data is processed by the analog signal processing circuit 27, converted into digital image data by the A / D conversion circuit 28, and input to the image processing circuit 29. In step S 23, white balance adjustment, γ gradation correction, JPEG formatting processing, and the like are performed in the image processing circuit 29. When the image processing ends, the process proceeds to step S24, and the image data after the image processing is temporarily stored in the buffer memory 30. In step S 25, image data is read from the buffer memory 30 and compressed by the JPEG compression circuit 33. In step S26, the compressed image data is stored in the PC card 34.

The effect of this embodiment will be described in further detail.
(1) The line processing circuit 100 shown in FIG. 3 takes charge of signal processing that can be performed in units of pixels and lines. That is, the line processing circuit 100 outputs data in a dot-sequential manner for each line along the data output from the CCD 26. Then, the data after the line processing is temporarily stored in the buffer memory 30, and the subsequent signal processing is performed in the block processing circuit 200 by nxm (n, m = 20, 16, 12, 8) pixels in one block unit. I tried to do it. Therefore, even in the case of an electronic still camera of a high image quality type exceeding 2 million pixels, the line buffer does not increase in size. That is, when signal processing is not performed in units of blocks as in this embodiment, as shown in FIG. 15, four lines are provided for each of the G interpolation processing, BPF processing, interpolation / LPF processing, and median processing circuit. It is clear that the buffer memories BM1 to BM4 are required, and the circuit scale increases. In addition, since the pipeline calculation performed in units of pixels and lines is not a process for each block but a line process, the pipeline calculation time can be increased as in the conventional case.

(2) RF gain and white balance for white balance fine adjustment as in the above formulas (1) and (2) based on an image that has been subjected to white balance using the white balance adjustment coefficient R gain and B gain determined in advance The fine adjustment BF gain is calculated, and the white balance fine adjustment is performed on the image data after the white balance by using the RF gain and the BF gain. Therefore, an adjustment failure of a predetermined white balance adjustment coefficient occurs. Even so, the occurrence of a color cast image is prevented.

(3) The interpolation / LPF circuit 228 interpolates the (B−G) signal and the (R−G) signal, and simultaneously performs a low-pass filtering process for extracting low frequency components. Processing time is shortened compared to a method of suppressing false colors and color moire by processing signals in the order of processing and LPF processing. In addition, the hardware can be omitted, and the total frequency response can be controlled in one place, so it is easy to control.

(4) Since media processing is performed on Cr image data and Cb image data of 8 × 8 pixels before compression by the JPEG method, false colors and color moire are suppressed only by low-pass filtering as in the past. Compared to the case, false color and color moire can be further suppressed in a shorter time. In addition, when generating 8 × 8 pixel Cr and Cb signals by JPEG compression format processing, 5 × 5 pixel region Cb signal and Cr signal for 12 × 12 pixel data subjected to interpolation / LPF processing and matrix processing. Since 9 data of 3 × 3 pixels are extracted for each pixel in both the horizontal direction and the vertical direction and median processing is performed, median processing is performed for all 25 data of 5 × 5 pixels. Compared with, median processing time can be shortened.

Although the electronic still camera has been described in the above embodiment, the line processing circuit 100 or the block processing circuit 200 is stored as an image processing program in a storage medium such as a CD-ROM or a floppy disk in the form of software , and the image is processed by a personal computer. It can also be used when processing. In this case, the image data captured by the CCD and digitized is stored in a large-capacity image data storage medium, and the storage medium is set in a personal computer to capture the image data. The line processing and block processing as described above are performed. For example, in FIG. 3, the output data of the black level circuit 105 can be stored in the PC card 34 as raw data, and the PC card 34 can be set in a personal computer for image processing of the raw data.

  As described above, when image processing is performed on a personal computer, if the image data stored in the image data storage medium has already been subjected to white balance adjustment, a program is executed so that only white balance fine adjustment processing is performed. create. On the other hand, when the image data stored in the image data storage medium has not been subjected to white balance adjustment, a program is created so as to perform white balance adjustment processing and white balance fine adjustment processing. In that case, not only the image data from the CCD but also the color temperature information of the subject detected by the white balance sensor 86 (35A) is stored together in the image data storage medium, and the white balance adjustment is performed based on the data. To do.

  The single-lens reflex electronic still camera has been described above. However, the present invention can also be applied to an electronic still camera in which lenses cannot be exchanged and a digital video camera capable of capturing moving images. Although the JPEG compression method has been described above, the present invention can be applied to other compression methods. Other compression methods include TIFF compression, fractal compression, MPEG compression, and the like. Note that the format process in this specification is not limited to the format process performed prior to the above-described various compression processes, and includes a non-compressed TIFF format process.

The circuit configuration in the above embodiment is merely an example, and includes, for example, the following aspects.
(1) In the G interpolation processing, BPF processing, LPF processing, and interpolation / LPF processing of the block processing circuit 200, image processing is performed with any block of 20 × 20, 16 × 16, 12 × 12, or 8 × 8 as one unit. Explained as what to do. However, in each processing, it is sufficient to perform image processing with 5 × 5 image data as one unit.
(2) When calculating the white balance fine adjustment gains RFgain and BFgain, the image data of the 512 × 512 region centered on the central portion of the focus detection region is extracted. Alternatively, data of a predetermined area at the center of the imaging area may be used, or if there are a plurality of focus detection areas, image data of the predetermined area of the selected focus detection area may be used. The white balance fine adjustment coefficient may be calculated based on the data of the area used as the photometric area.

The figure which shows the structure of one Embodiment of a single-lens reflex electronic still camera. Block diagram of an embodiment of a signal processing system of a single-lens reflex electronic still camera Block diagram for explaining a circuit for performing line processing in the signal processing system shown in FIG. Block diagram for explaining a circuit for performing block processing in the signal processing system shown in FIG. Diagram showing the arrangement of color filters The figure explaining the histogram of R, G, B The figure explaining the processing content of G interpolation circuit The figure explaining the processing contents of the band pass filter The figure explaining the processing contents of the low pass filter The figure explaining the processing content of a color difference signal generation circuit The figure which shows the example of data processed by an interpolation / LPF circuit The figure explaining the processing content of an interpolation / LPF circuit Diagram explaining processing contents of median circuit Flow chart showing a program that is activated by a full-press switch Block diagram when JPEG format processing is performed by line processing instead of block processing

Explanation of symbols

  21 ... CPU, 22 ... half-press switch, 23 ... full-press switch, 26 ... CCD, 29 ... image processing circuit, 33 ... JPEG compression circuit, 35 ... white balance detection processing circuit, 35A ... white balance sensor, 73 ... CCD, DESCRIPTION OF SYMBOLS 100 ... Line processing circuit, 104 ... White balance circuit, 107 ... Average value calculation / histogram calculation circuit, 200 ... Block processing circuit, 210 ... White balance fine adjustment circuit, 228 ... Interpolation / LPF circuit, 229 ... Matrix circuit, 232 ... Median circuit

Claims (7)

An imaging device that captures a subject image passing through a photographing lens and outputs image data;
A first image processing circuit that performs line-sequential preprocessing on N rows and M columns of image data output from the imaging device, and generates first image data;
A first storage device for temporarily storing the first image data for at least one frame;
A block of n rows and m columns (n is a positive integer satisfying N> n ≧ 3 and m is a positive integer satisfying M> m ≧ 3) is input from the first image data. On the other hand, by performing format processing including at least two stages of filter processing in which the block size is sequentially reduced in units of blocks without using the M column line buffer memory, (ni) rows (m- j) a second image processing circuit for generating second image data having a size of a column (i is a positive integer satisfying n> i ≧ 2 and j is a positive integer satisfying m> j ≧ 2); ,
A recording processing circuit for sequentially compressing and recording the second image data in the (n−i) rows (m−j) columns,
2. The digital camera according to claim 1, wherein the second image data in the (n−i) row (m−j) column has a size necessary for the compression recording process. The digital camera according to claim 1, wherein
The first image data includes color component data;
The second image processing circuit generates a luminance block of (n−i) rows (m−j) columns based on data of a block of common n rows and m columns read from the first image data. A digital camera comprising: luminance block processing; and chrominance block processing for generating a first chrominance block and a second chrominance block of (n−i) rows (m−j) columns. The digital camera according to claim 1 or 2,
A second storage device for temporarily storing the second image data;
The digital camera according to claim 1, wherein the recording processing circuit performs recording processing on the second image data stored in the second storage device . The digital camera according to claim 3, wherein
The digital camera, wherein the first storage device and the second storage device are the same storage device . The digital camera according to claim 1, wherein
(N−i1) rows (m−j1) columns (i1 is a positive integer satisfying i> i1 ≧ 1 and j1 is j> j1 ≧) extracted from the first image data of the block of n rows and m columns. A digital camera that performs median processing on image data of a positive integer satisfying 1 . The digital camera according to any one of claims 1 to 5,
The digital camera includes: an imaging unit that captures the subject image and outputs an analog image signal; and an A / D conversion circuit that converts the analog image signal into digital image data . The digital camera according to any one of claims 1 to 6,
The first image processing circuit includes white balance adjustment means for performing white balance adjustment on image data output from the imaging device,
A white balance fine adjustment coefficient calculation circuit for calculating a white balance fine adjustment coefficient based on the image data after white balance adjustment output from the white balance adjustment means;
2. The digital camera according to claim 1, wherein the second image processing circuit includes white balance fine adjustment means for performing white balance fine adjustment processing on the first image data using the white balance fine adjustment coefficient .

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