JP4685704B2 - Signal processing device - Google Patents

Description

  The present invention relates to a signal processing device that processes a signal such as an image signal or an audio signal, and more particularly to a configuration of a variable filter device that can control filter characteristics.

  Conventionally, in the field of image signal processing, for example, a two-dimensional filter (spatial filter) is used for improving the sharpness of an image and removing noise. A normal camera lens has a characteristic that the resolution in the vicinity of the optical axis of the lens is high, but the resolution in the portion corresponding to the peripheral portion of the screen far from the optical axis is low. As a method for suppressing image quality deterioration due to this characteristic, a method of switching filter characteristics between the screen center and the screen periphery is known.

  However, in a configuration in which a plurality of filter characteristics are mixed depending on the position of the screen, fixed pattern noise due to fluctuations in the DC gain of the filter occurs between different filter characteristics, and the image quality is degraded.

  For example, when filtering corresponding to the spatial position is performed on an image signal with little variation in DC gain, such as a wall of a building or the sky, the DC gain changes at the switching point of the filter characteristics, resulting in a level difference. Human vision is extremely sensitive to such DC gain fluctuations, and even detects fluctuations of 1% or less of the signal. Therefore, the fluctuation of the direct current gain becomes fixed pattern noise, causing image quality interference.

  As a factor of such DC gain fluctuation, the influence of the calculation error due to the accumulation of the rounding error to the number of effective digits of the filter coefficient is large. The occurrence of DC gain mismatch due to this rounding error will be described below.

For example, assume that each coefficient of a 7-tap transversal filter is given by 16 bits, and the following filter coefficients k0 to k6 are given.
k3 = + 49ACh
k2 = k4 = + 28BEh
k1 = k5 = + 0000h
k0 = k6 = −0D94h
The sum of the filter coefficients k0 to k6 is
k0 + k1 + k2 + k3 + k4 + k5 + k6 = 8000h
It becomes. 8000h is +1 in 16-bit representation and corresponds to the DC gain of this filter.

If the lower 6 bits of this coefficient are truncated and normalized to 10 bits,
k3 = + 126h
k2 = k4 = + 0A2h
k1 = k5 = + 000h
k0 = k6 = −037h
It becomes. The sum of all the coefficients of the filter coefficients k0 to k6 normalized to 10 bits is
k0 + k1 + k2 + k3 + k4 + k5 + k6 = 1FCh
It becomes. Since 1FCh is +508 in 10-bit representation, the DC gain of this filter is 508/512 = 0.99 times. Therefore, the DC gain of the filter is reduced by 1% from x1 to x0.99.

  Such fluctuations in DC gain can be eliminated if the calculation accuracy is improved. However, an attempt to increase the calculation accuracy increases the circuit scale. Until now, a method has been employed in which an increase in circuit scale is suppressed or a filter coefficient is corrected while allowing a DC gain error to some extent.

  Patent Document 1 discloses an example of a filter coefficient correction method. In Patent Document 1, a gain detection circuit that calculates a correction amount by calculating the sum of all filter coefficients is provided, and the DC gain fluctuation is suppressed by correcting the coefficient with the obtained correction amount.

FIG. 4 is a diagram showing the configuration of the variable filter device described in Patent Document 1. As shown in FIG. The coefficient generation circuit 12 generates a filter coefficient corresponding to the screen position. A signal representing this coefficient is branched into two systems, one being input to the gain detection circuit 13 and the other being input to the coefficient correction circuit 14. The gain detection circuit 13 calculates the sum of the input coefficient values and outputs a difference signal between the sum value and a predetermined value to the coefficient correction circuit 14. The coefficient correction circuit 14 corrects the filter coefficient using the input difference signal to make the DC gain of the coefficient variable filter 11 constant.
Japanese Patent Laid-Open No. 5-130452

  However, in the apparatus described in Patent Document 1, since the coefficients are corrected by the sum of the coefficients of all the taps, it is necessary to perform the calculation for obtaining the sum of the coefficients by the number of tap stages. Therefore, there is a problem that the circuit scale for correction becomes large.

  In addition, in the process of obtaining the sum of all coefficients, correction cannot be performed until the calculation of the sum of all coefficients is completed, so that there has been a problem that processing delay for correcting the coefficients is large. In particular, with the recent increase in the density of image pickup devices and the increase in the number of pixels, the number of taps constituting the filter increases, and the total calculation, coefficient correction calculation amount, and processing delay increase.

  In view of the above background, an object of the present invention is to provide a signal processing device capable of correcting a filter coefficient with a simple configuration and keeping a DC gain constant.

  A signal processing apparatus according to the present invention includes a filter coefficient generation unit that generates filter coefficients corresponding to spatial position information or time position information of image data, and coefficient normalization that normalizes the filter coefficients generated by the filter coefficient generation unit Unit, an error accumulating unit for accumulating rounding errors generated when normalizing the filter coefficient in the coefficient normalizing unit, and a normalizing unit in the coefficient normalizing unit based on the rounding error accumulated in the error accumulating unit. A coefficient correction unit that corrects the converted filter coefficient, and a filter processing unit that performs a filtering process on the image data using the coefficient corrected by the coefficient correction unit.

  With this configuration, the amount of calculation processing can be reduced by normalizing the filter coefficient, and the coefficient correction unit can control the filter coefficient based on the accumulated value of the rounding error, thereby suppressing fluctuations in DC gain.

  In the signal processing device according to the aspect of the invention, the filter processing unit may be variable by correcting the filter coefficient calculated by the coefficient normalization unit when a rounding error accumulated in the error accumulation unit exceeds a predetermined value. The DC gain of the filter is held constant.

  As described above, when the accumulated value of the rounding error exceeds a predetermined value, the DC gain of the filter processing unit can be made constant by correcting the filter coefficient.

  According to another aspect of the present invention, there is provided a signal processing apparatus including a lookup table in which a plurality of sets of filter coefficients are recorded, and a plurality of sets of filter coefficients recorded in the lookup table as spatial position information or time position of image data. And a coefficient control unit that controls the coefficient of the variable coefficient digital filter by switching according to the information, and the lookup table normalizes the filter coefficient generated corresponding to the spatial position information or time position information of the image data. In this configuration, rounding errors generated during normalization are accumulated, and filter coefficients obtained by correcting the filter coefficients based on the accumulated rounding errors are recorded.

  With this configuration, a plurality of sets of filter coefficients are recorded in the lookup table in advance, so that it is not necessary to perform filter coefficient correction calculation every time, and the DC gain of the variable filter can be made constant with a small amount of processing. .

  According to the present invention, it is possible to generate a filter coefficient capable of maintaining a constant DC gain with a simple configuration and to have an excellent effect of preventing occurrence of fixed pattern noise.

Hereinafter, a signal processing apparatus according to an embodiment of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a schematic block diagram of a signal processing apparatus according to the first embodiment of the present invention.
The signal processing apparatus according to the first embodiment of the present invention includes a coefficient variable filter 1 that performs filter processing on input data. In addition, the signal processing apparatus has a configuration for obtaining a filter coefficient used in the coefficient variable filter, a coefficient generation circuit 2 that generates a filter coefficient, and a coefficient normalization circuit that normalizes the filter coefficient and separates it into a normalization coefficient S2 and a rounding error S3. 5, an error accumulation circuit 3 for accumulating and accumulating the rounding error input from the coefficient normalization circuit 5, and a coefficient correction for correcting the coefficient when the error accumulated in the error accumulation circuit 3 exceeds a predetermined value And a circuit 4. The rounding error S3 separated by the coefficient normalization circuit 5 is an error that occurs when rounding to the number of significant digits after calculating the filter coefficient.

Next, the operation of the signal processing apparatus according to the present embodiment will be described.
The coefficient generation circuit 2 obtains screen position and lens information, and generates a filter coefficient S1 that can obtain a desired frequency characteristic corresponding to the screen position. The filter coefficient S1 generated by the coefficient generation circuit 2 is normalized by the coefficient normalization circuit 5. The coefficient normalization circuit 5 outputs the generated normalization coefficient S2 to the coefficient correction circuit 4, and outputs a rounding error S3 generated during normalization to the error accumulation circuit 3. The error accumulation circuit 3 outputs a carry signal S6 to the coefficient correction circuit 4 when the accumulated error exceeds a predetermined value. The coefficient correction circuit 4 corrects the filter coefficient based on the carry signal S <b> 6 input from the error accumulation circuit 3 and inputs the corrected filter coefficient to the coefficient variable filter 1. The coefficient variable filter 1 performs filtering processing on the input data using the filter coefficient input from the coefficient correction circuit 4.

  FIG. 2 is a diagram showing a time chart for explaining a specific operation of the signal processing apparatus according to the present embodiment. The coefficient generation circuit 2 generates a coefficient having a bit length sufficient to maintain calculation accuracy. A transversal digital filter requires a coefficient for each tap. The coefficient generation circuit 2 generates a coefficient set composed of a set of a plurality of coefficients. In updating the coefficient set composed of a plurality of coefficients, the error accumulating unit 3 is notified of the coefficient update by an update flag S4 indicating that the coefficient is being updated and a coefficient update pulse S5 indicating the end of updating of one coefficient.

Hereinafter, the coefficient generation circuit 2 will be described using an example in which each coefficient of the following 7-tap transversal filter is generated with 16 bits.
k3 = + 49ACh
k2 = k4 = + 28BEh
k1 = k5 = + 0000h
k0 = k6 = −0D94h

  The coefficient normalization circuit 5 performs normalization by truncating the lower 6 bits and generating a 10-bit coefficient. The coefficient normalization circuit 5 separates the upper 10-bit normalization coefficient into the coefficient correction circuit 4 and the lower 6-bit rounding error into the error accumulation circuit 3.

As a result of the above operation, the normalized coefficient normalized to 10 bits is
k3 = + 126h
k2 = k4 = + 0A2h
k1 = k5 = + 000h
k0 = k6 = −037h
The rounding error is
k3 = 2Ch
k2 = k4 = 3Eh
k1 = k5 = 00h
k0 = k6 = 2Ch
It becomes.

The error accumulation circuit 3 is cleared to 0 except when the coefficient is being updated by the update flag S4. When the coefficient update is started, the error accumulation circuit 3 performs cumulative addition of the coefficient rounding error every time the coefficient is updated. The following table shows the rounding error accumulation process taking the above-described coefficients k0 to k6 as an example.

  Here, when the result of accumulating the errors exceeds a predetermined amount (in this case, 40 h), a carry signal S6 that causes a carry to the coefficient correction circuit 4 is output. After the error accumulation circuit 3 outputs the carry signal S6, the error accumulation circuit 3 performs addition with the next coefficient using the lower 6 bits of the cumulative addition result as the cumulative addition value. The lower 6 bits correspond to the accumulated result −40h. The error accumulating circuit 3 performs the same process for all coefficients.

  Based on the carry signal S6 input from the error accumulation circuit 3, the coefficient correction circuit 4 performs correction by adding +1 to the coefficient value at that time when a carry occurs.

  In the example shown in FIG. 2, the second coefficient is 1C9h + 1 = 1CAh, and similarly, the coefficient corrected by +1 to the fifth, sixth, and seventh coefficients is sent to the coefficient variable filter 1 to perform filter calculation.

Here, the DC gain with the corrected coefficient will be described.
k0 = −037h
k1 = + 000h
k2 = + 0A3h
k3 = + 127h
k4 = + 0A3h
k5 = + 000h
k6 = −036h
Therefore, the sum of all coefficients is k0 + k1 + k2 + k3 + k4 + k5 + k6 = 200h. The sum 200h of all coefficients becomes +1 in 10-bit expression, and it can be seen that the DC gain is corrected from x0.99 times to x1 times when correction is not performed, and a desired gain is obtained.

  In this embodiment, the filter coefficient is normalized by truncation. However, the filter coefficient can be normalized by other methods. For example, when normalization is performed by rounding off a binary number, which is equivalent to rounding off a decimal number, the error accumulating circuit generates a carry signal and a borrow signal at both the carry and carry thresholds, respectively. The correction by the coefficient correction circuit performs both +1 and -1. Similarly, it goes without saying that normalization by rounding up is also possible.

  In this embodiment, the coefficient is corrected from the peripheral tap to the center tap of the transversal filter in order to correct the gain fluctuation. This is because weighting generally increases from the periphery toward the center tap, and the influence on the filter characteristics can be reduced.

  When the filter coefficient is corrected in this way, the filter coefficient differs slightly from the value generated by the coefficient generation circuit 2, and the frequency characteristic of the filter slightly varies. However, the sensitivity to a change in resolution is lower than that to a gain change, and a slight change in resolution is not detected. Therefore, only the gain fluctuation suppression effect can be obtained in the corrected image.

  Although the present embodiment has been described mainly with respect to the case where there is a spatial gain fluctuation, even if the gain fluctuates for each field or frame, it is detected as flicker, which also disturbs the image quality. According to the variable filter system for performing gain correction according to the present invention, it is possible to correct gain fluctuations with time, and to prevent image quality interference due to flicker or the like.

(Second Embodiment)
FIG. 3 is a schematic block diagram of a signal processing apparatus according to the second embodiment of the present invention.
The signal processing apparatus according to the second embodiment includes a coefficient generation circuit 2 that generates a filter coefficient, a coefficient normalization circuit 5 that normalizes the filter coefficient and separates it into a normalization coefficient and a rounding error, and an effective digit after calculating the filter coefficient. An error accumulating circuit 3 that accumulates and accumulates errors generated when rounding to a number, a coefficient correcting circuit 4 that corrects a coefficient when the accumulated accumulated error exceeds a predetermined value, and a plurality of coefficient sets are tabulated. The coefficient storage device 6 is provided.

  The coefficient storage device 6 stores a plurality of filter coefficient sets corresponding to the screen position and lens information as a look-up table. The filter coefficients stored in the lookup table are the signals of the first embodiment using the coefficient generation circuit 2, the coefficient normalization circuit 5, the error accumulation circuit 3, and the coefficient correction circuit 4 according to the position of the screen. The filter coefficient is obtained in the same manner as the processing device. In the calculation process at the time of creating the lookup table, as described above, the rounding error of the filter coefficient is cumulatively added, and the coefficient is corrected by the comparison result with the predetermined value to create the table.

  The signal processing apparatus according to the second embodiment selects an optimum coefficient set corresponding to the screen position and lens information from a plurality of coefficient sets stored in the coefficient storage device 6, switches the filter characteristics, and performs image processing. Do.

  The signal processing apparatus according to the second embodiment can fix the DC gain to a constant value by a simple configuration using the filter coefficient of the lookup table stored in the coefficient storage device 6.

  In the present embodiment, the coefficient storage device 6 that holds the filter coefficients is arranged in the subsequent stage of the coefficient correction circuit 4, and the coefficients are switched in the coefficient storage device 6 after the processing from the coefficient normalization circuit 2 to the coefficient correction circuit 4. The position where the coefficient storage device 6 is arranged is not limited to the subsequent stage of the coefficient correction circuit 4. For example, the coefficient storage device 6 may be disposed between the coefficient generation circuit 2 and the coefficient normalization circuit 5.

  In addition, when the number of input pixels or the number of output pixels from the image sensor is changed, or in response to other image data processing, it is also possible to further correct the corrected coefficients stored in advance. is there.

  In the present embodiment, the method of setting the filter gain to a constant value has been described using the contour compensation circuit of the television camera as an example. In addition to the contour compensation circuit, the present invention depends on time and space, such as a geometric transformation filter (affine transformation filter) that performs distortion correction according to the screen position, and an adaptive automatic equalizer used in magnetic recording. This can be applied to a shift variant filter whose characteristics are variable. In the above-described embodiment, the hardware configuration is described. However, the present invention is not limited to hardware, and can be configured by software.

  The present invention has an excellent effect of preventing generation of fixed pattern noise with a simple configuration, and is a signal processing device for processing a signal such as an image signal or an audio signal, in particular, a variable filter device capable of controlling filter characteristics. Useful as such.

1 is a schematic block diagram of a signal processing device according to a first embodiment of the present invention. Time chart for explaining the operation of the signal processing apparatus according to the first embodiment of the present invention Schematic block diagram of a signal processing device according to a second embodiment of the present invention Schematic block diagram of a conventional variable filter device

Explanation of symbols

1 coefficient variable filter 2 coefficient generation circuit 3 error accumulation circuit 4 coefficient correction circuit 5 coefficient normalization circuit 6 coefficient storage device S1 filter coefficient S2 normalization coefficient S3 rounding error S4 update flag S5 coefficient update pulse S6 carry 11 filter 12 coefficient generation circuit 13 Gain detection circuit 14 Coefficient correction circuit

Claims (3)

A filter coefficient generation unit that generates a filter coefficient corresponding to the spatial position information or temporal position information of the image data;
A coefficient normalization unit that normalizes the filter coefficient generated by the filter coefficient generation unit;
An error accumulating unit for accumulating rounding errors generated when normalizing filter coefficients in the coefficient normalizing unit;
A coefficient correction unit that corrects the filter coefficient normalized by the coefficient normalization unit based on the rounding error accumulated in the error accumulation unit;
A filter processing unit that performs a filtering process on the image data using the coefficient corrected by the coefficient correction unit;
A signal processing apparatus comprising:   The filter processing unit maintains the DC gain of the variable filter constant by correcting the filter coefficient calculated by the coefficient normalization unit when the rounding error accumulated in the error accumulation unit exceeds a predetermined value. The signal processing apparatus according to claim 1, wherein: A lookup table that records multiple sets of filter coefficients;
A coefficient control unit that controls a coefficient of the variable coefficient digital filter by switching a plurality of sets of filter coefficients recorded in the lookup table according to the spatial position information or the time position information of the image data;
With
The look-up table normalizes filter coefficients generated corresponding to the spatial position information or temporal position information of the image data, accumulates rounding errors generated when normalizing, and based on the accumulated rounding errors, the filter A signal processing apparatus, wherein filter coefficients obtained by correcting the coefficients are recorded.

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