JP4675863B2 - Programmable logic circuit - Google Patents

Description

  The present invention relates to a programmable logic circuit composed of spin transistors.

  In recent years, research and development of spin electronics devices using the spin degree of freedom of electrons has been active. Applied research based on the tunneling magneto-resistive (TMR) effect, such as magnetic random access memory (MRAM), read heads of magnetic recording devices, spin transistors, etc. More.

  Here, the spin transistor has a magnetic recording layer made of a magnetic material, and has attracted attention as a next-generation technology that can reconfigure a logic circuit in accordance with data (spin direction) stored in the magnetic recording layer. .

  Typical examples of spin transistor structures include diffusion type spin transistors (Mark Johnson type), spin orbit control type spin transistors (Supriyo Datta type), spin valve transistors, single electron spin transistors, and resonant spin transistors. ing.

  In addition, a MOS-structure spin transistor is known in which the source / drain is made of a magnetic material and a point contact is provided between the channel and the drain (see Patent Document 1).

  This spin transistor controls the magnetization of a magnetic material using spin torque generated by spin-polarized electrons. The point contact has a size that causes a quantum effect on spin-polarized electrons, and its resistance is significantly larger than the channel resistance.

  Since the interface resistance between the channel and the drain is the main factor that determines the magnetization dependence of the drain current, this spin transistor results in a large magnetoresistance ratio (MR ratio: Magneto-resistance ratio). ) Can be obtained.

  The programmable logic circuit is constituted by a combination of such spin transistors. First, basic logic circuits such as an AND gate circuit and an OR gate circuit are formed by spin transistors. Thereafter, the magnetization of the magnetic material of the spin transistor is controlled, and the contents of the logic circuit are changed or the logic circuit is enabled / disabled.

  The greatest feature of the programmable logic circuit is that a plurality of logics can be selectively realized by one hardware. Therefore, when it is desired to change the logic, it is only necessary to reconfigure the logic circuit by changing the magnetization of the magnetic material of the spin transistor, and redesign of the logic circuit is unnecessary.

However, there is a problem with such a programmable logic circuit.
One problem is that when the logic circuit is reconfigured, the magnetization of the magnetic material of the spin transistor must be controlled one by one, and the wiring for that is complicated.

  Spin transistors that control the magnetization of a magnetic material by utilizing spin torque generated by spin-polarized electrons can reduce the spin injection current that causes spin-polarized electrons as the size of the magnetic material decreases. Is excellent. However, a separate wiring is required only to cause a spin injection current to flow through the magnetic material and reverse the magnetization of the magnetic material, resulting in complicated wiring and increased circuit area.

  Specifically, a signal path for forcibly turning on the spin transistor when reconfiguring the logic circuit is required separately from the normal signal path. For this purpose, for example, one switch element must be connected to the input terminal of each spin transistor.

  Another problem is that when a desired logic cannot be obtained, it is difficult to specify a defective portion, and it takes a lot of time and labor to reconfigure the logic circuit.

It is not an easy task to identify a faulty hardware transistor, for example, one defective spin transistor among a large number of spin transistors. In addition, if the desired logic cannot be obtained, whether it is due to a design error, a hardware defect, or both, it takes a lot of time and effort to analyze the cause. Cost.
JP 2003-92412 A

  In an example of the present invention, a programmable logic circuit is proposed in which wiring for reconfiguring a logic circuit is simple and the logic circuit can be easily reconfigured.

    (1) A programmable logic circuit according to an example of the present invention includes a magnetic pinned layer connected between a first power supply node and an output node and having a fixed magnetization direction and a magnetic recording layer having a changed magnetization direction. A first transistor whose conductance changes in accordance with the relative relationship between the magnetization direction of the magnetic pinned layer and the magnetization direction of the magnetic recording layer; and a first transistor connected between the second power supply node and the output node. A second transistor whose conductance is set to a value between the maximum value and the minimum value of the conductance, and a third transistor and a resistance element connected in series between the third power supply node and the output node. A first transistor of a first conductivity type formed when the transistor is turned on; a first gate electrode in a floating state disposed on the first channel; A second gate electrode disposed on the gate electrode, and the second transistor is disposed on the second channel of the second conductivity type formed when the transistor is turned on, and on the second channel. A floating third gate electrode connected to the first gate electrode, a fourth gate electrode disposed on the third gate electrode, and a second and fourth gate A circuit for applying an input signal to the electrode and causing a spin injection current to flow between the first and third power supply nodes and a detection unit for detecting an output signal output to the output node are provided.

    (2) The programmable logic circuit according to the present invention is composed of a combination of a plurality of basic units, and each basic unit is connected between the first power supply node and the output node, and the magnetization direction is fixed. A first transistor having a pinned layer and a magnetic recording layer whose magnetization direction changes, wherein a conductance changes according to a relative relationship between the magnetization direction of the magnetic pinned layer and the magnetization direction of the magnetic recording layer; and a second power supply node Between the third power supply node and the output node, the second transistor having a conductance set to a value between the maximum value and the minimum value of the conductance of the first transistor. A first transistor of the first conductivity type formed when the transistor is turned on, and a first channel. The first transistor includes a first gate electrode in a floating state disposed above and a second gate electrode disposed above the first gate electrode, and the second transistor has a second conductivity formed when turned on. A second channel of the mold, a floating third gate electrode disposed on the second channel and connected to the first gate electrode, and a fourth disposed on the third gate electrode And a circuit for passing a spin injection current between the first and third power supply nodes for the plurality of basic units, the magnetization direction of the magnetic pinned layer, and the magnetization direction of the magnetic recording layer And a circuit for reconfiguring the logic.

    (3) In the programmable logic circuit reconfiguration method according to the example of the present invention, in the programmable logic circuit of (1) or (2), the logic value of the input signal to the programmable logic circuit is determined, and the input signal is applied. Thus, after passing a spin injection current between the first and third power supply nodes for the plurality of basic units, the logic value of the output signal of the programmable logic circuit is verified. Furthermore, when the logic value of the output signal is not accurate, the conditions regarding the spin injection current are changed, and the logic value of the output signal is verified again. When the logic value of the output signal is accurate, the input signal The logic value is changed, the logic value of the output signal is verified again, and the logic reconfiguration is completed when the logic value of the output signal is verified for all combinations of the logic values of the input signal.

  According to the example of the present invention, it is possible to realize a programmable logic circuit in which wiring for reconfiguring the logic circuit is simple and the logic circuit can be easily reconfigured.

  The best mode for carrying out an example of the present invention will be described below in detail with reference to the drawings.

1. Overview
In the programmable logic circuit according to the example of the present invention, after applying a spin injection current to the spin transistor with the input signal applied, the output signal is verified to determine whether the logic reconfiguration is completed. To do.

  In this way, the switching element connected to the input terminal of the spin transistor conventionally required for writing by simultaneously performing writing (reconfiguration of logic) by spin injection current and verification of the reconfigured logic. Can be omitted, and the wiring can be simplified and the reconfiguration time can be shortened (simplified).

  In the programmable logic circuit according to the example of the present invention, the logic is reconfigured by combining a plurality of basic units and causing a spin injection current to flow simultaneously through the spin transistors in the plurality of basic units.

  In this way, by simultaneously reconfiguring the logic for a plurality of basic units, the switch element connected to the input terminal of the spin transistor, which was conventionally necessary for writing, can be omitted, and the wiring can be simplified. And shortening (simplification) of reconfiguration.

  In the method for reconfiguring a programmable logic circuit according to the example of the present invention, a logic value of an input signal is determined, and after applying a spin injection current to spin transistors in a plurality of basic units in a state where the input signal is applied, the programmable logic circuit is programmable. The logic value of the output signal of the logic circuit is verified.

  As a result, the necessary logic can be obtained without the detailed design of the logic circuit, and the design effort and time can be greatly reduced. In addition, even if a part of the hardware is defective, the logic circuit can be reconfigured so as not to be affected by the defect, so there is no need to identify the defective part, and time and effort required to identify the defective part. Can be eliminated.

  According to the programmable logic circuit and the reconfiguration method as described above, the switch element that has been conventionally required only for writing can be omitted, so that the circuit area as a whole of the programmable logic circuit is reduced, and the logic circuit is increased in height. It can also contribute to integration.

  Further, by selecting a basic unit using a write signal, logic can be reconfigured in units of basic units. As a result, the number of types of logic circuits that can be realized by a single piece of hardware is increased compared to the conventional logic reconfiguration by the programmable logic circuit, and the design effort of the logic circuit can be further reduced.

2. Embodiment
Several embodiments that are considered best are described.

(1) First embodiment
A. Circuit
FIG. 1 shows a basic unit of a programmable logic circuit according to the first embodiment.

  This programmable logic circuit includes three transistors SP, SN, and T1 and one resistance element R1.

  Transistors SP and SN are connected in series between power supply terminals (power supply nodes) N1 and N2. Different potentials V1 and V2 are applied to the power supply terminals N1 and N2. For example, the potential V1 applied to the power supply terminal N1 is one of the power supply potential Vdd and the ground potential Vss, and the potential V2 applied to the power supply terminal N2 is the other of the power supply potential Vdd and the ground potential Vss. It is one of.

  The transistor SP is a spin transistor, and includes a magnetic pinned layer whose magnetization direction is fixed and a magnetic recording layer whose magnetization direction changes. The conductance of the transistor SP changes according to the relative relationship between the magnetization direction of the magnetic pinned layer and the magnetization direction of the magnetic recording layer.

  The transistor SP is a P-channel MISFET in which a P-type channel is formed when turned on. Accordingly, the transistor SP is formed in the N-type semiconductor region. A floating first gate electrode (floating gate electrode) is disposed above the channel of the transistor SP, and a second gate electrode is disposed above the first gate electrode.

  The transistor SN is an N-channel MISFET in which an N-type channel is formed when turned on. Therefore, the transistor SN is formed in the P-type semiconductor region. The conductance of the transistor SN is set to a value between the maximum value and the minimum value of the conductance of the transistor SP.

  For example, when the magnetization state of the transistor SP, that is, the relative relationship between the magnetization direction of the magnetic pinned layer and the magnetization direction of the magnetic recording layer, the conductance Gm in the parallel state is 100 (maximum value), When the conductance Gm is 1 (minimum value), the conductance Gm of the transistor SN is set to 10.

  A floating third gate electrode (floating gate electrode) connected to the first gate electrode is disposed above the channel of the transistor SN, and a fourth gate electrode is disposed above the third gate electrode. Is placed.

  Therefore, an input signal (logical value “0” or “1”) input to the second gate electrode of the transistor SP is A, and an input signal (logical value “0”) input to the fourth gate electrode of the transistor SN. “Or“ 1 ”) is B, the potential Vfg of the first and third gate electrodes in the floating state can be expressed by (A + B) / 2.

  The transistor T1 and the resistance element R1 are connected in series between a power supply terminal (power supply node) N3 and an output node O1. A potential V2 is applied to the power supply terminal N3. The output node O1 is a connection point between the two transistors SP and SN, and the output signal Y (= Vout) is output from the output node O1.

  The transistor T1 is an N-channel MISFET in which an N-type channel is formed when turned on. However, instead of this, a P-channel MISFET in which a P-type channel is formed at the time of ON may be used as the transistor T1. A write signal W serving as a control signal when performing logic reconfiguration is input to the gate electrode of the transistor T1.

  2 and 3 is a modification of the programmable logic circuit of FIG.

  In both FIG. 2 and FIG. 3, the transistor SN is composed of a spin transistor. The other points are the same as in FIG.

  The transistor SN includes a magnetic pinned layer whose magnetization direction is fixed and a magnetic recording layer whose magnetization direction changes.

  In FIG. 2, the magnetization state of the transistor SN, that is, the relative relationship between the magnetization direction of the magnetic pinned layer and the magnetization direction of the magnetic recording layer is fixed to a parallel state (conductance Gm = 10). The magnetization state is fixed to the anti-parallel state (conductance Gm = 10).

  The programmable logic circuit shown in FIGS. 1 to 3 is set so as to constitute specific logic that becomes an output signal (logic value) Y with respect to input signals (logic values) A and B in an initial state.

  When reconfiguring such a programmable logic circuit, input signals A and B are applied to transistors SP and SN, potentials V1 and V2 are applied to power supply terminals N1, N2 and N3, and write signal W is set to “H”. "

  Thereafter, a spin injection current is passed between the power supply terminals N1 and N3, and then the output signal Y with respect to the input signals A and B is verified.

  When the magnetization state of the magnetic recording layer of the transistor SP is not changed by the spin injection current, the output signal Y with respect to the input signals A and B remains in the initial state, so that it is determined that the logic reconfiguration is incomplete.

  Further, after changing the conditions regarding the spin injection current, the spin injection current is again passed between the power supply terminals N1 and N3, and after the spin injection current is passed, the output signal Y with respect to the input signals A and B is verified.

  When the magnetization state of the magnetic recording layer of the transistor SP is changed by the spin injection current, a desired output signal Y is obtained for the input signals A and B, and therefore it is determined that the logic reconfiguration is completed.

B. Device structure example 1
An example of the device structure of the programmable logic circuit according to the first embodiment will be described. Here, the structure in the case where FIG. 2 is made into a device among the programmable logic circuits of FIGS. 1 to 3 is taken as an example.

  4 shows a plan view of the device structure, and FIG. 5 shows a cross-sectional view taken along the line VV of FIG.

  The feature of this device is that, firstly, the two transistors SP and SN are both MOS type spin transistors, and secondly, the source and drain of the transistors SP and SN are formed by a ferromagnetic material. The drains of the transistors SP and SN are shared. Third, the transistors SP and SN have a stack gate structure and the floating gate electrodes are connected to each other.

  For example, an element isolation insulating layer 17 having an STI structure is formed in the semiconductor substrate 10. In the element region surrounded by the element isolation insulating layer 17, an N-type well region 10a and a P-type well region 10b are formed.

  In a recess provided at the boundary between the N-type well region 10a and the P-type well region 10b, a ferromagnetic body 12a is formed as a pinned layer having a fixed magnetization direction. In this example, the magnetization direction of the ferromagnetic body 12a is fixed to the right with respect to the paper surface. The ferromagnetic body 12a is shared as the drains of the transistors SP and SN.

  An antiferromagnetic material 13 as a pin layer is formed on the ferromagnetic material 12a. A tunnel barrier layer 11a is formed between the N-type well region 10a and the ferromagnetic body 12a and between the P-type well region 10b and the ferromagnetic body 12a.

  In the recess provided in the N-type well region 10a, a ferromagnetic body 12b is formed as a free layer whose magnetization direction changes. In this example, the magnetization direction of the residual magnetization of the ferromagnetic body 12b is rightward or leftward with respect to the paper surface. The ferromagnetic body 12b becomes a source of the transistor SP.

  A tunnel barrier layer 11b is formed between the N-type well region 10a and the ferromagnetic body 12b.

  A ferromagnetic body 12b 'serving as a pinned layer whose magnetization direction is fixed is formed in the recess provided in the P-type well region 10b. In this example, the magnetization direction of the ferromagnetic body 12b 'is fixed to the right with respect to the paper surface. The ferromagnetic body 12b 'serves as the source of the transistor SN.

  An antiferromagnetic material 13 as a pinned layer is formed on the ferromagnetic material 12b '. A tunnel barrier layer 11b is formed between the P-type well region 10b and the ferromagnetic body 12b '.

  A floating gate electrode FG is formed on the channel between the ferromagnetic bodies 12a and 12b via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode is formed via an insulating layer (IPD: inter-polysilicon dielectric) made of ONO (oxide / nitride / oxide). An input signal A is input to the gate electrode.

  A floating gate electrode FG is formed on the channel between the ferromagnetic bodies 12a and 12b 'via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode to which the input signal B is input is formed via an insulating layer made of ONO.

  The ferromagnetic body 12b as the source of the transistor SP is connected to the power supply terminal N1 to which the power supply potential V1 is applied. The ferromagnetic body 12b 'as the source of the transistor SN is connected to the power supply terminal N2 to which the power supply potential V2 is applied.

  The ferromagnetic body 12a as the drains of the transistors SP and SN is connected to the output node O1. Between the output node O1 and the power supply terminal N3, a transistor T1 and a resistance element R1 whose on / off is controlled by a write signal W are connected. A power supply potential V2 is applied to the power supply terminal N3.

  For the transistors SP and SN, one or both of the tunnel barrier layers 11a and 11b may be omitted.

  The potential of the power supply terminal N3 is the same as the potential V2 of the power supply terminal N2, but may be set to other potentials.

C. Reconfiguration example 1
An example of logic reconfiguration for the programmable logic circuit having the structure of FIGS. 4 and 5 will be described.

  In the initial state, the magnetization state of the transistor SP is set to an anti-parallel state. That is, the magnetization direction of the residual magnetization of the ferromagnetic body 12b is set to the left with respect to the paper surface. In this case, as shown in FIG. 2, the ratio of the conductance Gm of the transistors SP and SN is 1:10.

Accordingly, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 1.

  That is, the logic of the programmable logic circuit in the initial state is NOR, and the equivalent circuit of the device of FIGS. 4 and 5 is a symbol of a NOR gate as shown in FIG.

  If the devices of FIGS. 4 and 5 are used as NOR gates, it is not necessary to reconfigure the logic, so the write signal W remains “L”.

  4 and 5 is used as a NAND gate, the write signal W is set to “H” and the logic is reconfigured as follows.

  When the power supply potentials V1 (= Vdd), V2 (= Vss), and V2 (= Vss) are applied to the power supply terminals N1, N2, and N3, respectively, with the write signal W set to “H”, the spin injection current (current pulse) ) Flows from the ferromagnetic body 12b as the free layer toward the ferromagnetic body 12a as the pinned layer, as shown in FIG.

  At this time, the ferromagnet 12a acts as a spin filter that passes only the electrons spin-polarized to the right with respect to the paper surface. The spin-polarized electrons are contained in the ferromagnet 12b as a free layer. Gives electrons spin torque. For this reason, the magnetization direction of the ferromagnet 12b changes from leftward to the paper surface (anti-parallel state) to rightward to the paper surface (parallel state).

  Then, as shown in FIG. 2, the ratio of the conductance Gm of the transistors SP and SN is 100: 10.

Accordingly, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 2.

  That is, the logic of the programmable logic circuit is NAND, and the equivalent circuit of the device of FIGS. 4 and 5 is a symbol of a NAND gate as shown in FIG.

  In this manner, the logic of the programmable logic circuit can be reconfigured from the NOR gate to the NAND gate by the write signal W.

Here, it is necessary to verify whether or not the logic reconfiguration has been completed.
In this example, writing (logic reconfiguration) and logic verification are performed simultaneously.

  In the state where power supply potentials V1, V2, V2 are applied to the power supply terminals N1, N2, N3, the write signal W is set to “H”, and the input signals (logic values) A, B are applied, a spin injection current (current pulse) is applied. When flowing, an output signal Y (= Vout) corresponding to the reconfigured logic can be obtained.

  Therefore, the logic can be verified by checking the logic value of the output signal Y.

  For example, when the relationship between the input signals A and B and the output signal Y is as shown in Table 1, the output signal Y has the relationship shown in Table 2 for all four combinations of the input signals A and B. If not, it can be determined that the reconfiguration has not been completed.

  Further, for all four combinations of the input signals A and B, when the output signal Y has the relationship shown in Table 2, it can be determined that the reconstruction has been completed.

  When there is a request to return to the initial logic (reset operation) after completing the reconfiguration, a circuit for changing the direction of the spin injection current flowing in the transistor SP may be provided separately. .

  However, since such a reset function causes the circuit to be complicated, it is preferable to determine whether or not the reset function can be adopted according to the user's request.

D. Device structure example 2
Next, an example of the device structure of the programmable logic circuit according to the first embodiment will be described. Here, of the programmable logic circuits shown in FIGS. 1 to 3, the structure of FIG. 1 as a device is taken as an example.

  7 shows a plan view of the device structure, and FIG. 8 shows a cross-sectional view taken along line VIII-VIII in FIG.

  For example, an element isolation insulating layer 17 having an STI structure is formed in the semiconductor substrate 10. In the element region surrounded by the element isolation insulating layer 17, an N-type well region 10a and a P-type well region 10b are formed.

  A ferromagnetic body 12a as a pinned layer having a fixed magnetization direction is formed in one of the two recesses provided in the N-type well region 10a, and the magnetization direction is formed in the other one. A ferromagnetic body 12b is formed as a changing free layer.

  In this example, the magnetization direction of the ferromagnetic body 12a is fixed to the right with respect to the paper surface, and the magnetization direction of the residual magnetization of the ferromagnetic body 12b is rightward or leftward with respect to the paper surface.

  An antiferromagnetic material 13 as a pinned layer is formed on the ferromagnetic material 12a. Tunnel barrier layers 11a and 11b are formed between the N-type well region 10a and the ferromagnetic bodies 12a and 12b.

  The ferromagnetic body 12a becomes the source of the transistor SP, and the ferromagnetic body 12b becomes the drain of the transistor SP.

  An N-type source region 12c and an N-type drain region 12d are formed in the P-type well region 10b.

  A floating gate electrode FG is formed on the channel between the ferromagnetic bodies 12a and 12b via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode is formed via an insulating layer made of ONO. An input signal A is input to the gate electrode.

  A floating gate electrode FG is formed on the channel between the source / drain regions 12c and 12d via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode to which the input signal B is input is formed via an insulating layer made of ONO.

  The ferromagnetic body 12a as the source of the transistor SP is connected to the power supply terminal N1 to which the power supply potential V1 is applied. The source region 12c of the transistor SN is connected to the power supply terminal N2 to which the power supply potential V2 is applied.

  The ferromagnetic body 12b as the drain of the transistor SP and the drain region 12d of the transistor SN are each connected to the output node O1. Between the output node O1 and the power supply terminal N3, a transistor T1 and a resistance element R1 whose on / off is controlled by a write signal W are connected. A power supply potential V2 is applied to the power supply terminal N3.

  Note that one or both of the tunnel barrier layers 11a and 11b may be omitted for the transistor SP.

  The potential of the power supply terminal N3 is the same as the potential V2 of the power supply terminal N2, but may be set to other potentials.

E. Reconfiguration example 2
An example of logic reconfiguration for the programmable logic circuit having the structure of FIGS. 7 and 8 will be described.

  In the initial state, the magnetization state of the transistor SP is set to a parallel state. That is, the magnetization direction of the residual magnetization of the ferromagnetic body 12b is set to the right with respect to the paper surface. In this case, as shown in FIG. 1, the ratio of the conductance Gm of the transistors SP and SN is 100: 10.

  Accordingly, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 2.

  That is, the logic of the programmable logic circuit in the initial state is NAND, and the equivalent circuits of the devices in FIGS. 7 and 8 are NAND gate symbols as shown in FIG.

  If the devices of FIGS. 7 and 8 are used as NAND gates, it is not necessary to reconfigure the logic, so the write signal W remains “L”.

  If the devices of FIGS. 7 and 8 are used as NOR gates, the write signal W is set to “H” and the logic is reconfigured as follows.

  When the power supply potentials V1 (= Vdd), V2 (= Vss), and V2 (= Vss) are applied to the power supply terminals N1, N2, and N3, respectively, while the write signal W is set to “H”, the spin injection current (current pulse) ) Flows from the ferromagnetic body 12a as the pinned layer toward the ferromagnetic body 12b as the free layer, as shown in FIG.

  At this time, the ferromagnet 12a acts as a spin reflection layer that reflects electrons polarized leftward with respect to the paper surface, and the spin-polarized electrons are electrons in the ferromagnet 12b as a free layer. Is given a spin torque. For this reason, the magnetization direction of the ferromagnetic body 12b changes from the right direction (parallel state) with respect to the paper surface to the left direction (antiparallel state) with respect to the paper surface.

  Then, as shown in FIG. 1, the ratio of the conductance Gm of the transistors SP and SN is 1:10.

  Accordingly, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 1.

  That is, the logic of the programmable logic circuit is NOR, and the equivalent circuit of the device of FIGS. 7 and 8 is a symbol of a NOR gate as shown in FIG.

  In this manner, the logic of the programmable logic circuit can be reconfigured from the NAND gate to the NOR gate by the write signal W.

  Here, as in the reconfiguration example 1, the logic verification can be performed at the same time as the writing (logic reconfiguration).

F. Principle of reconstruction
The principle of reconfiguration of the programmable logic circuit of FIGS. 1 to 3 will be described.

  FIG. 10 shows the relationship between the floating gate potential Vfg and the output signal Y (= Vout).

  The floating gate electrodes of the transistors SP and SN are common. Therefore, the floating gate potential Vfg is an average value of the input signals A and B.

  For example, when the input signals A and B are both “1 (= Vdd)”, the floating gate potential Vfg is also “1”. When both the input signals A and B are “0 (= Vss)”, the floating gate potential Vfg is also “0”.

  When one of the input signals A and B is “1 (= Vdd)” and the other is “0 (= Vss)”, the floating gate potential Vfg is “½ (= (Vdd + Vss) / 2)”. .

  Here, when the value of the conductance Gm of the transistor SN is set to a value between the maximum value and the minimum value of the conductance Gm of the transistor SP, the floating gate potential Vfg is “1” according to the value of the conductance Gm of the transistor SP. The output signal Y (= Vout) at the time of / 2 "changes.

  This is the principle of reconfiguration of the programmable logic circuit.

G. Summary
As described above, according to the first embodiment, it is possible to realize a programmable logic circuit in which wiring for reconfiguring a logic circuit is simple and the logic circuit can be easily reconfigured in a short time. .

(2) Second embodiment
A. Circuit
FIG. 11 shows a basic unit of a programmable logic circuit according to the second embodiment.

  This programmable logic circuit includes three transistors SP, SN, and T1 and one resistance element R1.

  Transistors SP and SN are connected in series between power supply terminals (power supply nodes) N1 and N2. Different potentials V1 and V2 are applied to the power supply terminals N1 and N2. For example, the potential V1 applied to the power supply terminal N1 is one of the power supply potential Vdd and the ground potential Vss, and the potential V2 applied to the power supply terminal N2 is the other of the power supply potential Vdd and the ground potential Vss. It is one of.

  The transistor SN is a spin transistor, and includes a magnetic pinned layer whose magnetization direction is fixed and a magnetic recording layer whose magnetization direction changes. The conductance of the transistor SN changes according to the relative relationship between the magnetization direction of the magnetic pinned layer and the magnetization direction of the magnetic recording layer.

  The transistor SN is an N-channel MISFET in which an N-type channel is formed when turned on. Therefore, the transistor SN is formed in the P-type semiconductor region. A floating third gate electrode (floating gate electrode) is disposed above the channel of the transistor SN, and a fourth gate electrode is disposed above the third gate electrode.

  The transistor SP is a P-channel MISFET in which a P-type channel is formed when turned on. Accordingly, the transistor SP is formed in the N-type semiconductor region. The conductance of the transistor SP is set to a value between the maximum value and the minimum value of the conductance of the transistor SN.

  For example, when the magnetization state of the transistor SN, that is, the relative relationship between the magnetization direction of the magnetic pinned layer and the magnetization direction of the magnetic recording layer, the conductance Gm in the parallel state is 100 (maximum value), When the conductance Gm is 1 (minimum value), the conductance Gm of the transistor SP is set to 10.

  A floating first gate electrode (floating gate electrode) connected to the third gate electrode is disposed above the channel of the transistor SP, and a second gate electrode is disposed above the first gate electrode. Is placed.

  Therefore, an input signal (logical value “0” or “1”) input to the second gate electrode of the transistor SP is A, and an input signal (logical value “0”) input to the fourth gate electrode of the transistor SN. “Or“ 1 ”) is B, the potential Vfg of the first and third gate electrodes in the floating state can be expressed by (A + B) / 2.

  The transistor T1 and the resistance element R1 are connected in series between a power supply terminal (power supply node) N3 and an output node O1. A potential V1 is applied to the power supply terminal N3. The output node O1 is a connection point between the two transistors SP and SN, and the output signal Y (= Vout) is output from the output node O1.

  The transistor T1 is an N-channel MISFET in which an N-type channel is formed when turned on. However, instead of this, a P-channel MISFET in which a P-type channel is formed at the time of ON may be used as the transistor T1. A write signal W serving as a control signal when performing logic reconfiguration is input to the gate electrode of the transistor T1.

  The programmable logic circuit of FIGS. 12 and 13 is a modification of the programmable logic circuit of FIG.

  In both FIG. 12 and FIG. 13, the transistor SP is composed of a spin transistor. The other points are the same as in FIG.

  The transistor SP includes a magnetic pinned layer whose magnetization direction is fixed and a magnetic recording layer whose magnetization direction changes.

  In FIG. 12, the magnetization state of the transistor SP, that is, the relative relationship between the magnetization direction of the magnetic pinned layer and the magnetization direction of the magnetic recording layer is fixed to a parallel state (conductance Gm = 10). The magnetization state is fixed to the anti-parallel state (conductance Gm = 10).

  The programmable logic circuits shown in FIG. 11 to FIG. 13 are set so as to constitute specific logic that becomes the output signal (logic value) Y with respect to the input signals (logic values) A and B in the initial state.

  When reconfiguring such a programmable logic circuit, input signals A and B are applied to the transistors SP and SN, potentials V1, V2 and V2 are applied to the power supply terminals N1, N2 and N3, and a write signal W is applied. Set to “H”.

  Thereafter, a spin injection current is passed between the power supply terminals N2 and N3, and then the output signal Y with respect to the input signals A and B is verified.

  When the magnetization state of the magnetic recording layer of the transistor SP is not changed by the spin injection current, the output signal Y with respect to the input signals A and B remains in the initial state, so that it is determined that the logic reconfiguration is incomplete.

  Further, the spin injection current is passed again between the power supply terminals N2 and N3 while changing the conditions regarding the spin injection current, and then the output signal Y with respect to the input signals A and B is verified.

  When the magnetization state of the magnetic recording layer of the transistor SP is changed by the spin injection current, a desired output signal Y is obtained for the input signals A and B, and therefore it is determined that the logic reconfiguration is completed.

B. Device structure example 1
An example of a device structure of a programmable logic circuit according to the second embodiment will be described. Here, the structure in the case where FIG. 12 is made into a device among the programmable logic circuits of FIGS. 11 to 13 is taken as an example.

  FIG. 14 is a plan view of the device structure, and FIG. 15 is a cross-sectional view taken along line XV-XV in FIG.

  For example, an element isolation insulating layer 17 having an STI structure is formed in the semiconductor substrate 10. In the element region surrounded by the element isolation insulating layer 17, an N-type well region 10a and a P-type well region 10b are formed.

  In a recess provided at the boundary between the N-type well region 10a and the P-type well region 10b, a ferromagnetic body 12a as a pinned layer having a fixed magnetization direction is formed. In this example, the magnetization direction of the ferromagnetic body 12a is fixed to the right with respect to the paper surface. The ferromagnetic body 12a is shared as the drains of the transistors SP and SN.

  An antiferromagnetic material 13 as a pinned layer is formed on the ferromagnetic material 12a. A tunnel barrier layer 11a is formed between the N-type well region 10a and the ferromagnetic body 12a and between the P-type well region 10b and the ferromagnetic body 12a.

  In the concave portion provided in the P-type well region 10b, a ferromagnetic body 12b is formed as a free layer whose magnetization direction changes. In this example, the magnetization direction of the residual magnetization of the ferromagnetic body 12b is rightward or leftward with respect to the paper surface. The ferromagnetic body 12b becomes a source of the transistor SN.

  A tunnel barrier layer 11b is formed between the P-type well region 10b and the ferromagnetic body 12b.

  A ferromagnetic body 12b 'serving as a pinned layer whose magnetization direction is fixed is formed in a recess provided in the N-type well region 10a. In this example, the magnetization direction of the ferromagnetic body 12b 'is fixed to the right with respect to the paper surface. The ferromagnetic body 12b 'serves as the source of the transistor SP.

  An antiferromagnetic material 13 as a pinned layer is formed on the ferromagnetic material 12b '. A tunnel barrier layer 11b is formed between the N-type well region 10a and the ferromagnetic body 12b '.

  A floating gate electrode FG is formed on the channel between the ferromagnetic bodies 12a and 12b via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode is formed via an insulating layer made of ONO. An input signal B is input to the gate electrode.

  A floating gate electrode FG is formed on the channel between the ferromagnetic bodies 12a and 12b 'via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode to which the input signal A is input is formed via an insulating layer made of ONO.

  The ferromagnetic body 12b 'serving as the source of the transistor SP is connected to the power supply terminal N1 to which the power supply potential V1 is applied. The ferromagnetic body 12b as the source of the transistor SN is connected to the power supply terminal N2 to which the power supply potential V2 is applied.

  The ferromagnetic body 12a as the drains of the transistors SP and SN is connected to the output node O1. Between the output node O1 and the power supply terminal N3, a transistor T1 and a resistance element R1 whose on / off is controlled by a write signal W are connected. A power supply potential V1 is applied to the power supply terminal N3.

  For the transistors SP and SN, one or both of the tunnel barrier layers 11a and 11b may be omitted.

  The potential of the power supply terminal N3 is the same as the potential V1 of the power supply terminal N1, but may be set to other potentials.

C. Reconfiguration example 1
An example of logic reconfiguration for the programmable logic circuit having the structure of FIGS. 14 and 15 will be described.

  In the initial state, the magnetization state of the transistor SN is set to a parallel state. That is, the magnetization direction of the residual magnetization of the ferromagnetic body 12b is set to the right with respect to the paper surface. In this case, as shown in FIG. 12, the ratio of the conductance Gm of the transistors SN and SP is 100: 10.

Accordingly, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 3.

  That is, the logic of the programmable logic circuit in the initial state is NOR, and the equivalent circuit of the device of FIGS. 14 and 15 is a symbol of the NOR gate as shown in FIG.

  If the devices of FIGS. 14 and 15 are used as NOR gates, it is not necessary to reconfigure the logic, so the write signal W remains “L”.

  If the devices of FIGS. 14 and 15 are used as NAND gates, the write signal W is set to “H” and the logic is reconfigured as follows.

  When the power supply potentials V1 (= Vdd), V2 (= Vss), and V1 (= Vdd) are applied to the power supply terminals N1, N2, and N3, respectively, with the write signal W set to “H”, the spin injection current (current pulse) ) Flows from the ferromagnetic body 12a as the pinned layer toward the ferromagnetic body 12b as the free layer, as shown in FIG.

  At this time, the ferromagnet 12a acts as a spin reflection layer that reflects electrons polarized leftward with respect to the paper surface, and the spin-polarized electrons are electrons in the ferromagnet 12b as a free layer. Is given a spin torque. For this reason, the magnetization direction of the ferromagnetic body 12b changes from the right direction (parallel state) with respect to the paper surface to the left direction (antiparallel state) with respect to the paper surface.

  Then, as shown in FIG. 12, the ratio of the conductance Gm of the transistors SN and SP becomes 1:10.

Accordingly, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 4.

  That is, the logic of the programmable logic circuit is NAND, and the equivalent circuit of the device of FIGS. 14 and 15 is a symbol of the NAND gate as shown in FIG.

  In this manner, the logic of the programmable logic circuit can be reconfigured from the NOR gate to the NAND gate by the write signal W.

  As in the first embodiment, logic verification can be performed at the same time as writing (reconfiguration of logic).

D. Device structure example 2
Subsequently, an example of the device structure of the programmable logic circuit according to the second embodiment will be described. Here, of the programmable logic circuits shown in FIGS. 11 to 13, the structure of FIG. 11 as a device is taken as an example.

  FIG. 17 is a plan view of the device structure, and FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG.

  For example, an element isolation insulating layer 17 having an STI structure is formed in the semiconductor substrate 10. In the element region surrounded by the element isolation insulating layer 17, an N-type well region 10a and a P-type well region 10b are formed.

  A ferromagnetic body 12a as a pinned layer having a fixed magnetization direction is formed in one of the two recesses provided in the P-type well region 10b, and the magnetization direction is formed in the other one. A ferromagnetic body 12b is formed as a changing free layer.

  In this example, the magnetization direction of the ferromagnetic body 12a is fixed to the right with respect to the paper surface, and the magnetization direction of the residual magnetization of the ferromagnetic body 12b is rightward or leftward with respect to the paper surface.

  An antiferromagnetic material 13 as a pinned layer is formed on the ferromagnetic material 12a. Tunnel barrier layers 11a and 11b are formed between the P-type well region 10b and the ferromagnetic bodies 12a and 12b.

  The ferromagnetic body 12a serves as the source of the transistor SN, and the ferromagnetic body 12b serves as the drain of the transistor SN.

  A P-type source region 12c and a P-type drain region 12d are formed in the N-type well region 10a.

  A floating gate electrode FG is formed on the channel between the ferromagnetic bodies 12a and 12b via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode is formed via an insulating layer made of ONO. An input signal B is input to the gate electrode.

  A floating gate electrode FG is formed on the channel between the source / drain regions 12c and 12d via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode to which the input signal A is input is formed via an insulating layer made of ONO.

  The source region 12c of the transistor SP is connected to the power supply terminal N1 to which the power supply potential V1 is applied. The ferromagnetic body 12a as the source of the transistor SN is connected to the power supply terminal N2 to which the power supply potential V2 is applied.

  The drain region 12d of the transistor SP and the ferromagnetic body 12b as the drain of the transistor SN are each connected to the output node O1. Between the output node O1 and the power supply terminal N3, a transistor T1 and a resistance element R1 whose on / off is controlled by a write signal W are connected. A power supply potential V1 is applied to the power supply terminal N3.

  With respect to the transistor SN, one or both of the tunnel barrier layers 11a and 11b may be omitted.

  The potential of the power supply terminal N3 is the same as the potential V1 of the power supply terminal N1, but may be set to other potentials.

E. Reconfiguration example 2
An example of logic reconfiguration for the programmable logic circuit having the structure of FIGS. 17 and 18 will be described.

  In the initial state, the magnetization state of the transistor SN is set to the anti-parallel state. That is, the magnetization direction of the residual magnetization of the ferromagnetic body 12b is set to the left with respect to the paper surface. In this case, as shown in FIG. 11, the ratio of the conductance Gm of the transistors SN and SP is 1:10.

  Accordingly, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 4.

  That is, the logic of the programmable logic circuit in the initial state is NAND, and the equivalent circuit of the device of FIGS. 17 and 18 is a symbol of the NAND gate as shown in FIG.

  If the devices of FIGS. 17 and 18 are used as NAND gates, it is not necessary to reconfigure the logic, so the write signal W remains “L”.

  If the devices of FIGS. 17 and 18 are used as NOR gates, the write signal W is set to “H” and the logic is reconfigured as follows.

  When the power supply potentials V1 (= Vdd), V2 (= Vss), and V1 (= Vdd) are applied to the power supply terminals N1, N2, and N3, respectively, with the write signal W set to “H”, the spin injection current (current pulse) ) Flows from the ferromagnetic body 12b as the free layer toward the ferromagnetic body 12a as the pinned layer, as shown in FIG.

  At this time, the ferromagnet 12a acts as a spin filter that passes only the electrons spin-polarized to the right with respect to the paper surface. The spin-polarized electrons are contained in the ferromagnet 12b as a free layer. Gives electrons spin torque. For this reason, the magnetization direction of the ferromagnet 12b changes from leftward to the paper surface (anti-parallel state) to rightward to the paper surface (parallel state).

  Then, as shown in FIG. 11, the ratio of the conductance Gm of the transistors SN and SP becomes 100: 10.

  Accordingly, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 3.

  That is, the logic of the programmable logic circuit is NOR, and the equivalent circuit of the device of FIGS. 17 and 18 is a symbol of a NOR gate as shown in FIG.

  In this manner, the logic of the programmable logic circuit can be reconfigured from the NAND gate to the NOR gate by the write signal W.

  As in the first embodiment, logic verification can be performed at the same time as writing (reconfiguration of logic).

F. Principle of reconstruction
The principle of reconfiguration of the programmable logic circuit of FIGS. 11 to 13 will be described.

  FIG. 20 shows the relationship between the floating gate potential Vfg and the output signal Y (= Vout).

  When the value of the conductance Gm of the transistor SP is set to a value between the maximum value and the minimum value of the conductance Gm of the transistor SN, the conductance Gm of the transistor SN is determined according to the same principle as in the first embodiment. Thus, the output signal Y (= Vout) when the floating gate potential Vfg is “1/2” changes.

G. Summary
As described above, according to the second embodiment, it is possible to realize a programmable logic circuit in which the wiring for reconfiguring the logic circuit is simple and the logic circuit can be easily reconfigured in a short time. .

(3) Third embodiment
A. Circuit
FIG. 21 shows a basic unit of a programmable logic circuit according to the third embodiment.

  Transistors SN and SP are connected in series between power supply terminals (power supply nodes) N1 and N2. Different potentials V1 and V2 are applied to the power supply terminals N1 and N2. For example, the potential V1 applied to the power supply terminal N1 is one of the power supply potential Vdd and the ground potential Vss, and the potential V2 applied to the power supply terminal N2 is the other of the power supply potential Vdd and the ground potential Vss. It is one of.

  The transistor SN is a spin transistor, and includes a magnetic pinned layer whose magnetization direction is fixed and a magnetic recording layer whose magnetization direction changes. The conductance of the transistor SN changes according to the relative relationship between the magnetization direction of the magnetic pinned layer and the magnetization direction of the magnetic recording layer.

  The transistor SN is an N-channel MISFET in which an N-type channel is formed when turned on. Therefore, the transistor SN is formed in the P-type semiconductor region. A floating first gate electrode (floating gate electrode) is disposed above the channel of the transistor SN, and a second gate electrode is disposed above the first gate electrode.

  The transistor SP is a P-channel MISFET in which a P-type channel is formed when turned on. Accordingly, the transistor SP is formed in the N-type semiconductor region. The conductance of the transistor SP is set to a value between the maximum value and the minimum value of the conductance of the transistor SN.

  For example, when the magnetization state of the transistor SN, that is, the relative relationship between the magnetization direction of the magnetic pinned layer and the magnetization direction of the magnetic recording layer, the conductance Gm in the parallel state is 100 (maximum value), When the conductance Gm is 1 (minimum value), the conductance Gm of the transistor SP is set to 10.

  A floating third gate electrode (floating gate electrode) connected to the first gate electrode is disposed above the channel of the transistor SP, and a fourth gate electrode is disposed above the third gate electrode. Is placed.

  Therefore, an input signal (logical value “0” or “1”) input to the second gate electrode of the transistor SN is A, and an input signal (logical value “0”) is input to the fourth gate electrode of the transistor SP. “Or“ 1 ”) is B, the potential Vfg of the first and third gate electrodes in the floating state can be expressed by (A + B) / 2.

  The transistor T1 and the resistance element R1 are connected in series between a power supply terminal (power supply node) N3 and an output node O1. A potential V2 is applied to the power supply terminal N3. The output node O1 is a connection point between the two transistors SN and SP, and the output signal Y (= Vout) is output from the output node O1.

  The transistor T1 is an N-channel MISFET in which an N-type channel is formed when turned on. However, instead of this, a P-channel MISFET in which a P-type channel is formed at the time of ON may be used as the transistor T1. A write signal W serving as a control signal when performing logic reconfiguration is input to the gate electrode of the transistor T1.

  The programmable logic circuit of FIGS. 22 and 23 is a modification of the programmable logic circuit of FIG.

  22 and 23, the transistor SP is composed of a spin transistor. Other points are the same as in FIG.

  The transistor SP includes a magnetic pinned layer whose magnetization direction is fixed and a magnetic recording layer whose magnetization direction changes.

  In FIG. 22, the magnetization state of the transistor SP, that is, the relative relationship between the magnetization direction of the magnetic pinned layer and the magnetization direction of the magnetic recording layer is fixed to a parallel state (conductance Gm = 10). The magnetization state is fixed to the anti-parallel state (conductance Gm = 10).

  The programmable logic circuit shown in FIG. 21 to FIG. 23 is set so as to constitute a specific logic that becomes an output signal (logic value) Y with respect to input signals (logic values) A and B in the initial state.

  When reconfiguring such a programmable logic circuit, input signals A and B are applied to the transistors SN and SP, potentials V1, V2 and V2 are applied to the power supply terminals N1, N2 and N3, and a write signal W is applied. Set to “H”.

  Thereafter, a spin injection current is passed between the power supply terminals N1 and N3, and then the output signal Y with respect to the input signals A and B is verified.

  When the magnetization state of the magnetic recording layer of the transistor SN is not changed by the spin injection current, the output signal Y with respect to the input signals A and B remains in the initial state, so that it is determined that the logic reconfiguration is incomplete.

  In addition, the spin injection current is passed again between the power supply terminals N1 and N3 while changing the conditions regarding the spin injection current, and then the output signal Y with respect to the input signals A and B is verified.

  When the magnetization state of the magnetic recording layer of the transistor SN changes due to the spin injection current, a desired output signal Y is obtained for the input signals A and B, and therefore it is determined that the logic reconfiguration has been completed.

B. Device structure example 1
An example of a device structure of a programmable logic circuit according to the third embodiment will be described. Here, of the programmable logic circuits of FIG. 21 to FIG. 23, the structure of FIG. 22 as a device is taken as an example.

  24 shows a plan view of the device structure, and FIG. 25 shows a cross-sectional view along the line XXV-XXV in FIG.

  For example, an element isolation insulating layer 17 having an STI structure is formed in the semiconductor substrate 10. In the element region surrounded by the element isolation insulating layer 17, an N-type well region 10a and a P-type well region 10b are formed.

  In a recess provided at the boundary between the N-type well region 10a and the P-type well region 10b, a ferromagnetic body 12a as a pinned layer having a fixed magnetization direction is formed. In this example, the magnetization direction of the ferromagnetic body 12a is fixed to the right with respect to the paper surface. The ferromagnetic body 12a is shared as the drains of the transistors SN and SP.

  An antiferromagnetic material 13 as a pinned layer is formed on the ferromagnetic material 12a. A tunnel barrier layer 11a is formed between the N-type well region 10a and the ferromagnetic body 12a and between the P-type well region 10b and the ferromagnetic body 12a.

  In the concave portion provided in the P-type well region 10b, a ferromagnetic body 12b is formed as a free layer whose magnetization direction changes. In this example, the magnetization direction of the residual magnetization of the ferromagnetic body 12b is rightward or leftward with respect to the paper surface. The ferromagnetic body 12b becomes a source of the transistor SN.

  A tunnel barrier layer 11b is formed between the P-type well region 10b and the ferromagnetic body 12b.

  A ferromagnetic body 12b 'serving as a pinned layer whose magnetization direction is fixed is formed in a recess provided in the N-type well region 10a. In this example, the magnetization direction of the ferromagnetic body 12b 'is fixed to the right with respect to the paper surface. The ferromagnetic body 12b 'serves as the source of the transistor SP.

  An antiferromagnetic material 13 as a pinned layer is formed on the ferromagnetic material 12b '. A tunnel barrier layer 11b is formed between the N-type well region 10a and the ferromagnetic body 12b '.

  A floating gate electrode FG is formed on the channel between the ferromagnetic bodies 12a and 12b via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode is formed via an insulating layer made of ONO. An input signal A is input to the gate electrode.

  A floating gate electrode FG is formed on the channel between the ferromagnetic bodies 12a and 12b 'via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode to which the input signal B is input is formed via an insulating layer made of ONO.

  The ferromagnetic body 12b as the source of the transistor SN is connected to the power supply terminal N1 to which the power supply potential V1 is applied. The ferromagnetic body 12b 'as the source of the transistor SP is connected to the power supply terminal N2 to which the power supply potential V2 is applied.

  The ferromagnetic body 12a as the drains of the transistors SN and SP is connected to the output node O1. Between the output node O1 and the power supply terminal N3, a transistor T1 and a resistance element R1 whose on / off is controlled by a write signal W are connected. A power supply potential V2 is applied to the power supply terminal N3.

  For the transistors SN and SP, one or both of the tunnel barrier layers 11a and 11b may be omitted.

  The potential of the power supply terminal N3 is the same as the potential V2 of the power supply terminal N2, but may be set to other potentials.

C. Reconfiguration example 1
An example of logic reconfiguration for the programmable logic circuit having the structure of FIGS. 24 and 25 will be described.

  In the initial state, the magnetization state of the transistor SN is set to the anti-parallel state. That is, the magnetization direction of the residual magnetization of the ferromagnetic body 12b is set to the left with respect to the paper surface. In this case, as shown in FIG. 22, the ratio of the conductance Gm of the transistors SN and SP is 1:10.

Accordingly, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 5.

  That is, the logic of the programmable logic circuit in the initial state is AND, and the equivalent circuit of the device of FIGS. 24 and 25 is a symbol of an AND gate as shown in FIG.

  If the devices of FIGS. 24 and 25 are used as AND gates, it is not necessary to reconfigure the logic, so the write signal W remains “L”.

  If the devices of FIGS. 24 and 25 are used as OR gates, the write signal W is set to “H” and the logic is reconfigured as follows.

  When the power supply potentials V1 (= Vdd), V2 (= Vss), and V2 (= Vss) are applied to the power supply terminals N1, N2, and N3, respectively, while the write signal W is set to “H”, the spin injection current (current pulse) ) Flows from the ferromagnetic body 12b as the free layer toward the ferromagnetic body 12a as the pinned layer, as shown in FIG.

  At this time, the ferromagnet 12a acts as a spin filter that passes only the electrons spin-polarized to the right with respect to the paper surface. The spin-polarized electrons are contained in the ferromagnet 12b as a free layer. Gives electrons spin torque. For this reason, the magnetization direction of the ferromagnet 12b changes from leftward to the paper surface (anti-parallel state) to rightward to the paper surface (parallel state).

  Then, as shown in FIG. 22, the ratio of the conductance Gm of the transistors SN and SP becomes 100: 10.

Therefore, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 6.

  That is, the logic of the programmable logic circuit is OR, and the equivalent circuit of the device of FIGS. 24 and 25 is a symbol of the OR gate as shown in FIG.

  In this manner, the logic of the programmable logic circuit can be reconfigured from the AND gate to the OR gate by the write signal W.

  As in the first embodiment, logic verification can be performed at the same time as writing (reconfiguration of logic).

D. Device structure example 2
Next, an example of the device structure of the programmable logic circuit according to the third embodiment will be described. Here, of the programmable logic circuits of FIGS. 21 to 23, the structure of FIG. 21 as a device is taken as an example.

  27 shows a plan view of the device structure, and FIG. 28 shows a cross-sectional view taken along line XXVIII-XXVIII in FIG.

  For example, an element isolation insulating layer 17 having an STI structure is formed in the semiconductor substrate 10. In the element region surrounded by the element isolation insulating layer 17, an N-type well region 10a and a P-type well region 10b are formed.

  A ferromagnetic body 12a as a pinned layer having a fixed magnetization direction is formed in one of the two recesses provided in the P-type well region 10b, and the magnetization direction is formed in the other one. A ferromagnetic body 12b is formed as a changing free layer.

  In this example, the magnetization direction of the ferromagnetic body 12a is fixed to the right with respect to the paper surface, and the magnetization direction of the residual magnetization of the ferromagnetic body 12b is rightward or leftward with respect to the paper surface.

  An antiferromagnetic material 13 as a pinned layer is formed on the ferromagnetic material 12a. Tunnel barrier layers 11a and 11b are formed between the P-type well region 10b and the ferromagnetic bodies 12a and 12b.

  The ferromagnetic body 12a serves as the source of the transistor SN, and the ferromagnetic body 12b serves as the drain of the transistor SN.

  A P-type source region 12c and a P-type drain region 12d are formed in the N-type well region 10a.

  A floating gate electrode FG is formed on the channel between the ferromagnetic bodies 12a and 12b via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode is formed via an insulating layer made of ONO. An input signal A is input to the gate electrode.

  A floating gate electrode FG is formed on the channel between the source / drain regions 12c and 12d via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode to which the input signal B is input is formed via an insulating layer made of ONO.

  The ferromagnetic body 12a as the source of the transistor SN is connected to the power supply terminal N1 to which the power supply potential V1 is applied. The source region 12c of the transistor SP is connected to the power supply terminal N2 to which the power supply potential V2 is applied.

  The ferromagnetic body 12b as the drain of the transistor SN and the drain region 12d of the transistor SP are each connected to the output node O1. Between the output node O1 and the power supply terminal N3, a transistor T1 and a resistance element R1 whose on / off is controlled by a write signal W are connected. A power supply potential V2 is applied to the power supply terminal N3.

  With respect to the transistor SN, one or both of the tunnel barrier layers 11a and 11b may be omitted.

  The potential of the power supply terminal N3 is the same as the potential V2 of the power supply terminal N2, but may be set to other potentials.

E. Reconfiguration example 2
An example of logic reconfiguration for the programmable logic circuit having the structure of FIGS. 27 and 28 will be described.

  In the initial state, the magnetization state of the transistor SN is set to a parallel state. That is, the magnetization direction of the residual magnetization of the ferromagnetic body 12b is set to the right with respect to the paper surface. In this case, as shown in FIG. 21, the ratio of the conductance Gm of the transistors SN and SP is 100: 10.

  Therefore, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 6.

  That is, the logic of the programmable logic circuit in the initial state is OR, and the equivalent circuit of the device of FIGS. 27 and 28 is a symbol of the OR gate as shown in FIG.

  If the devices of FIGS. 27 and 28 are used as OR gates, it is not necessary to reconfigure the logic, so the write signal W remains “L”.

  If the device of FIGS. 27 and 28 is used as an AND gate, the write signal W is set to “H” and the logic is reconfigured as follows.

  When the power supply potentials V1 (= Vdd), V2 (= Vss), and V2 (= Vss) are applied to the power supply terminals N1, N2, and N3, respectively, while the write signal W is set to “H”, the spin injection current (current pulse) ) Flows from the ferromagnetic body 12a as the pinned layer toward the ferromagnetic body 12b as the free layer, as shown in FIG.

  At this time, the ferromagnet 12a acts as a spin reflection layer that reflects electrons polarized leftward with respect to the paper surface, and the spin-polarized electrons are electrons in the ferromagnet 12b as a free layer. Is given a spin torque. For this reason, the magnetization direction of the ferromagnetic body 12b changes from the right direction (parallel state) with respect to the paper surface to the left direction (antiparallel state) with respect to the paper surface.

  Then, as shown in FIG. 21, the ratio of the conductance Gm of the transistors SN and SP is 1:10.

  Accordingly, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 5.

  That is, the logic of the programmable logic circuit is AND, and the equivalent circuit of the device of FIGS. 27 and 28 is a symbol of an AND gate as shown in FIG.

  Thus, the logic of the programmable logic circuit can be reconfigured from the OR gate to the AND gate by the write signal W.

  As in the first embodiment, logic verification can be performed at the same time as writing (reconfiguration of logic).

F. Principle of reconstruction
The principle of reconfiguration of the programmable logic circuit of FIGS. 21 to 23 will be described.

  FIG. 30 shows the relationship between the floating gate potential Vfg and the output signal Y (= Vout).

  When the value of the conductance Gm of the transistor SP is set to a value between the maximum value and the minimum value of the conductance Gm of the transistor SN, the conductance Gm of the transistor SN is determined according to the same principle as in the first embodiment. Thus, the output signal Y (= Vout) when the floating gate potential Vfg is “1/2” changes.

G. Summary
As described above, according to the third embodiment, it is possible to realize a programmable logic circuit in which the wiring for reconfiguring the logic circuit is simple and the logic circuit can be easily reconfigured in a short time. .

(4) Fourth embodiment
A. Circuit
FIG. 31 shows a basic unit of a programmable logic circuit according to the fourth embodiment.

  Transistors SN and SP are connected in series between power supply terminals (power supply nodes) N1 and N2. Different potentials V1 and V2 are applied to the power supply terminals N1 and N2. For example, the potential V1 applied to the power supply terminal N1 is one of the power supply potential Vdd and the ground potential Vss, and the potential V2 applied to the power supply terminal N2 is the other of the power supply potential Vdd and the ground potential Vss. It is one of.

  The transistor SP is a spin transistor, and includes a magnetic pinned layer whose magnetization direction is fixed and a magnetic recording layer whose magnetization direction changes. The conductance of the transistor SP changes according to the relative relationship between the magnetization direction of the magnetic pinned layer and the magnetization direction of the magnetic recording layer.

  The transistor SP is a P-channel MISFET in which a P-type channel is formed when turned on. Accordingly, the transistor SP is formed in the N-type semiconductor region. A floating third gate electrode (floating gate electrode) is disposed above the channel of the transistor SP, and a fourth gate electrode is disposed above the third gate electrode.

  The transistor SN is an N-channel MISFET in which an N-type channel is formed when turned on. Therefore, the transistor SN is formed in the P-type semiconductor region. The conductance of the transistor SN is set to a value between the maximum value and the minimum value of the conductance of the transistor SP.

  For example, when the magnetization state of the transistor SP, that is, the relative relationship between the magnetization direction of the magnetic pinned layer and the magnetization direction of the magnetic recording layer, the conductance Gm in the parallel state is 100 (maximum value), When the conductance Gm is 1 (minimum value), the conductance Gm of the transistor SN is set to 10.

  A floating first gate electrode (floating gate electrode) connected to the third gate electrode is disposed above the channel of the transistor SN, and a second gate electrode is disposed above the first gate electrode. Is placed.

  Therefore, an input signal (logical value “0” or “1”) input to the second gate electrode of the transistor SN is A, and an input signal (logical value “0”) is input to the fourth gate electrode of the transistor SP. “Or“ 1 ”) is B, the potential Vfg of the first and third gate electrodes in the floating state can be expressed by (A + B) / 2.

  The transistor T1 and the resistance element R1 are connected in series between a power supply terminal (power supply node) N3 and an output node O1. A potential V1 is applied to the power supply terminal N3. The output node O1 is a connection point between the two transistors SN and SP, and the output signal Y (= Vout) is output from the output node O1.

  The transistor T1 is an N-channel MISFET in which an N-type channel is formed when turned on. However, instead of this, a P-channel MISFET in which a P-type channel is formed at the time of ON may be used as the transistor T1. A write signal W serving as a control signal when performing logic reconfiguration is input to the gate electrode of the transistor T1.

  The programmable logic circuit of FIGS. 32 and 33 is a modification of the programmable logic circuit of FIG.

  In both FIG. 32 and FIG. 33, the transistor SN is composed of a spin transistor. The other points are the same as in FIG.

  The transistor SN includes a magnetic pinned layer whose magnetization direction is fixed and a magnetic recording layer whose magnetization direction changes.

  In FIG. 32, the magnetization state of the transistor SN, that is, the relative relationship between the magnetization direction of the magnetic pinned layer and the magnetization direction of the magnetic recording layer is fixed to a parallel state (conductance Gm = 10). The magnetization state is fixed to the anti-parallel state (conductance Gm = 10).

  The programmable logic circuits shown in FIG. 31 to FIG. 33 are set so as to constitute specific logic that becomes an output signal (logic value) Y with respect to input signals (logic values) A and B in the initial state.

  When reconfiguring such a programmable logic circuit, the input signals A and B are applied to the transistors SN and SP, the potentials V1 and V2 are applied to the power supply terminals N1, N2 and N3, and the write signal W is set to “H”. "

  Thereafter, a spin injection current is passed between the power supply terminals N2 and N3, and then the output signal Y with respect to the input signals A and B is verified.

  When the magnetization state of the magnetic recording layer of the transistor SN is not changed by the spin injection current, the output signal Y with respect to the input signals A and B remains in the initial state, so that it is determined that the logic reconfiguration is incomplete.

  Further, the spin injection current is passed again between the power supply terminals N2 and N3 while changing the conditions regarding the spin injection current, and then the output signal Y with respect to the input signals A and B is verified.

  When the magnetization state of the magnetic recording layer of the transistor SN changes due to the spin injection current, a desired output signal Y is obtained for the input signals A and B, and therefore it is determined that the logic reconfiguration has been completed.

B. Device structure example 1
An example of a device structure of a programmable logic circuit according to the fourth embodiment will be described. Here, of the programmable logic circuits of FIGS. 31 to 33, the structure of FIG. 32 as a device is taken as an example.

  34 shows a plan view of the device structure, and FIG. 35 shows a cross-sectional view taken along the line XXXV-XXXV in FIG.

  For example, an element isolation insulating layer 17 having an STI structure is formed in the semiconductor substrate 10. In the element region surrounded by the element isolation insulating layer 17, an N-type well region 10a and a P-type well region 10b are formed.

  In a recess provided at the boundary between the N-type well region 10a and the P-type well region 10b, a ferromagnetic body 12a as a pinned layer having a fixed magnetization direction is formed. In this example, the magnetization direction of the ferromagnetic body 12a is fixed to the right with respect to the paper surface. The ferromagnetic body 12a is shared as the drains of the transistors SN and SP.

  An antiferromagnetic material 13 as a pinned layer is formed on the ferromagnetic material 12a. A tunnel barrier layer 11a is formed between the N-type well region 10a and the ferromagnetic body 12a and between the P-type well region 10b and the ferromagnetic body 12a.

  In the recess provided in the N-type well region 10a, a ferromagnetic body 12b is formed as a free layer whose magnetization direction changes. In this example, the magnetization direction of the residual magnetization of the ferromagnetic body 12b is rightward or leftward with respect to the paper surface. The ferromagnetic body 12b becomes a source of the transistor SP.

  A tunnel barrier layer 11b is formed between the N-type well region 10a and the ferromagnetic body 12b.

  A ferromagnetic body 12b 'serving as a pinned layer whose magnetization direction is fixed is formed in the recess provided in the P-type well region 10b. In this example, the magnetization direction of the ferromagnetic body 12b 'is fixed to the right with respect to the paper surface. The ferromagnetic body 12b 'serves as the source of the transistor SN.

  An antiferromagnetic material 13 as a pinned layer is formed on the ferromagnetic material 12b '. A tunnel barrier layer 11b is formed between the P-type well region 10b and the ferromagnetic body 12b '.

  A floating gate electrode FG is formed on the channel between the ferromagnetic bodies 12a and 12b via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode is formed via an insulating layer made of ONO. An input signal B is input to the gate electrode.

  A floating gate electrode FG is formed on the channel between the ferromagnetic bodies 12a and 12b 'via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode to which the input signal A is input is formed via an insulating layer made of ONO.

  The ferromagnetic body 12b 'serving as the source of the transistor SN is connected to the power supply terminal N1 to which the power supply potential V1 is applied. The ferromagnetic body 12b as the source of the transistor SP is connected to the power supply terminal N2 to which the power supply potential V2 is applied.

  The ferromagnetic body 12a as the drains of the transistors SN and SP is connected to the output node O1. Between the output node O1 and the power supply terminal N3, a transistor T1 and a resistance element R1 whose on / off is controlled by a write signal W are connected. A power supply potential V1 is applied to the power supply terminal N3.

  For the transistors SN and SP, one or both of the tunnel barrier layers 11a and 11b may be omitted.

  The potential of the power supply terminal N3 is the same as the potential V1 of the power supply terminal N1, but may be set to other potentials.

C. Reconfiguration example 1
An example of logic reconfiguration for the programmable logic circuit having the structure of FIGS. 34 and 35 will be described.

  In the initial state, the magnetization state of the transistor SP is set to a parallel state. That is, the magnetization direction of the residual magnetization of the ferromagnetic body 12b is set to the right with respect to the paper surface. In this case, as shown in FIG. 32, the ratio of the conductance Gm of the transistors SP and SN is 100: 10.

Therefore, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 7.

  That is, the logic of the programmable logic circuit in the initial state is AND, and the equivalent circuit of the device of FIGS. 34 and 35 is a symbol of an AND gate as shown in FIG.

  If the devices of FIGS. 34 and 35 are used as AND gates, it is not necessary to reconfigure the logic, so the write signal W remains “L”.

  If the devices of FIGS. 34 and 35 are used as OR gates, the write signal W is set to “H” and the logic is reconfigured as follows.

  When the power supply potentials V1 (= Vdd), V2 (= Vss), and V1 (= Vdd) are applied to the power supply terminals N1, N2, and N3, respectively, with the write signal W set to “H”, the spin injection current (current pulse) ) Flows from the ferromagnetic body 12a as the pinned layer toward the ferromagnetic body 12b as the free layer, as shown in FIG.

  At this time, the ferromagnet 12a acts as a spin reflection layer that reflects electrons polarized leftward with respect to the paper surface, and the spin-polarized electrons are electrons in the ferromagnet 12b as a free layer. Is given a spin torque. For this reason, the magnetization direction of the ferromagnetic body 12b changes from the right direction (parallel state) with respect to the paper surface to the left direction (antiparallel state) with respect to the paper surface.

  Then, as shown in FIG. 32, the ratio of the conductance Gm of the transistors SP and SN is 1:10.

Therefore, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 8.

  That is, the logic of the programmable logic circuit is OR, and the equivalent circuit of the device of FIGS. 34 and 35 is a symbol of the OR gate as shown in FIG.

  In this manner, the logic of the programmable logic circuit can be reconfigured from the AND gate to the OR gate by the write signal W.

D. Device structure example 2
Subsequently, an example of a device structure of a programmable logic circuit according to the fourth embodiment will be described. Here, of the programmable logic circuits of FIGS. 31 to 33, the structure of FIG. 31 as a device is taken as an example.

  FIG. 37 shows a plan view of the device structure, and FIG. 38 shows a sectional view taken along the line XXXVIII-XXXVIII in FIG.

  For example, an element isolation insulating layer 17 having an STI structure is formed in the semiconductor substrate 10. In the element region surrounded by the element isolation insulating layer 17, an N-type well region 10a and a P-type well region 10b are formed.

  A ferromagnetic body 12a as a pinned layer having a fixed magnetization direction is formed in one of the two recesses provided in the N-type well region 10a, and the magnetization direction is formed in the other one. A ferromagnetic body 12b is formed as a changing free layer.

  In this example, the magnetization direction of the ferromagnetic body 12a is fixed leftward with respect to the paper surface, and the magnetization direction of the residual magnetization of the ferromagnetic body 12b is rightward or leftward with respect to the paper surface.

  An antiferromagnetic material 13 as a pinned layer is formed on the ferromagnetic material 12a. Tunnel barrier layers 11a and 11b are formed between the N-type well region 10a and the ferromagnetic bodies 12a and 12b.

  The ferromagnetic body 12a becomes the source of the transistor SP, and the ferromagnetic body 12b becomes the drain of the transistor SP.

  An N-type source region 12c and an N-type drain region 12d are formed in the P-type well region 10b.

  A floating gate electrode FG is formed on the channel between the ferromagnetic bodies 12a and 12b via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode is formed via an insulating layer made of ONO. An input signal B is input to the gate electrode.

  A floating gate electrode FG is formed on the channel between the source / drain regions 12c and 12d via a gate insulating layer made of, for example, silicon oxide. The floating gate electrode FG is made of conductive polysilicon containing impurities, for example.

  On the floating gate electrode FG, for example, a gate electrode to which the input signal A is input is formed via an insulating layer made of ONO.

  The source region 12c of the transistor SN is connected to the power supply terminal N1 to which the power supply potential V1 is applied. The ferromagnetic body 12a as the source of the transistor SP is connected to the power supply terminal N2 to which the power supply potential V2 is applied.

  The drain region 12d of the transistor SN and the ferromagnetic body 12b as the drain of the transistor SP are each connected to the output node O1. Between the output node O1 and the power supply terminal N3, a transistor T1 and a resistance element R1 whose on / off is controlled by a write signal W are connected. A power supply potential V1 is applied to the power supply terminal N3.

  Note that one or both of the tunnel barrier layers 11a and 11b may be omitted for the transistor SP.

  The potential of the power supply terminal N3 is the same as the potential V1 of the power supply terminal N1, but may be set to other potentials.

E. Reconfiguration example 2
An example of logic reconfiguration for the programmable logic circuit having the structure of FIGS. 37 and 38 will be described.

  In the initial state, the magnetization state of the transistor SP is set to an anti-parallel state. That is, the magnetization direction of the residual magnetization of the ferromagnetic body 12b is set to the right with respect to the paper surface. In this case, as shown in FIG. 31, the ratio of the conductance Gm of the transistors SP and SN is 1:10.

  Therefore, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 8.

  That is, the logic of the programmable logic circuit in the initial state is OR, and the equivalent circuit of the device of FIGS. 37 and 38 is a symbol of the OR gate as shown in FIG.

  If the devices of FIGS. 37 and 38 are used as OR gates, it is not necessary to reconfigure the logic, so the write signal W remains “L”.

  If the devices of FIGS. 37 and 38 are used as AND gates, the write signal W is set to “H” and the logic is reconfigured as follows.

  When the power supply potentials V1 (= Vdd), V2 (= Vss), and V1 (= Vdd) are applied to the power supply terminals N1, N2, and N3, respectively, with the write signal W set to “H”, the spin injection current (current pulse) ) Flows from the ferromagnetic body 12b as the free layer toward the ferromagnetic body 12a as the pinned layer, as shown in FIG.

  At this time, the ferromagnet 12a acts as a spin filter that allows only electrons that are spin-polarized to the left with respect to the paper surface to pass, and these spin-polarized electrons are contained in the ferromagnet 12b as a free layer. Gives electrons spin torque. For this reason, the magnetization direction of the ferromagnetic body 12b changes from rightward (anti-parallel state) to the paper surface to leftward (parallel state) with respect to the paper surface.

  Then, as shown in FIG. 31, the ratio of the conductance Gm of the transistors SP and SN is 100: 10.

  Therefore, the relationship between the input signals (logic values) A and B and the output signal Y (= Vout) is as shown in Table 7.

  That is, the logic of the programmable logic circuit is AND, and the equivalent circuit of the device of FIGS. 37 and 38 is a symbol of an AND gate as shown in FIG.

  Thus, the logic of the programmable logic circuit can be reconfigured from the OR gate to the AND gate by the write signal W.

  As in the first embodiment, logic verification can be performed at the same time as writing (reconfiguration of logic).

F. Principle of reconstruction
The principle of reconfiguration of the programmable logic circuit of FIGS. 31 to 33 will be described.

  FIG. 40 shows the relationship between the floating gate potential Vfg and the output signal Y (= Vout).

  When the value of the conductance Gm of the transistor SN is set to a value between the maximum value and the minimum value of the conductance Gm of the transistor SP, the value according to the value of the conductance Gm of the transistor SP is determined based on the same principle as in the first embodiment. Thus, the output signal Y (= Vout) when the floating gate potential Vfg is “1/2” changes.

G. Summary
As described above, according to the fourth embodiment, it is possible to realize a programmable logic circuit in which the wiring for reconfiguring the logic circuit is simple and the logic circuit can be easily reconfigured in a short time. .

3. Reconfigurable programmable logic circuit
One of the features of the example of the present invention is that logic reconfiguration and verification can be performed simultaneously, so that logic reconfiguration can be easily performed in a short time without complicating hardware. In that point.

  Therefore, the reconstruction method will be described in detail.

FIG. 41 shows a flow of a programmable logic circuit reconfiguration method.
First, for example, the logic value of the input signal is determined by a random number, and the input signal is applied to the programmable logic circuit (steps ST1 to ST2).

  A write signal (W = “H”) is applied, and power supply potentials V1 and V2 are applied (steps ST3 to ST4).

  Thereafter, the logic value of the output signal of the programmable logic circuit is verified (step ST5).

  It is ascertained whether or not the logic value of the output signal is an expected value (the logic after reconfiguration). If not, the spin injection current (pulse current) is generated (steps ST6 to ST9).

  Here, since the input signal and the power supply potentials V1 and V2 are applied immediately after the spin injection current is passed, the output signal can be verified. That is, the change in magnetization state due to the spin injection current immediately appears as an output signal.

  When the logical value of the output signal is not the expected value, the conditions regarding the spin injection current are changed each time. For example, in step ST8, the magnitude (amplitude), length (width), or both of the pulses of the spin injection current are gradually increased until the logical value of the output signal reaches the expected value.

  However, as shown in step ST7, when the condition regarding the spin injection current reaches the upper limit, for example, the maximum value of the amplitude or width of the pulse, the reconstruction is performed even if the logical value of the output signal is not the expected value. End the operation.

  Thereafter, the reconfiguration operation may be started again from the initial state, or may be processed as a defective product.

  On the other hand, if the logical value of the output signal is an expected value, it is confirmed whether or not the logical value of the output signal has been verified for all combinations of the logical values of the input signal (step ST10).

  If the logic value of the output signal is not verified for all combinations of the logic values of the input signal, the logic value of the input signal is changed, and the logic value of the output signal is verified again (step ST11).

  When the logic values of the output signals are verified for all combinations of the logic values of the input signals, the logic reconfiguration is completed.

  In this example, the input signal is determined by a random number, but may be determined by other methods. Further, the conditions relating to the spin injection current may be simply increased without changing the number of spin injection currents.

  When the programmable logic circuit is reconfigured according to the above flow, especially when a logic circuit is configured by combining a plurality of basic units shown in the first to fourth embodiments, the input signal of the logic circuit If only the correspondence relationship with the output signal is designed, verification of the logic of each basic unit becomes unnecessary.

  Therefore, for the basic unit, only the layout and the channel type (N-type or P-type) of the spin transistor need only be considered, and the design effort and time can be greatly reduced.

  Even when the logic circuit is not designed as a result of hardware failure, if the programmable logic circuit is reconfigured according to the flow of FIG. 41, the defect location is not identified and the design is not corrected. It is also possible to configure a logic circuit that is not affected by the defective part.

  Furthermore, since the output signal can be verified in a state where writing (reconstruction) is performed by supplying a spin injection current, reconstruction can be performed easily in a short time.

4). Example
Hereinafter, an embodiment of reconfiguration of the logic circuit will be described.

  Here, as shown in FIG. 42, an example in which a logic circuit is configured by combining a plurality of basic units described in the first to fourth embodiments will be described.

(1) First embodiment
FIG. 43 shows the programmable logic circuit of the first embodiment.
In this example, two basic units are connected in series.

  Here, the basic unit BU1 is the logic circuit of FIG. 22, and the basic unit BU2 is the logic circuit of FIG.

  This programmable logic circuit is characterized in that two basic units BU1 and BU2 are connected in parallel between a power supply terminal N1 and a power supply terminal N3. In this case, since the logic can be reconfigured by simultaneously applying the spin injection current to the basic units BU1 and BU2, the hardware can be simplified and the reconfiguration can be shortened.

  Vdd is applied as the power supply potential V1 to the power supply terminal N1, and Vss (<Vdd) is applied as the power supply potential V2 to the power supply terminals N2 and N3. The write signal W is input in common to the basic units BU1 and BU2. There are three input signals A, B, and D, and the output signal is Y (= Vout).

  Note that the write signal W may be provided independently to the basic units BU1 and BU2.

  In the initial state, the spin transistors SN1 and SP2 in the basic units BU1 and BU2 are both in a parallel state. In this case, the logic circuit has a structure in which an OR gate and a NAND gate are connected in series as shown in FIG.

  When the logic is reconfigured, the write signal W is set to “H” to turn on the transistors T11 and T12. The spin injection current simultaneously flows in the basic units BU1 and BU2 along the current path shown in FIG.

  For example, the spin transistor SN1 in the basic unit BU1 changes from the parallel state to the anti-parallel state by the mechanism shown in FIG. Similarly, the spin transistor SP2 in the basic unit BU2 changes from the parallel state to the anti-parallel state by, for example, the mechanism shown in FIG.

  Therefore, the logic circuit after the reconfiguration is completed has a structure in which an AND gate and a NOR gate are connected in series as shown in FIG.

  In the reconfiguration of the first embodiment, the spin transistor is changed from the parallel state to the anti-parallel state, but the reverse is also possible. Further, the direction of the spin injection current may be reversed by changing the potential of the power supply terminal N3 to a potential higher than the power supply potential V1 instead of the power supply potential V2.

(2) Second embodiment
FIG. 45 shows the programmable logic circuit of the second embodiment.
In this example, as in the first embodiment, two basic units are connected in series.

  Here, the basic unit BU1 is the logic circuit of FIG. 11, and the basic unit BU2 is the logic circuit of FIG.

  The feature of this programmable logic circuit is that two basic units BU1 and BU2 are connected in parallel between a power supply terminal N1 and a power supply terminal N3, as in the first embodiment.

  Vdd is applied as the power supply potential V1 to the power supply terminals N1 and N3, and Vss (<Vdd) is applied as the power supply potential V2 to the power supply terminal N2. The write signal W is input in common to the basic units BU1 and BU2. There are three input signals A, B, and D, and the output signal is Y (= Vout).

  Note that the write signal W may be provided independently to the basic units BU1 and BU2.

  In the initial state, the spin transistors SN1 and SP2 in the basic units BU1 and BU2 are both in a parallel state. In this case, the logic circuit has a structure in which a NOR gate and an AND gate are connected in series as shown in FIG.

  When the logic is reconfigured, the write signal W is set to “H” to turn on the transistors T11 and T12. The spin injection current flows through the basic units BU1 and BU2 simultaneously along the current path shown in FIG.

  The spin transistor SN1 in the basic unit BU1 changes from the parallel state to the anti-parallel state by the mechanism shown in FIG. 15, for example. Similarly, the spin transistor SP2 in the basic unit BU2 changes from the parallel state to the anti-parallel state by, for example, the mechanism shown in FIG.

  Therefore, the logic circuit after completion of the reconfiguration has a structure in which a NAND gate and an OR gate are connected in series as shown in FIG.

  In the reconfiguration of the second embodiment, the spin transistor is changed from the parallel state to the anti-parallel state, but the reverse is also possible. Further, the direction of the spin injection current may be reversed by changing the potential of the power supply terminal N3 to a potential lower than the power supply potential V2 instead of the power supply potential V1.

(3) Third embodiment
FIG. 47 shows a programmable logic circuit according to the third embodiment.
In this example, as in the first embodiment, two basic units are connected in series.

  Here, the basic unit BU1 is the logic circuit of FIG. 22, and the basic unit BU2 is the logic circuit of FIG.

  The feature of this programmable logic circuit is that two basic units BU1 and BU2 are connected in parallel between a power supply terminal N1 and a power supply terminal N3, as in the first embodiment.

  Vdd is applied as the power supply potential V1 to the power supply terminal N1, and Vss (<Vdd) is applied as the power supply potential V2 to the power supply terminal N2. A power supply potential V3 (V2 <V3 <V1) is applied to the power supply terminal N3. The write signal W is input in common to the basic units BU1 and BU2. There are three input signals A, B, and D, and the output signal is Y (= Vout).

  Note that the write signal W may be provided independently to the basic units BU1 and BU2.

  In the initial state, the spin transistor SN1 in the basic unit BU1 is in the parallel state, and the spin transistor SN2 in the basic unit BU2 is in the anti-parallel state. In this case, the logic circuit has a structure in which an OR gate and a NAND gate are connected in series as shown in FIG.

  When the logic is reconfigured, the write signal W is set to “H” to turn on the transistors T11 and T12. The spin injection current simultaneously flows in the basic units BU1 and BU2 along the current path shown in FIG.

  For example, the spin transistor SN1 in the basic unit BU1 changes from the parallel state to the anti-parallel state by the mechanism shown in FIG. Similarly, the spin transistor SN2 in the basic unit BU2 changes from the anti-parallel state to the parallel state, for example, by the mechanism shown in FIG.

  Therefore, the logic circuit after the reconfiguration is completed has a structure in which an AND gate and a NOR gate are connected in series as shown in FIG.

  In the reconfiguration of the third embodiment, the power supply potential applied to the power supply terminal N3 is V3 (V2 <V3 <V1). Alternatively, the reconfiguration can be performed by switching between V1 and V2.

  In this case, first, the potential of the power supply terminal N3 is set to V2, and a spin injection current is supplied to the spin transistor SN1 in the basic unit BU1. Thereafter, the potential of the power supply terminal N3 is set to V1, and a spin injection current is passed through the spin transistor SN2 in the basic unit BU2. The order in which the spin injection current flows through the basic units BU1 and BU2 may be reversed.

  As a reconfiguration method, a spin injection current is alternately supplied to the basic units BU1 and BU2 until the reconfiguration is completed, and first, one of the basic units BU1 and BU2 is supplied until a desired output signal is obtained. On the other hand, there are two methods: a method in which a spin injection current is supplied and then a spin injection current is supplied to the other of the basic units BU1 and BU2 until the reconfiguration is completed.

(4) Fourth embodiment
FIG. 49 shows a programmable logic circuit according to the fourth embodiment.
In this example, as in the first embodiment, two basic units are connected in series.

  Here, the basic unit BU1 is the logic circuit of FIG. 32, and the basic unit BU2 is the logic circuit of FIG.

  The feature of this programmable logic circuit is that two basic units BU1 and BU2 are connected in parallel between a power supply terminal N1 and a power supply terminal N3, as in the first embodiment.

  Vdd is applied as the power supply potential V1 to the power supply terminal N1, and Vss (<Vdd) is applied as the power supply potential V2 to the power supply terminal N2. A power supply potential V3 (V2 <V3 <V1) is applied to the power supply terminal N3. The write signal W is input in common to the basic units BU1 and BU2. There are three input signals A, B, and D, and the output signal is Y (= Vout).

  Note that the write signal W may be provided independently to the basic units BU1 and BU2.

  In the initial state, the spin transistor SP1 in the basic unit BU1 is in the anti-parallel state, and the spin transistor SP2 in the basic unit BU2 is in the parallel state. In this case, the logic circuit has a structure in which an OR gate and a NAND gate are connected in series as shown in FIG.

  When the logic is reconfigured, the write signal W is set to “H” to turn on the transistors T11 and T12. The spin injection current simultaneously flows in the basic units BU1 and BU2 along the current path shown in FIG.

  The spin transistor SP1 in the basic unit BU1 changes from the anti-parallel state to the parallel state, for example, by the mechanism shown in FIG. Similarly, the spin transistor SP2 in the basic unit BU2 changes from the parallel state to the anti-parallel state by, for example, the mechanism shown in FIG.

  Therefore, the logic circuit after completion of the reconfiguration has a structure in which an AND gate and a NOR gate are connected in series as shown in FIG.

  Also in the reconfiguration of the fourth embodiment, the power supply potential applied to the power supply terminal N3 is V3 (V2 <V3 <V1), but instead, V1 and V2 can be switched for reconfiguration.

  In this case, first, the potential of the power supply terminal N3 is set to V1, and a spin injection current is supplied to the spin transistor SP1 in the basic unit BU1. Thereafter, the potential of the power supply terminal N3 is set to V2, and a spin injection current is passed through the spin transistor SP2 in the basic unit BU2. The order in which the spin injection current flows through the basic units BU1 and BU2 may be reversed.

  As the reconstruction method, as described in the third embodiment, a spin output current is alternately supplied to the basic units BU1 and BU2 until the reconstruction is completed. First, a desired output signal is obtained. Until then, the spin injection current is supplied to one of the basic units BU1 and BU2, and then the spin injection current is supplied to the other of the basic units BU1 and BU2 until the reconfiguration is completed. is there.

(5) Other
In the first to fourth embodiments, only the basic units BU1 and BU2 are shown, but a logic circuit can be realized by providing a plurality of pairs of the basic units BU1 and BU2.

5). Application examples
The programmable logic circuit according to the example of the present invention can be a so-called universal logic circuit by combining a plurality of basic units in an array.

FIG. 51 shows an example of a universal logic circuit.
In this example, two input signals A and B and two output signals Y1 and Y2 are used. However, the present invention is not limited to this. The cell corresponds to the basic unit described in the first to fourth embodiments. The write signal W is common to all the cells, and the spin injection current flows from the power supply terminal N1 toward the power supply terminal N2.

  Reconfiguration can be done in a short time by applying input signals A and B and taking out output signals Y1 and Y2 through multiplexers MP1 and MP2 while reconfiguring with spin injection current. Can do.

  In such a universal logic circuit, the states of a plurality of cells cannot be individually controlled. Therefore, the reconfiguration is repeated until the output signals Y1 and Y2 reach desired values during the reconfiguration. Therefore, the reconstruction is finished when a desired output signal is obtained.

  According to such a method, time and labor required for complicated circuit design can be greatly reduced. In addition, even if there is a defect in hardware, it is not necessary to specify a defective cell. From this point, the logic circuit can be reconfigured without extra time and effort.

  FIG. 52 shows a DSP chip.

  The main components of the DSP chip are a digital signal processor (DSP), an ADC (analog-digital converter), and a DAC (digital-analog converter) as digital signal processing units.

  In many cases, the optimal signal differs between the signal from the outside and the signal transmitted to the outside depending on the environment in which the chip is placed. The programmable logic circuit according to the example of the present invention in which the logic circuit can be reconfigured according to the environment in which the individual chip is placed is particularly used for an interface circuit between the ADC and the DSP and between the DSP and the DAC. Convenient.

  Although only a DSP is shown here, the example of the present invention is applicable to all semiconductor integrated circuits that require a logic circuit.

6). Conclusion
According to the example of the present invention, it is possible to realize a programmable logic circuit in which the wiring for reconfiguring the logic circuit is simple and the logic circuit can be easily reconfigured in a short time.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the scope of the invention. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

FIG. 3 is a circuit diagram illustrating a logic circuit according to the first embodiment. FIG. 3 is a circuit diagram illustrating a logic circuit according to the first embodiment. FIG. 3 is a circuit diagram illustrating a logic circuit according to the first embodiment. FIG. 2 is a plan view showing the structure of the logic circuit according to the first embodiment. Sectional drawing which follows the VV line | wire of FIG. The figure which shows the symbol of the logic gate before and behind reconstruction. FIG. 2 is a plan view showing the structure of the logic circuit according to the first embodiment. Sectional drawing which follows the VIII-VIII line of FIG. The figure which shows the symbol of the logic gate before and behind reconstruction. The figure which shows the relationship between Vfg and Vout. A circuit diagram showing a logic circuit of a 2nd embodiment. A circuit diagram showing a logic circuit of a 2nd embodiment. A circuit diagram showing a logic circuit of a 2nd embodiment. The top view which shows the structure of the logic circuit of 2nd Embodiment. Sectional drawing which follows the XV-XV line | wire of FIG. The figure which shows the symbol of the logic gate before and behind reconstruction. The top view which shows the structure of the logic circuit of 2nd Embodiment. Sectional drawing which follows the XVIII-XVIII line | wire of FIG. The figure which shows the symbol of the logic gate before and behind reconstruction. The figure which shows the relationship between Vfg and Vout. A circuit diagram showing a logic circuit of a 3rd embodiment. A circuit diagram showing a logic circuit of a 3rd embodiment. A circuit diagram showing a logic circuit of a 3rd embodiment. The top view which shows the structure of the logic circuit of 3rd Embodiment. FIG. 25 is a sectional view taken along line XXV-XXV in FIG. 24. The figure which shows the symbol of the logic gate before and behind reconstruction. The top view which shows the structure of the logic circuit of 3rd Embodiment. Sectional drawing which follows the XXVIII-XXVIII line | wire of FIG. The figure which shows the symbol of the logic gate before and behind reconstruction. The figure which shows the relationship between Vfg and Vout. A circuit diagram showing a logic circuit of a 4th embodiment. A circuit diagram showing a logic circuit of a 4th embodiment. A circuit diagram showing a logic circuit of a 4th embodiment. The top view which shows the structure of the logic circuit of 4th Embodiment. Sectional drawing which follows the XXXV-XXXV line | wire of FIG. The figure which shows the symbol of the logic gate before and behind reconstruction. The top view which shows the structure of the logic circuit of 4th Embodiment. Sectional drawing which follows the XXXVIII-XXXVIII line of FIG. The figure which shows the symbol of the logic gate before and behind reconstruction. The figure which shows the relationship between Vfg and Vout. The figure which shows the flow of the reconfiguration | reconstruction method of a programmable logic circuit. The figure which shows the example of a programmable logic circuit. 1 is a circuit diagram showing a logic circuit of a first embodiment. The figure which shows the symbol of the logic gate before and behind reconstruction. The circuit diagram which shows the logic circuit of a 2nd Example. The figure which shows the symbol of the logic gate before and behind reconstruction. The circuit diagram which shows the logic circuit of a 3rd Example. The figure which shows the symbol of the logic gate before and behind reconstruction. The circuit diagram which shows the logic circuit of a 4th Example. The figure which shows the symbol of the logic gate before and behind reconstruction. The figure which shows a universal logic circuit. The figure which shows a DSP chip.

Explanation of symbols

  10: Semiconductor substrate, 10a: N-type well region, 10b: P-type well region, 11a, 11b: Tunnel barrier layer, 12a, 12b, 12b ′: Ferromagnetic material, 13: Antiferromagnetic material, 17: Element isolation insulation Layer, FG: floating gate electrode, SP, SN, T1: transistor, N1, N2, N3: power supply terminal.

Claims (13)

A magnetic pinned layer connected between the first power supply node and the output node and having a magnetization direction fixed; and a magnetic recording layer having a changed magnetization direction, wherein the magnetization direction of the magnetic pinned layer and the magnetic recording layer A first transistor whose conductance changes according to a relative relationship with the magnetization direction;
A second transistor connected between a second power supply node and the output node, the conductance of which is set to a value between a maximum value and a minimum value of conductance of the first transistor;
A third transistor and a resistance element connected in series between a third power supply node and the output node;
The first transistor includes a first conductivity type first channel formed when the transistor is turned on, a floating first gate electrode disposed on the first channel, and the first gate electrode. A second gate electrode disposed on top of
The second transistor includes a second channel of a second conductivity type that is formed when the transistor is turned on, and a third channel in a floating state that is disposed on the second channel and connected to the first gate electrode. A gate electrode; and a fourth gate electrode disposed above the third gate electrode;
Furthermore, an input signal is applied to the second and fourth gate electrodes, and a circuit for causing the spin injection current to flow between the first and third power supply nodes and an output signal output to the output node are detected. A programmable logic circuit comprising: a detection unit.   2. The programmable logic circuit according to claim 1, wherein a logic reconfiguration is performed by changing a relative relationship between a magnetization direction of the magnetic pinned layer and a magnetization direction of the magnetic recording layer by the spin injection current.   When the relative relationship between the magnetization direction of the magnetic pinned layer and the magnetization direction of the magnetic recording layer is in a parallel state, the conductance of the first transistor becomes a maximum value, and the magnetization direction of the magnetic pinned layer and the magnetic recording layer 2. The programmable logic circuit according to claim 1, wherein a conductance of the first transistor becomes a minimum value when a relative relationship with a magnetization direction of the first transistor is in an anti-parallel state.   The magnetic pinned layer is disposed on the output node side with respect to the first channel, and the magnetic recording layer is disposed on the first power supply node side with respect to the first channel. The programmable logic circuit according to claim 1.   The magnetic pinned layer is disposed on the first power supply node side with respect to the first channel, and the magnetic recording layer is disposed on the output node side with respect to the first channel. The programmable logic circuit according to claim 1.   The programmable logic circuit according to claim 1, wherein the potential of the third power supply node is the same as the potential of the first or second power supply node.   The programmable logic circuit according to claim 1, wherein the first channel is disposed between the magnetic pinned layer and the magnetic recording layer.   8. The tunnel barrier layer according to claim 7, wherein a tunnel barrier layer is disposed between at least one of the first channel and the magnetic pinned layer and between the first channel and the magnetic recording layer. Programmable logic circuit. In a programmable logic circuit constituted by a combination of a plurality of basic units, each basic unit is
A magnetic pinned layer connected between the first power supply node and the output node and having a magnetization direction fixed; and a magnetic recording layer changing the magnetization direction. A first transistor whose conductance changes according to a relative relationship with the magnetization direction;
A second transistor connected between a second power supply node and the output node, the conductance of which is set to a value between a maximum value and a minimum value of conductance of the first transistor;
A third transistor and a resistance element connected in series between a third power supply node and the output node;
The first transistor includes a first conductivity type first channel formed when the transistor is turned on, a floating first gate electrode disposed on the first channel, and the first gate electrode. A second gate electrode disposed on top of
The second transistor includes a second channel of a second conductivity type that is formed when the transistor is turned on, and a third channel in a floating state that is disposed on the second channel and connected to the first gate electrode. A gate electrode; and a fourth gate electrode disposed above the third gate electrode;
Further, a circuit for causing a spin injection current to flow in parallel between the first and third power supply nodes with respect to the plurality of basic units, a magnetization direction of the magnetic pinned layer, and a magnetization direction of the magnetic recording layer A programmable logic circuit comprising: a circuit for reconfiguring logic by changing a relative relationship.   An output of the programmable logic circuit after applying the spin injection current between the first and third power supply nodes to the plurality of basic units in a state where an input signal is applied to the programmable logic circuit The programmable logic circuit according to claim 9, wherein an output signal output to the node is verified to determine whether or not the logic reconfiguration is completed. The programmable logic circuit of claim 1, wherein
Determining a logic value of an input signal to the programmable logic circuit;
Thereafter, after passing the spin injection current between the first and third power supply nodes, the logic value of the output signal of the programmable logic circuit is verified, and whether or not the logic reconfiguration is completed. A method for reconfiguring a programmable logic circuit, wherein: The programmable logic circuit of claim 9, wherein
Determining a logic value of an input signal to the programmable logic circuit;
Then, after passing the spin injection current between the first and third power supply nodes to the plurality of basic units, the logic value of the output signal of the programmable logic circuit is verified, and the logic A method for reconfiguring a programmable logic circuit, comprising determining whether or not reconfiguration has been completed. The method for reconfiguring a programmable logic circuit according to claim 11 or 12,
When the logical value of the output signal is not accurate, change the condition regarding the spin injection current, and again verify the logical value of the output signal,
When the logical value of the output signal is accurate, change the logical value of the input signal, and again verify the logical value of the output signal,
A method for reconfiguring a programmable logic circuit, wherein the logic reconfiguration is completed when the logic value of the output signal is verified for all combinations of logic values of the input signal.

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