JP4673405B2 - Passive element design program, design apparatus, and design method - Google Patents

Description

  The present invention relates to a design method for passive elements used in electronic circuits, and more particularly to a design method for passive elements used on a semiconductor large-scale integrated circuit.

  Conventionally, in the manufacture of passive elements, for example, passive elements used on large scale integrated circuits (LSIs), there has been a problem that the variation of element values between wafers or factories increases. As a method of dealing with this problem, there has conventionally been a method of dealing with variations in element values by taking a large margin in circuit design. However, in this method, circuit complexity and circuit block area are reduced. There was a problem of increasing.

  As a second method, there is a method of suppressing variation in the value of the element due to variation in size by changing the shape of the element, that is, the length and width, or by changing the number of divisions when the element is divided and manufactured. Although this method is effective to some extent due to variations in size, there is a problem in that it is ineffective to variations in sheet resistance and capacitance per unit area.

  As a third method, there is a method of performing trimming at the factory and pulling back to the center value when the element value deviates from the center value to be designed due to variations. FIG. 1 is an explanatory diagram of this method. In the figure, when creating a layout for creating a 10Ω resistor using a material having a sheet resistance of 1Ω, when the resistance is created with a length L of 10 μm and a width of W = 1 μm, the actual finish is 8Ω, that is, 20 % Resistance is obtained, the target value of 10Ω is obtained by setting the width W to 0.8 μm by trimming during manufacturing. However, the third method requires processing for each chip, and thus has a problem that it takes man-hours and costs.

  In Patent Document 1 as a conventional technique related to a method for manufacturing a resistance element on a semiconductor device, for example, as described above, by combining two or more types of resistance layers having different temperature characteristics, resistance having low temperature characteristics, A method of manufacturing a resistance element having an arbitrary temperature characteristic is disclosed.

  Next, Patent Document 2 discloses a technique for providing a small-sized thin film resistance element having excellent characteristics in which variation in resistance value with respect to temperature is reduced by combining conductive oxide thin films having opposite temperature characteristics. Yes.

However, even these conventional techniques cannot solve the problem that the manufacturing cost is high and, for example, it is impossible to design a passive element that effectively uses the resistance on the LSI.
Japanese Patent Laid-Open No. 6-260303 "Semiconductor Device and Method for Manufacturing the Same" Japanese Patent Laid-Open No. 9-190904 “Thin Film Resistor and Display Device Using Thin Film Resistor”

The object of the present invention is to combine a plurality of passive elements, rather than the elements used in the combination,
Designing one passive element with little variation, that is, error.
The passive element design program of the present invention is a program that is used by a computer that designs a single passive element by combining a plurality of passive elements, and most basically uses a coefficient calculation procedure and an element value determination procedure in the computer. To be executed.

  The coefficient calculation procedure starts with a combination of two passive elements and sequentially calculates the coefficients used for multiplication corresponding to the value of one passive element to be designed in the process of further combining the passive elements one by one. In the element value determination procedure, the values of a plurality of passive elements to be combined are determined using the calculated coefficient.

  Prior to the above-described coefficient calculation procedure, the passive element determination program of the present invention further causes a computer to execute a list-up procedure for listing passive elements to be combined in ascending order of manufacturing error. The above-described coefficients in the process of combining are calculated in the order of priority of small passive elements.

  The passive element design apparatus of the present invention is an apparatus for designing one passive element by combining a plurality of passive elements by executing the passive element design program of the present invention, for example, a CAD apparatus, and the passive element design method of the present invention. These are passive element design methods corresponding to the passive element design program of the present invention.

  As described above, in the present invention, when designing a passive element by combining a plurality of passive elements, the passive elements to be combined are listed in ascending order of manufacturing error, and the passive elements having the lowest manufacturing error are given priority in order. Compared with the case where only one passive element is used by calculating the coefficient value in the process of combination and calculating the coefficient so as to suppress the error of one passive element to be designed. It becomes possible to reduce the error of the element.

It is explanatory drawing of the trimming as a prior art corresponding to the dispersion | variation in the value of an element. It is a fundamental functional block diagram of the passive element design program of this invention. It is explanatory drawing of the resistance element as a combination candidate corresponding to the resistance element which should be designed in this embodiment. It is explanatory drawing of the capacitive element as a combination candidate corresponding to the capacitive element which should be designed in this embodiment. It is a detailed flowchart of the element design process in this embodiment. It is explanatory drawing of the element combination example in this embodiment. It is a figure explaining the loading to the computer of the program in this invention.

  FIG. 2 is a principle functional block diagram of the passive element design program of the present invention. This program is a program used to design one passive element with few errors by combining a plurality of passive elements.

  In FIG. 2, first, in step S1, a procedure for listing a plurality of passive elements to be combined in the order of small manufacturing error, that is, manufacturing variation, is executed, and then in step S2, starting from a combination of two passive elements, In the process of further combining the passive elements one by one in the order of priority of the small passive elements, a coefficient calculation procedure for sequentially calculating coefficients used for multiplication corresponding to the value of one passive element to be designed is executed. An element value determination procedure for determining values of a plurality of passive elements to be combined is executed using the coefficients calculated in step S3.

  FIG. 3 is a diagram showing resistance elements that are combination candidates in designing a resistance element as one passive element on a large scale integrated circuit (LSI). In this embodiment, when designing a single passive element, by combining a plurality of passive elements connected in series or in parallel, an element with less error, that is, manufacturing variation than using a single element can be designed. Done.

  In this design, a plurality of passive elements to be combined, that is, resistance elements in FIG. In other words, as the resistance elements, elements such as wiring resistance and poly resistance, which are mutually different, that is, have no correlation in error factors are combined. For example, since it is considered that there is a correlation between a poly resistance and a silicide poly resistance having characteristics closer to metal than a general poly resistance, a factor of manufacturing error, that is, manufacturing variation, No combination is used.

  FIG. 4 is an explanatory diagram of a capacitive element on an LSI that is a combination candidate for designing one capacitive element. Among these capacitors, a plurality of elements having no correlation between factors of manufacturing variations, that is, errors are selected, and one capacitor element is designed by connecting these elements in parallel or in series. In FIG. 4, the electrode of MIM (Metal Insulator Metal) is disposed at the top, but this electrode is not always disposed at the top. The STI (Shallow Trench Isolation) capacitance is a capacitance of a thick insulating film inserted by forming a groove between two elements, but details of these capacitances are not directly related to the present invention. Therefore, detailed description is omitted.

  Next, in the present embodiment, a resistive element or a capacitive element is connected in series or in parallel, and a single resistive element or capacitive element having a smaller variation than that using a single element is designed. However, in this design, starting from the combination of two elements, in the process of increasing the number of elements to be combined one by one, the elements to be combined so that the variation as a whole combination, that is, the error becomes as small as possible. A coefficient for calculating the value of the value is obtained, and the value of the element to be combined is determined by using the coefficient. The details of the determination method will be described below by distinguishing when the elements are combined in series or in parallel. explain.

First, a case where resistance elements are connected in series or capacitance elements are connected in parallel (the combined element value is the sum of the element values) will be described.
A single error (square) E ² (1) is given by the following equation.

ここで、ｅ_１：１個単体の素子の最大誤差
２個組み合わせた場合の誤差（の２乗）Ｅ^２（２個）は次式で与えられる。

Here, e ₁ : Maximum error of a single element (error 2) E ² (2) when two elements are combined is given by the following equation.

αは１番目の素子（Ａ）に２番目の素子を組み合わせるときに、１番目の素子の値との乗算に用いられる係数であり、その値は１より小さいものとする。各素子の取る値（抵抗値ｏｒ容量値）Ｘｉは次式で与えられる。

α is a coefficient used for multiplication with the value of the first element when the second element is combined with the first element (A), and its value is assumed to be smaller than 1. The value (resistance value or capacitance value) Xi taken by each element is given by the following equation.

X ₁ = αA _1, X ₂ = (1-α) A (1)
Next, in order to obtain α such that (two combination errors) <(single unit error), the difference between the squares of the two is obtained.

ここでｅ_ｎ：ｎ番目の素子の最大誤差
＝（αｅ_１）^２＋（（１−α）ｅ_２）^２−ｅ_１ ^２ ・・・（２）

Here, e _n : Maximum error of the n-th element = (αe ₁ ) ² + ((1−α) e ₂ ) ² −e ₁ ² (2)

となる。最後から２番目の式から

It becomes. From the second expression from the end

のときＥ^２（２個）がＥ^２（１個）よりも小さくなり、また最後の式から

Then E ² (2) is smaller than E ² (1), and from the last equation

でＥ^２（２個）が最小となることがわかる。なお後述するように、ｅ_２＜ｅ_１となる順序で組合せを行うものとする。

It can be seen that E ² (2) is minimized. As will be described later, the combinations are performed in the order of e ₂ <e ₁ .

Next, a case where resistance elements are connected in parallel or capacitive elements are connected in series (the reciprocal of the combined element value becomes the sum of the reciprocal of each element value) will be described.
Error (square) of the reciprocal of a single unit (1 / resistor or 1 / capacity)

(1) is given by the following equation. This formula is a known one and its description is omitted. Where

Means the error of the reciprocal, and in the following, this is represented by the symbol Er.

ここで、ｅ_１：１個単体の最大誤差
２個組み合わせた場合の逆数の誤差（の２乗）Ｅｒ^２（２個）は次式となる。

Here, e ₁ : single unit maximum error When two are combined, the reciprocal error (the square) Er ² (2) is expressed by the following equation.

αは前述と同様の係数（＜１）で、各素子の取る値（抵抗値ｏｒ容量値）Ｘｉは次式で与えられる。

α is the same coefficient (<1) as described above, and the value (resistance value or capacitance value) Xi of each element is given by the following equation.

次に（２個の組合せ誤差）＜（１個単体の誤差）となるαを求めると、

Next, when α is obtained such that (two combination errors) <(single unit error),

よって

Therefore

のときＥｒ^２（２個）がＥｒ^２（１個）よりも小さくなる。また、この式はαについての２つの１次因数を含んでおり、この式を零とおいた方程式の２つの根の和の１／２はこの２次関数が最小となるαを与える。その値は

In this case, Er ² (2 pieces) is smaller than Er ² (1 piece). This equation also includes two first-order factors for α, and ½ of the sum of the two roots of the equation with this equation set to zero gives α that minimizes this quadratic function. Its value is

であり、Ｅｒ^２（１個）の値が一定であることから、このときＥｒ^２（２個）が最小となることがわかる。

Since the value of Er ² (1 piece) is constant, it can be seen that Er ² (2 pieces) is minimized.

  Finally, the conversion from the reciprocal error to the original error is calculated by the following equation. Here, the original error E (two) corresponds to an error of the entire impedance (resistance value) when two resistance elements are connected in parallel, for example. Note that this conversion formula is also known and will not be described.

以上においては素子を２個組み合わせる場合の誤差や、素子のとるべき値について説明した。前述のように本実施形態では、組み合わせる素子の個数を１個ずつ増加させていく過程で、組合せ誤差を減少させるように、各素子のとるべき値を決定するための係数、例えば（１）式におけるαの値が求められる。

In the above, the error when combining two elements and the value to be taken of the element have been described. As described above, in this embodiment, in the process of increasing the number of elements to be combined one by one, a coefficient for determining a value to be taken for each element so as to reduce the combination error, for example, Equation (1) The value of α at is determined.

In the following description, the value of the coefficient used to determine the element value when combining the i-th element will be represented by α _i . When i = 1, there is no meaning as a combination, and the coefficient α ₁ does not exist. For example, α in the equation (1) corresponding to the case where two resistance elements are connected in series is α ₂ . For example, when designing a resistance element with A = 10 [Ω] as a whole, if, for example, α ₂ = 0.2, then X ₁ = 0.2 × 10 = 2 [Ω], X ₂ = 0.8 × 10 = 8 [Ω]
Is required.

Next, when the third element is further connected in series, the coefficient α ₃ corresponds to the equation (4).

を満足するように決定される。ここでＥ_２ ^２は２個の組合せに対する誤差の２乗であり、Ｅ^２（２個）と同じである。

To be satisfied. Here, E ₂ ² is the square of the error for the two combinations, and is the same as E ² (2).

Rewriting equation (2) corresponding to E ₃ ² = E ² (3) and E ₂ ² = E ² (2),
E ₃ ² = (α ₃ E ₂ ) ² + {(1-α ₃ ) e ₃ } ²
The value of the element is expressed by the following equation using α ₃ .

X ₁ = α ₂ α ₃ A, X ₂ = (1-α ₂ ) α ₃ A, X ₃ = (1-α ₃ ) A
Generalizing the above equation when the i-th resistance element is connected in series, the range of the coefficient α _i is

によって決定され、このとき
Ｅ_ｉ ^２＝（α_ｉＥ_ｉ−１）^２＋｛（１−α_ｉ）ｅ_ｉ｝^２ ・・・（９）
が成立し、素子の値は
Ｘ_１＝α_２α_３・・・α_ｉＡ、Ｘ_２＝（１−α_２）α_３・・・α_ｉＡ、・・・、
Ｘ_ｉ−１＝（１−α_ｉ−１）α_ｉＡ、Ｘ_ｉ＝（１−α_ｉ）Ａ ・・・（１０）
によって決定される。なおここでＥ_ｉ−１は（ｉ−１）個の素子の組合せに対する誤差を示すのみであり、その組合せはすべて直列であるとは限らない。

Where E _i ² = (α _i E _i−1 ) ² + {(1−α _i ) e _i } ² (9)
And the element values are X ₁ = α ₂ α ₃ ... Α _i A, X ₂ = (1−α ₂ ) α ₃ ... Α _i A,.
X _i-1 = (1-α _i-1 ) α _i A, X _i = (1-α _i ) A (10)
Determined by. Here, E _i-1 only indicates an error with respect to the combination of (i-1) elements, and all the combinations are not necessarily in series.

  Similarly, the error range corresponds to equation (6) when the i-th resistance element is connected in parallel.

となる。また（７）式に対応して、ｉ番目の素子までの組合せに対する誤差は

It becomes. Corresponding to equation (7), the error for the combination up to the i-th element is

で与えられ、さらに素子の値は次式によって決定される。

Further, the element value is determined by the following equation.

X ₁ = A / α ₂ α ₃ ... Α _i , X ₂ = A / (1-α ₂ ) α ₃ ... Α _i ,.
X _i-1 = A / (1-α _i-1 ) α _i , X _i = A / (1-α _i ) (13)
Based on the above description, the passive element design process in the present embodiment will be further described. FIG. 5 is a detailed flowchart of the passive element design process. When processing is started in the figure, first, in step S10, N elements that are not correlated with each other are listed, and in step S11, the N elements are listed, that is, sorted in ascending order of variation. The value of error E ₁ corresponding to only a single element is set equal to the error e _{1 of} that element, and the value of i is set to “2”. The reason why the sorting is performed in ascending order of variation is to start with the element having the smallest variation, that is, the smallest error, and sequentially combine other elements in the order of the smallest error.

Subsequently, in step S12, it is determined whether the i-th element, here the second element, is connected in series if it is a resistive element, or in parallel if it is a capacitive element. In such a case, the value of the coefficient α _i is determined in the range of the equation (8) in step S13, and the error up to the i-th combination is determined in step S14 according to the equation (9). Then, it is determined whether or not the number i of elements combined in step S15 has reached the number N listed in step S10. If not, the value of i is incremented in step S16. The processing after S12 is continued.

If it is determined in step S12 that the resistor element is connected in parallel and the capacitor element is connected in series, the value of the coefficient α _i is determined in step S17 within the range of the equation (11), and the i-th element is determined in step S18. The error for the combinations up to is obtained according to the equation (12), and the process proceeds to step S15.

If it is determined in step S15 that the number i of the combined elements has reached N, the values of the elements are determined by the processes in steps S20 to S25. First, in step S20, the number j of elements to be combined corresponding to the value of i described above is set to “2”. In step S21, if the jth element is a resistance element, it is in series, and if it is a capacitance element, it is It is determined whether or not to connect, and if so, the values of up to j elements are calculated in step S22. Here, j = 2, and the values of X ₁ and X ₂ are determined, but the values are the same as in the equation (1). Then, it is determined whether or not the number j of elements combined in step S23 has reached N. If it has not yet reached, the value of j is incremented in step S24, and the processing after step S21 is continued.

  If the j-th element is a resistance element in step S21 and the capacitor element is connected in series, the value of each element is determined in step S25 corresponding to equation (13). If it is determined that the number j of elements combined in step S23 has reached N, the process is terminated.

For example, when all N elements are connected in series, the range of the coefficient α _i is sequentially determined in step S13, and the square of the error for the combination up to the i-th element is calculated in step S14. Is obtained in step S22. In step S22, the value of _{X 1} and _{X 2} are determined in the case of j = 2, as described above, j is incremented and its value is _"3", with respect to X 1, _{X 2} Is further multiplied by a coefficient α ₃ and X ₃ is determined by (1−α ₃ ) A. By repeating such a process, the value of each element shown in the equation (10) is sequentially determined.

A specific element design example in the present embodiment will be described below. FIG. 6 is an explanatory diagram in the case where three resistance elements are connected in series to create one resistance value A as a whole. FIG. 2A shows an application example of the present invention. Here, it is assumed that errors of three elements to be combined are 10%, 20%, and 30%, respectively. When the value of the coefficient is determined using the above formula, α ₂ is 0.8 and α ₃ is 0.918367, and the value of each resistor is R ₁ = 0.734694 A R ₂ = 0. 183673A R ₃ = 0.081633A
It becomes. Total error, i.e. to calculate the _{E 3,} the value is 0.085714. That is, the overall error of 8.57% is smaller than 10% with the smallest error among the three elements.

FIG. 6B shows a case where the values of the three resistors are all the same without applying the present invention. In this case, the total error, i.e. the value of _{E 3} becomes 0.124722. That is, the total error of 12.47% is larger than the minimum error of the three elements to be combined.

  A similar design can naturally be realized for the capacitive element. For example, when four elements of a capacitor 1 with an error of 5%, a capacitor 2 with an error of 10%, a capacitor 3 with an error of 15%, and a capacitor 4 with an error of 20% are combined in parallel to create a 10 pF capacitor, The capacitance values calculated by the flowchart of FIG. 5 are 7.02 pF for the capacitance 1, 1.76 pF for the capacitance 2, 0.78 pF for the capacitance 3, and 0.44 pF for the capacitance 4. The error for the whole of all four elements connected in parallel is calculated by the following equation.

このように４つの容量素子を組み合わせることによって、全体の誤差、すなわちばらつきは３．６５％となり、４つの素子に対する誤差の最小値５％よりも低く抑えることが可能となる。

By combining the four capacitive elements in this way, the overall error, that is, the variation is 3.65%, and can be suppressed to be lower than the minimum value of 5% for the four elements.

  Although the details of the passive element design method and design program of the present invention have been described above, such a passive element design apparatus can naturally be realized by a CAD apparatus based on a general computer system. . FIG. 7 is a block diagram showing the configuration of such a computer system, that is, a hardware environment.

  In FIG. 7, the computer system includes a central processing unit (CPU) 10, a read only memory (ROM) 11, a random access memory (RAM) 12, a communication interface 13, a storage device 14, an input / output device 15, and a portable storage. A medium reader 16 and a bus 17 to which all of them are connected are constituted.

  Various types of storage devices such as a hard disk and a magnetic disk can be used as the storage device 14, and the program shown in the flowchart of FIG. The programs of claims 1 to 7 in the range are stored, and such a program is executed by the CPU 10, so that it is possible to design a passive element that can reduce the combination error in the present embodiment.

  Such a program can be stored in the storage device 14 from the program provider 18 via the network 19 and the communication interface 13, for example, or stored in a portable storage medium 20 that is commercially available and distributed, It can also be set in the reader 16 and executed by the CPU 10. As the portable storage medium 20, various types of storage media such as a CD-ROM, a flexible disk, an optical disk, a magneto-optical disk, and a DVD can be used, and a program stored in such a storage medium is read by the reader 16. By reading, the passive element in this embodiment can be designed.

  As described above in detail, in this embodiment, in order to suppress an error of a designed element without incurring an extra cost, the element creation method can be used without depending on the process technology. . At this time, it is possible to design a higher performance element, that is, an element with a smaller error, by combining a higher performance element, that is, an element with less error, and a lower performance element, that is, an element with larger error. . As a combination method, either serial or parallel can be selected, and elements on the integrated circuit can be easily combined.

  As a result, the area of the circuit for compensating for variations, that is, errors, and power consumption can be reduced, and the design period can be shortened and the device yield can be improved by simplifying the circuit. The variation of on-wafer elements is becoming more severe in the future, and the technology of the present invention that can design passive elements with small errors while reducing the cost by reducing the processing such as trimming will contribute to future LSI development. However, it is expected to be big.

Claims (10)

In a program for designing passive elements,
A coefficient calculation procedure for obtaining a coefficient corresponding to the value of one passive element when adding one passive element to a combination of two or more passive elements;
A passive element design program for causing a computer to execute an element value determination procedure for obtaining values of a plurality of combined passive elements using the coefficient. Prior to the coefficient calculation procedure,
Let the computer execute a list-up procedure that lists the passive elements to be combined in ascending order of manufacturing error,
2. The passive element design program according to claim 1, wherein in the coefficient calculation procedure, the coefficient in the process of adding passive elements in the order of giving priority to passive elements having a small manufacturing error is calculated. 3. The passive element design program according to claim 2, wherein in the list-up procedure, passive elements having no correlation in manufacturing variation are listed. In the coefficient calculation procedure, when a combination of two or more passive elements and one passive element are added, different coefficients are calculated depending on whether the combination is a serial combination or a parallel combination. ,
2. The passive element design program according to claim 1, wherein in the element value determination procedure, different calculation formulas are used corresponding to the serial combination or the parallel combination. 2. The passive element design program according to claim 1, wherein, in the coefficient calculation procedure, the coefficient is calculated so as to suppress an error of the passive element to be designed. 2. The passive element design program according to claim 1, wherein the combined passive element is an element in a semiconductor integrated circuit, and the designed passive element is used in the semiconductor integrated circuit. The passive element design program according to claim 1, wherein the passive element is a resistance element or a capacitance element. In a storage medium used by a computer that designs passive elements,
A coefficient calculation step for obtaining a coefficient corresponding to the value of one passive element when adding one passive element to a combination of two or more passive elements;
A computer-readable portable storage medium storing a passive element design program for causing a computer to execute an element value determining step for obtaining values of a plurality of combined passive elements using the coefficient. In a device for designing passive elements,
Coefficient calculating means for obtaining a coefficient corresponding to the value of one passive element when adding one passive element to a combination of two or more passive elements;
A passive element design apparatus comprising element value determining means for obtaining values of a plurality of combined passive elements using the coefficient. In designing a passive element,
When one passive element is added to a combination of two or more passive elements, a coefficient corresponding to the value of the one passive element is obtained.
A passive element design method characterized by obtaining values of a plurality of combined passive elements using the coefficient.

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