JP4669264B2 - Solid-state imaging device and camera using the same - Google Patents

Description

  The present invention relates to a solid-state imaging device that converts a charge into a voltage by a two-dimensionally arranged pixel and reads it as a voltage signal.

  In recent years, digital single-lens reflex cameras have increased their demand, and sensors used therein tend to be as large as 35 mm film size from APS-C size. There are also a wide variety of sensors used, such as CCDs and APS (Active Pixel Sensor). The present invention relates to a solid-state imaging device that converts a charge into a voltage for each pixel and reads it out as a voltage signal, particularly APS.

  FIG. 8 is an example of an equivalent circuit diagram of a pixel in the prior art which is also applied to the present invention. Such pixels are arranged two-dimensionally.

  A node corresponding to the drain of Q3 (terminal connected to the gate of Q1) in the drawing is referred to as FD (floating diffusion). Although not shown, a load such as a constant current source is connected to the vertical output line, and the voltage of the FD is output to the vertical output line through Q1 and Q4.

  FIG. 9 is a schematic layout diagram of a pixel in the prior art.

9, the PD in the photodiode portion 8, the TX section and the FD unit Q3, although amplifying unit Q2 indicating the Q1, Q4 are arranged, not specifically illustrated in FIG.

Also, FIG. 8, for example the following Patent Document 1, the transfer control line 43 with respect to the photodiode 44 as a photoelectric conversion unit, an active pixel sensor is arranged on the same side as the amplifier section 49 is disclosed.
JP 2000-58809 A

  FIG. 10 shows an example of timing when a signal is read out from a pixel in the prior art, which is also applied to the present invention.

This is a method of reading in line units, which will be described in detail below.
(1) A row is selected, Q2 is turned OFF, and the FD is brought into a floating state. The voltage of the FD is output to the vertical output line with Q1 as the source MOS driver MOS.
(2) The voltage at this time is sampled and held in a memory or the like. In “N reading” in FIG. 10, a noise signal is read.
(3) Turn on Q3 to transfer the signal from the photodiode to the FD. A signal obtained by superimposing the optical signal from the photodiode on the noise signal described above appears as the voltage of the FD.
(4) The voltage of the FD at this time is read again through Q1 which is a driver MOS of the follower. This corresponds to “S reading” in FIG.
A good signal can be obtained by subtracting the signal (2) from the signal (4).

  However, in the conventional pixel portion shown in FIG. 9, a plurality of wirings are interlaced, and the potential of the FD changes due to the fluctuation of the wirings.

  As a result of studies, the present inventors have found that the TX line and the output line of the adjacent pixel greatly deteriorate the characteristics.

  That is, in the pixel arrangement according to the conventional technique, Cp1 (capacity between the transfer control line and FD) and Cp2 (capacity between the adjacent pixel output line and FD) shown in FIG. 9 are large, and the output of the transfer control line and the adjacent pixel is large. Due to the influence of the line, the voltage of the FD is changed through the capacitance.

  The transfer control line will be specifically described.

If the capacitance of the FD is CFD, the amount of fluctuation of the potential of the FD is expressed by Cp1 / (Cp1 + Cp2 + CFD) × ΔVtx. ΔVtx is a voltage fluctuation amount of the transfer control line. The reason why the transfer control line is important with respect to the selection line and the reset control line will be described below.
1. At the timing of FIG. 10, the pulse that changes between “N reading” and “S reading” is only the transfer control line.
As shown in FIG. 10, the vertical output line fluctuates as the transfer control line is turned on and off. This variation is caused by the FD sagging through the capacitor Cp1, and when Cp1 is large, the amount of sagging increases. As a matter of course, in the dark output, it is necessary to return to the level of “N reading” at the time of “S reading”. These deteriorate the shading characteristics in the dark. In addition, a certain amount of time is required until the output of the vertical line is stabilized, resulting in a delay in readout time, which causes deterioration of continuous shooting performance in a digital camera or the like.
2. In order to suppress the dark output of the pixel portion, the LOW level may be set lower than GND.
The power source that supplies this LOW level uses a power source of a charge pump system in the system, and the stability (sink capability, source capability) of the power source may be inferior. That is, control line fluctuations often increase due to fluctuations caused by the power source.

  As a result, fluctuations in the control line appear in the image, and a defective image such as a horizontal band-like unevenness occurs in the digital camera.

  The output lines of adjacent pixels will be specifically described.

Assuming that the capacitance of the FD is CFD, the fluctuation amount of the potential of the FD is expressed by Cp2 / (Cp1 + Cp2 + CFD) × ΔVn + 1. ΔVn + 1 is an output value of an adjacent pixel. When these solid-state imaging devices are used as sensors for general digital cameras, adjacent pixels output signals of different colors.

  As a result, the pixel output fluctuates due to the output of adjacent pixels, that is, a problem of color mixing occurs.

In view of the above-described problems, the present invention provides a photoelectric conversion unit that converts light into an electrical signal, a charge-voltage conversion unit that converts the photoelectrically converted optical signal into a voltage signal, and a source follower MOS for reading out the voltage signal. A transistor , a control unit for controlling transfer of an optical signal from the photoelectric conversion unit to the charge voltage conversion unit, and a connection wiring that connects the charge voltage conversion unit and the gate of the source follower MOS transistor. A plurality of pixels, and a plurality of control lines for controlling the control means for the plurality of pixels arranged adjacent to each other in the first direction, and a plurality of pixels arranged adjacent to each other in the second direction a plurality having a solid-state imaging device an output line to which a signal is read from, the control line, when doing the transfer of the optical signal to the charge-voltage converter in a predetermined control line, the predetermined Control line adjacent to the control line has a behavior not transfer the optical signal to the charge-voltage converter, a control line for controlling the control means included in the first pixel, the first pixel The source follower MOS transistor included is disposed on the opposite side of the photoelectric conversion unit included in the first pixel, and includes the connection wiring included in the first pixel, the first pixel, and the first pixel. The distance from the output line from which the signal from the second pixel adjacent in the direction of 1 is output is that the signal from the connection line included in the first pixel and the first pixel is output. It is longer than the distance to the output line.

  In particular, it is possible to provide a solid-state imaging device having a high S / N characteristic in an active solid-state imaging device having a large imaging area (for example, film size). Furthermore, a solid-state imaging device with high performance can be provided by shading or the like. Furthermore, it is possible to provide a solid-state imaging device with a short readout time and high continuous shooting performance.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an arrangement of the most characteristic pixels of the present invention.
The first feature is the arrangement of transfer control lines. The transfer control line is a wiring connected to the gate (TX) of Q3 in FIG. FIG. 2 shows a schematic layout diagram. Q1~Q4 hits the gate electrode of the transistor of FIG.

  As shown in FIG. 2, the vertical output line of its own pixel is adjacent to the wiring from FD to Q1. Especially in this case, there is also an intersection. In the prior art, for example, the vertical output lines of adjacent pixels are arranged adjacent to each other, and the signal of the adjacent pixels is mixed by several percent. In the present invention, the FD can be shielded by its own vertical output line by adjoining the FD and the wiring connected thereto with the vertical output line of its own pixel rather than the vertical output line of the adjacent pixel.

Further, when capacitively coupled to a vertical output line of an adjacent pixel, the capacitance becomes a stray capacitance of the FD portion. As a result, the charge conversion efficiency in the FD portion is reduced. This is likely to be affected by noise generated in the subsequent readout circuit including the source follower portion of the pixel portion, resulting in degradation of S / N characteristics. On the other hand, even if capacitively coupled to the output line of its own pixel, not all the capacitance becomes the stray capacitance of the FD portion. Specifically, if the shift coefficient of the threshold voltage due to the substrate bias effect of the pixel portion source follower MOS is β (the amount of change in the threshold voltage with respect to the substrate bias of 1 volt), the capacitance increases only by β times . In general, β is 1 or less, specifically about 0.3. Therefore, at most, only about 1/3 of the coupled capacity is substantially increased. This is to suppress the stray capacitance of the FD, and has an effect of improving the S / N characteristic.

FIG. 3 is an example in which GND wirings are adjacent to each other in addition to FIG.
By taking such an arrangement, a GND wiring serving as a shield is arranged between the output lines of adjacent pixels.
As a result, signal mixing from the vertical output line of the adjacent pixel can be further suppressed.

In addition, by disposing the control line of the transfer switch on the side opposite to the source follower MOS of the pixel portion with the photodiode interposed therebetween, it is possible to reduce the capacitive coupling from the FD to the Q1 gate.

  According to the prior art, a voltage of about 10% FD is applied to the amplitude of the control line of the transfer switch.

  That is, when the control line is changed from 0 volt to 5 volt, the FD voltage is changed to about 500 mV on the higher side. When this variation is large, “S reading” cannot be performed until the variation is suppressed. As a result, the readout time becomes long, and the continuous shooting performance deteriorates in the digital camera.

  According to the layout of the present invention, the capacitive coupling with the control line of the transfer switch of its own pixel is reduced, but the capacitive coupling with the control line of the transfer switch in the adjacent row is increased. However, in the row being read, the control line of the transfer switch in the adjacent row maintains the LOW level during the period, so that the potential of the FD does not fluctuate.

  In addition, the present invention has an effect of improving S / N characteristics. Since the amplification unit is a source follower using a MOS transistor, 1 / f noise has a large ratio. However, if the time until “S reading” is long, the 1 / f noise increases and the S / N characteristics deteriorate. . On the other hand, when “S reading” is performed before the fluctuations are subsided, characteristics such as shading deteriorate. According to the present invention, the reading time can be shortened without deteriorating shading characteristics and the like. As a result, a sensor having high continuous shooting performance and excellent S / N characteristics can be provided.

(First embodiment)
The present embodiment will be described with reference to FIG.

  FIG. 2 is a schematic layout diagram of this embodiment. Q1 to Q4 correspond to the gate electrodes of the transistor of FIG.

  As shown in FIG. 2, the vertical output line of the same pixel is adjacent to the wiring from FD to Q1. Especially in this case, there is also an intersection. A feature of this embodiment is that MOS transistors including a source follower are arranged in the horizontal direction (the same direction as the control line). In this case, the control line of the transfer switch is arranged on the side opposite to the side where the source follower MOS is arranged with the photodiode interposed therebetween. In the prior art, as described above, when the control line and the FD are capacitively coupled, many characteristic deteriorations occur. This coupling capacity consists of several components. (1) Overlap capacitance between the diffusion region of Q3 and the FD, (2) Since Q1 from the FD portion is generally connected by wiring, the capacitance between the wires, (3) Diffusion region of the control wiring and the FD portion Capacity. The feature of the present invention is to particularly reduce (2). In addition, as a tendency, the component (3) is also reduced. According to the present embodiment, the wiring can be separated from the wiring connecting the gate of FD and Q1.

  As a result, the rate of change in fullerage = FD potential / control line change greatly improved from 10% to 4%.

  The fluctuation amount of the vertical output line is reduced by 0.4 times with the fluctuation of the TX pulse shown in FIG. Thus, the time until “S reading” could be shortened.

  At the same time, the vertical output line was adjacent to and intersected with the wiring connecting FD and Q1, thereby reducing the coupling capacity with other lines.

As a result, the FD capacity can be reduced by about 10% compared to the conventional case, and the S / N characteristics can be improved by about 10.
In addition, the color mixture that has been nearly 10% can be improved to about 2%.

(Second Embodiment)
This embodiment will be described with reference to FIG. FIG. 3 is a schematic layout diagram of this embodiment.

  With respect to the first embodiment, the GND line is arranged in the vertical direction and between the FD portion and the wiring connecting the FD and Q1 and the vertical output line of the adjacent pixel.

  As a result, compared with the example, the FD capacity slightly increased and the color mixture was reduced to 1% or less.

  In addition, improvements in characteristics such as shortening the time to “S reading” were able to obtain the same effects as in Example 1.

(Third embodiment)
The present embodiment will be described with reference to FIG. FIG. 4 is a schematic layout diagram of this embodiment.

  A feature of this embodiment is that MOS transistors including a source follower are arranged in the vertical direction (the same direction as the control line).

  Another feature is that the wiring connecting FD and Q1 is arranged to be short.

  Even in such an arrangement, when the control line of the transfer switch is arranged immediately above the FD portion and immediately above the Q3 gate, that is, when the conventional technique is used, the fulleret ratio = the amount of change in the FD potential / control. The amount of line change is about 6%.

In this case as well, the control line of the transfer switch is arranged on the opposite side of the source follower MOS transistor from the photodiode. More specifically, the control line of the transfer switch is at the top, particularly Q1 / G, with respect to the center of the photodiode, but the FD and its wiring in question are located at the bottom. By doing so, the coupling capacity between the control line and the FD portion could be minimized.

  As a result, the rate of fullerage = FD potential change / control line change was reduced to 2%.

  The vertical output line of its own pixel is arranged in the vicinity of the wiring connecting FD and Q1. Further, it is better to extend the control line of the transfer switch like a dotted line between the vertical output lines of adjacent pixels. When extended, this control line exerts a shielding effect on the vertical output line, thus further improving color mixing. As a result, the color mixture was reduced to 1% or less.

(Fourth embodiment)
This embodiment will be described with reference to FIG. FIG. 5 is a schematic layout diagram of this embodiment.

In this case, the source follower MOS transistor and the reset portion MOS transistor are separated from each other. Even in such a case, the same effect as in the third embodiment can be obtained.

(Fifth embodiment)
This embodiment will be described with reference to FIG. FIG. 6 is a schematic layout diagram of this embodiment.

  FIG. 7 is an equivalent circuit diagram of the present embodiment, which is an example having one amplifying unit for two photodiodes, and this is a feature of the present embodiment. In the present embodiment, the control line 1 is arranged at a position farthest from the source follower portion with the photodiode 1 and the photodiode 2 interposed therebetween. The control line 2 is also arranged on the opposite side of the source follower portion with the photodiode 2 interposed therebetween. In addition, the coupling capacitance with the control line 1 and the coupling capacitance with the control line 2 are generally matched to the connection to the gates of FD1, FD2, and SFMOS (FIG. 7). As a result, the amount of FD flare when reading a signal from the photodiode 1 is equal to the amount of FD flare when reading a signal from the photodiode 2.

  As a result, the characteristics such as shading of the row corresponding to the photodiode 1 and the row corresponding to the photodiode 2 coincided.

  According to the prior art, for example, when the control line 2 is arranged between the source follower unit and the photodiode 2, the amount of FD flare when the control line 2 is read increases, and only the row of the photodiode 2 is characteristic. Deterioration occurs.

  As a result, an image like a horizontal stripe was obtained. In order to solve this problem, a long “S reading” time was taken, but although it improved, a weak streak remained. By adopting the arrangement as in the present embodiment, the objectivity is improved, and such a phenomenon is eliminated.

In addition, color mixture was suppressed by drawing the vertical output line to the FD side.
As a result, good characteristics with a color mixture of 1% or less were obtained.

  In this embodiment, one source follower is provided for every two photodiodes. However, the same effect as in this embodiment can be obtained with three or more photodiodes based on the same concept.

  Next, an example in which the solid-state imaging device according to the first to fifth embodiments of the present invention is applied to a still video camera will be described in detail with reference to FIG.

  FIG. 11 is a block diagram showing a case where the solid-state imaging device of the present invention is applied to a still video camera.

  In FIG. 11, 10 is a barrier that serves as a lens protect and a main switch, 20 is a lens that forms an optical image of a subject on the solid-state imaging device 40, 30 is a stop for changing the amount of light passing through the lens 20, and 40 is A solid-state imaging device for capturing an object imaged by the lens 20 as an image signal, 60 an A / D converter that performs analog-digital conversion of an image signal output from the solid-state imaging device 40, and 70 an A / D conversion A signal processing unit 80 performs various corrections on the image data output from the device 60 and compresses the data. 80 is a solid state imaging device 40, an imaging signal processing circuit 50, an A / D converter 60, and a signal processing unit 70. A timing generation unit for outputting a timing signal, 90 is an overall control / arithmetic unit for controlling various operations and the entire still video camera, and 100 is temporarily used for image data. Memory unit 110 for storing, interface unit 110 for recording or reading on a recording medium, 120 a removable recording medium such as a semiconductor memory for recording or reading image data, 130 an external computer or the like An interface unit for communication.

  Next, the operation of the still video camera at the time of shooting in the above configuration will be described.

  When the barrier 10 is opened, the main power supply is turned on, then the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 60 is turned on.

  Then, in order to control the exposure amount, the overall control / arithmetic unit 90 opens the aperture 30, and the signal output from the solid-state imaging device 40 is converted by the A / D converter 60 and then sent to the signal processing unit 70. Entered.

  Based on the data, the exposure calculation is performed by the overall control / calculation unit 90.

  The brightness is determined based on the result of the photometry, and the overall control / calculation unit 90 controls the aperture according to the result.

  Next, based on the signal output from the solid-state imaging device 40, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 90. Thereafter, the lens is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.

  Then, after the in-focus state is confirmed, the main exposure starts.

  When the exposure is completed, the image signal output from the solid-state imaging device 40 is A / D converted by the A / D converter 60, passes through the signal processing unit 70, and is written in the memory unit by the overall control / calculation unit 90.

  Thereafter, the data stored in the memory unit 100 is recorded on a removable recording medium 120 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 90.

  Further, the image processing may be performed by directly inputting to a computer or the like through the external I / F unit 130.

2 is a plan view of a pixel portion that best represents the characteristics of the present invention. FIG. FIG. 2 is a schematic layout diagram of the first embodiment of the present invention. It is a typical layout figure of the 2nd Embodiment of this invention. It is a typical layout figure of the 3rd Embodiment of this invention. It is a typical layout figure of the 4th Embodiment of this invention. It is a typical layout figure of the 5th Embodiment of this invention. It is an equivalent circuit of the pixel of the 5th Embodiment of this invention. It is the equivalent circuit of the pixel of a prior art applied also to this invention. It is a typical layout figure of a prior art. It is a drive timing diagram for reading the signal from a photodiode. It is a block diagram which shows the structural example of a still video camera.

Explanation of symbols

Cp1 Transfer (TX) Capacitance between control line and FD Cp2 Capacitance between output line and FD of adjacent pixel PD Photo diode FD Floating diffusion SF Amplification source follower transistor RES Reset transistor TX Transfer transistor SEL Select transistor VCC Reset Power supply voltage Q1 Gate electrode of amplification transistor Q2 Gate electrode of reset transistor Q3 Gate electrode of transfer transistor Q4 Gate electrode of selection transistor 10 Barrier that serves as both lens protection and main switch 20 Lens 30 Aperture 40 Solid-state imaging device 50 Imaging Signal processing circuit 60 A / D converter 70 Signal processing unit 80 Timing generation unit 90 Overall control / calculation unit 100 Memory unit 110 Interface unit 120 Recording medium 1 0 external I / F unit

Claims (9)

From a photoelectric conversion unit that converts light into an electric signal, a charge-voltage conversion unit for converting the photoelectrically converted optical signal into a voltage signal, a source follower MOS transistor for reading out the voltage signal, and the photoelectric conversion unit A plurality of pixels having control means for controlling transfer of an optical signal to the charge-voltage converter, and a connection wiring connecting the charge-voltage converter and a gate of the source follower MOS transistor ;
A plurality of control lines for controlling the control means of a plurality of pixels arranged adjacent to each other in the first direction;
A solid-state imaging device having a plurality of output lines from which signals from a plurality of pixels arranged adjacent to each other in the second direction are read,
When the optical signal is transferred to the charge / voltage converter in the predetermined control line, the control line adjacent to the predetermined control line has an operation of not transferring the optical signal to the charge / voltage converter. And
A control line for controlling the control means included in the first pixel is arranged on the opposite side of the source follower MOS transistor included in the first pixel with the photoelectric conversion unit included in the first pixel interposed therebetween. And
The distance between the connection wiring included in the first pixel and the output line from which a signal from the second pixel adjacent to the first pixel in the first direction is output. A solid-state imaging device, wherein a distance between the connection wiring included in a pixel and an output line from which a signal from the first pixel is output is longer.   The shield wiring is disposed between the connection wiring included in the first pixel and an output line from which a signal from the second pixel is output. Solid-state imaging device.   The solid-state imaging device according to claim 2, wherein the shield wiring is a ground wiring. The control means includes a transfer MOS transistor,
The solid-state imaging device according to claim 2, wherein the shield wiring is a gate wiring of the transfer MOS transistor . The source follower MOS transistor is shared by the photoelectric conversion unit included in the first pixel and the photoelectric conversion unit of the third pixel adjacent to the first pixel in the second direction. The solid-state imaging device according to claim 1. From a photoelectric conversion unit that converts light into an electric signal, a charge-voltage conversion unit for converting the photoelectrically converted optical signal into a voltage signal, a source follower MOS transistor for reading out the voltage signal, and the photoelectric conversion unit A plurality of pixels having control means for controlling transfer of the optical signal to the charge-voltage converter, and connection wiring connecting the charge-voltage converter and the input of the source follower MOS transistor ;
A plurality of control lines for controlling the control means of a plurality of pixels arranged adjacent to each other in the first direction;
A solid-state imaging device having a plurality of output lines from which signals from a plurality of pixels arranged adjacent to each other in the second direction are read,
Each control line transfers an optical signal to the charge-voltage converter when the optical signal is transferred to the charge-voltage converter on the predetermined control line. Have no action
A control line for controlling the control means included in the first pixel is arranged on the opposite side of the source follower MOS transistor included in the first pixel with the photoelectric conversion unit included in the first pixel interposed therebetween. And
Shield wiring is provided between the connection wiring included in the first pixel and the output line from which a signal from the second pixel adjacent to the first pixel in the first direction is output. A solid-state imaging device characterized by being arranged.   The solid-state imaging device according to claim 6, wherein the shield wiring is a ground wiring. 7. The solid-state imaging device according to claim 6, wherein the control means includes a transfer MOS transistor, and the shield wiring is a gate wiring of the transfer MOS transistor . The solid-state imaging device according to claim 1, a lens for forming an optical image on the solid-state imaging device , and a diaphragm for changing the amount of light passing through the lens. Camera.

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