JP4665544B2 - Amplification type solid-state imaging device - Google Patents

Description

  The present invention relates to an amplifying solid-state imaging device used in home video cameras, digital still cameras, mobile phone cameras, and the like.

  Solid-state imaging devices in which photoelectric conversion elements are arranged are rapidly developing due to their small size, light weight, high reliability, and low power consumption. However, as the density of pixels increases, the amount of signal charge that can be extracted from one pixel decreases, and it becomes difficult to avoid a reduction in the S / N ratio.

  As one means for solving such a problem, an amplification type solid-state imaging device has been proposed, and in recent years, the demand for the device is increasing.

  FIG. 9 is a schematic diagram of an amplification type solid-state imaging device equipped with a conventional CDS (correlated double sampling) circuit (see, for example, Patent Document 1).

  First, the overall configuration will be described. FIG. 9 shows the entire configuration of the chip 120, and unit pixels 121 are two-dimensionally arranged to constitute the light receiving unit 122. The light receiving unit 122 outputs to the CDS circuit side for each row selected by the vertical shift register 129. On the other hand, the CDS circuit includes a clamp capacitor 124, a sampling capacitor 125, and the like, and performs differential processing between a signal component and a noise component.

  The signal subjected to differential processing by the CDS circuit is output to the horizontal signal line 127 when the column selection switch 126 of the column selected by the horizontal shift register 128 is turned ON. The signal on the horizontal signal line 127 is output via the output amplifier 130 and the like.

  Details of the CDS circuit will be described with reference to FIGS. The outline of these structures is described in Patent Document 1 as a clamp-type CDS circuit.

  FIG. 10 is an enlarged view of a portion B in FIG. The CDS circuit includes a sampling switch 131 that connects and separates the unit pixel 121 and the CDS circuit, a clamp capacitor 124 that clamps a signal from the unit pixel, and a clamp power source 132 that sets a terminal voltage of the clamp capacitor to a reference potential. And a clamp switch 133, and a sampling capacitor 125 for holding a differential voltage from the reference potential.

  FIG. 11 is a timing chart for explaining the operation of the clamp type CDS circuit. The CDS operation is performed in an operation period of only pixels called a horizontal blanking period. First, the sampling switch 131 is turned on so that a signal from the unit pixel can be transferred. At this time, the pixel has already been exposed. Therefore, at that time, the clamp switch 133 is turned ON, and the clamp voltage is held in the sampling capacitor 125 as a reference voltage. Next, simultaneously with turning off the clamp switch 133, the reset transistor 135 in the unit pixel is turned on, and a pixel signal (noise component) in a state where it is not exposed is read out. As a result, the output of the sampling capacitor 125 is maintained by changing only the noise component from the clamp voltage. This completes the differential output with the noise removed. Thereafter, the column selection switch 126 is sequentially turned on in time series to read out a pixel signal (accumulated signal) in a state where the horizontal signal line 127 is exposed.

The advantages of this clamp-type CDS circuit are as follows: (1) Since the circuit can be completed in one row, the signal path of the signal component and the noise component can be made the same.

  (2) The layout in the column direction is compact.

(3) The operation is simple.
However, as a disadvantage, there is a problem that the signal voltage is lowered due to the capacitance division of the clamp capacitor and the sampling capacitor, and noise is easily added particularly in the horizontal signal line after the CDS circuit.

On the other hand, a technique for providing an amplification amplifier (hereinafter referred to as a column amplifier) for each column in order to increase the signal amplitude has been developed in recent years, and is disclosed in, for example, Patent Document 2.
Japanese Patent No. 2791073 JP 2001-245221 A

  However, when a column amplifier is inserted into the clamp-type CDS circuit, the amplitude of the output signal from the column amplifier is larger than the operation width of the sampling switch 131 connected thereafter, depending on the insertion position, as will be described later. It has been found that there is a problem that the signal becomes large, and all signals cannot be used, and signal propagation loss occurs.

  In particular, when the driving capability of the sampling switch 131 is set to the same level as other switches and transistors and the signal amplification factor is increased to a desired value or more, this problem becomes remarkable.

  If the driving capability of the sampling switch 131 is improved, the problem can be solved to some extent. However, since a process for separately forming the sampling switch 131 and the transistors constituting other switches is added, the manufacturing cost increases and the throughput decreases. A new problem arises.

  Accordingly, an object of the present invention is to provide a solid-state imaging device having a circuit configuration in which all signals can be used by completely propagating the amplified signal to a CDS circuit while using a column amplifier.

  In order to achieve the above object, an amplification type solid-state imaging device according to the present invention includes a unit pixel that is two-dimensionally arranged and includes a photodiode that accumulates signal charges obtained by photoelectric conversion of incident light, and the unit pixel. A vertical signal line for reading out the signal for each column, column signal amplification means for amplifying the output of the vertical signal line, a noise removal circuit for removing noise from the output of the column signal amplification means, and a noise removal circuit An amplification type solid-state imaging device having a configuration for outputting an output through a horizontal signal line and an output amplifier, wherein a clamp capacitor for clamping the output of the column signal amplification means is directly connected to the output of the column signal amplification means It is characterized by.

  It is preferable that a sampling switch for connecting and controlling the unit pixel and the noise removing circuit is directly connected to the output of the clamp capacitor.

  Preferably, the unit pixel further includes a pixel driver transistor for amplifying a signal charge generated by the photodiode and a reset transistor for setting an input potential of the pixel driver transistor.

  At least the pixel driver transistor is preferably a MOS transistor.

  Preferably, the sampling switch is composed of a MOS transistor, and the threshold values of the pixel driver transistor and the sampling switch are approximately the same.

  In the present invention, since the bias component (DC component of the signal) of the column amplifier output can be removed by the clamp capacitor, the sampling switch can be made to have full amplitude as compared to when there is no clamp capacitor.

(Embodiment)
(Circuit configuration)
FIG. 1 is a schematic diagram of an amplification type solid-state imaging device according to an embodiment of the present invention, and FIG. 2 is an enlarged view of a portion A in FIG.

  In this MOS type solid-state imaging device, a unit pixel 21 is constituted by a photodiode 50, a pixel driver transistor 36, a reset transistor 35, and a pixel power source 37 as an active type minimum transistor configuration. In addition, a pixel source follower load transistor 34 is provided in common for each column, and forms a source follower together with the pixel driver transistor 36. This source follower output is used as a signal and further amplified by the column amplifier 23.

  The output of the column amplifier 23 is directly connected to the clamp capacitor 24, and the other terminal of the clamp capacitor 24 is connected to the sampling switch 31. The output of the sampling switch 31 is connected to the clamp power source 32 via the sampling capacitor 25 and the clamp switch 33, as in the conventional CDS circuit. The sampling capacitor 25 holds the difference signal between the signal and the noise component, and the difference signal is output to the horizontal signal line 27 by turning on the column selection switch 26 of the column selected by the horizontal shift register 28. Since the principle of operation after the column amplifier is the same as that of the conventional example, a description thereof will be omitted.

  FIG. 3 is an example of a column amplifier circuit in the embodiment of the present invention. Here, an ED type amplifier circuit that is generally used is shown as an example, and the column amplifier load transistor 40 is used as a power supply side load, and the output of the unit pixel 21 is connected to a column amplifier drive transistor via a column amplifier coupling capacitor 43. 41. The operating point feedback transistor 42 is inserted after the output of the ED amplifier circuit and the column amplifier coupling capacitor 43. By turning on the operating point feedback transistor 42, the operating point center bias of the ED amplifier circuit can be fed back to the input side.

  In this embodiment mode, an example of forming with an ED type amplifier circuit is shown, but the circuit system is not restricted at all. There is no restriction on the amplification factor.

(Contrast 1 of the operation of the conventional circuit and the operation of the circuit of the present invention 1)
Hereinafter, a mechanism that can solve the problem of the present invention by directly connecting the clamp capacitor 24 to the output of the column amplifier 23 will be described with reference to FIGS.

  4A and 4B are diagrams for explaining a problem in the conventional solid-state imaging device. FIG. 4A is a circuit diagram of a portion including a CDS circuit, and FIG. 4B is a circuit diagram of FIG. It is a figure showing potential change under each node and transistor at the time of operation in a circuit. FIGS. 5A and 5B are diagrams for explaining a problem in the solid-state imaging device when the column amplifier is inserted before the clamp capacitor, FIG. 5A is a circuit diagram, and FIG. 5B is a diagram in FIG. It is the figure which showed the potential change under each node and transistor at the time of operation | movement in the circuit shown to (a).

  In each case, the circuit after the clamp capacitor 24 is omitted.

  First, FIGS. 4A and 4B will be described. In this example, a 3.0V power supply and a 3.0Vp-p pulse amplitude are assumed.

  A voltage signal from the unit pixel 21 output from the pixel driver transistor 36 is transmitted to the node 1, and the potential of the node 1 becomes an input signal of the sampling switch 31.

Here, the highest voltage Vmax transmitted to the next stage through the sampling switch 31 has the same threshold value of the pixel driver transistor 36 and the sampling switch 31, for example, 0.6V, and the modulation degree of the sampling switch 31 is 0.7. Then,
Vmax = (3−0.6) × 0.7 to 1.7V.

On the other hand, the output amplitude Vpix, which is the AC component of the pixel signal, is expressed as follows:
Vpix to Epix × Tpix (Equation 1)
When an actual value, Epix to 3000 (electrons), Tpix to 100 (μV / number of electrons) is substituted for each parameter, Vpix to 0.3 V is obtained. Further, since the power supply voltage 3.0V is divided by the pixel driver transistor 36 and the load transistor 34 which are transistors having the same performance and size, the DC potential of the node 1 is about 1.5V.

  Therefore, the maximum potential of the pixel signal is 1.5 + 0.3 / 2 to 1.65V, which is always lower than Vmax. Therefore, the sampling switch 31 is turned on at 3.0V, and the maximum potential is 1.7V. In this way, all signals can propagate to node 2.

  However, as described above, since the voltage is divided by the clamp capacitor 24 and the sampling capacitor 25, the signal voltage is greatly reduced depending on the ratio, and noise is likely to be added particularly in the horizontal signal line after the CDS circuit.

  Next, FIGS. 5A and 5B will be described. In this example, it is assumed that a 3.0V power source, a 3.0Vp-p pulse amplitude, and a column amplifier amplification factor of 5 times. Node 3 is the output of the unit pixel 21 and is the same as the operation of the conventional circuit. The column amplifier 23 is output to the node 4, but since the amplification factor is five, the above Vmax × 5 to 1.4V is obtained.

  The maximum potential of the node 4 reaches 2.2 V because the DC component of the column amplifier and the amplitude of Vmax are added, and is strong against noise.

  However, if the sampling switch 31 having the same threshold value as the conventional one is used, since the maximum potential is 1.7 V as described above, the entire amplitude of the signal cannot be propagated to the node 5.

  Therefore, the present inventors have found that the above problem can be solved by connecting the clamp capacitor 24 directly to the output of the column amplifier 23, paying attention to the arrangement relationship between the column amplifier, the clamp capacitor, and the sampling switch. .

  Hereinafter, the effects of the present invention will be described.

  6A and 6B are diagrams for explaining the effect of the solid-state imaging device according to the present embodiment. FIG. 6A is a circuit diagram of a portion including a CDS circuit, and FIG. 6B is a diagram of FIG. 6 is a diagram showing potential changes under each node and transistor during operation in the circuit shown in FIG.

  The circuit after the sampling switch 31 is not shown.

  In FIG. 6A, the clamp capacitor 24 is connected to the output of the column amplifier 23 and the sampling switch 31 is connected to the output of the clamp capacitor 24, as shown in FIG.

  In FIG. 6B, the nodes up to the node 7 are the same as the amplitudes of the nodes shown in FIG.

  Since there is a clamp capacitor 24 between the node 7 and the node 8, the DC component is removed, and only the amplitude that is the AC component is propagated. Since the amplitude after amplification of the column amplifier is about 1.4V as described above, the maximum potential of the node 8 is about 1.4V, which is the same as the signal amplitude, and the maximum potential of the sampling switch is 1.7V or less. Can be propagated to the node 9.

  Thus, by connecting the clamp capacitor 24 directly after the column amplifier 23 and connecting the sampling switch 31 after that, the amplitude after amplification is not lost, and the signal propagation loss can be eliminated.

  In the present embodiment, an example in which the clamp capacitor 24 is directly connected to the output of the column amplifier 23 and the sampling switch 31 is directly connected to the output of the clamp capacitor 24 is shown. However, depending on other circuit forms, The sampling switch 31 may not be provided.

(Contrast 2 between the operation of the conventional circuit and the operation of the circuit of the present invention)
As shown in FIG. 2, when the sampling switch 31 is directly connected to the output of the clamp capacitor 24, the speed can be increased compared to the conventional configuration.

  Hereinafter, this point will be described with reference to FIGS.

  FIG. 7 is a diagram showing the configuration and operation of the solid-state imaging device when a column amplifier is inserted in front of the clamp capacitor. FIG. 7A is a circuit diagram of a portion including a CDS circuit, and FIG. FIG. 7C is a timing chart for explaining the operation of the CDS circuit, and FIG. 7C is an equivalent circuit diagram of the CDS circuit at the time of signal reading.

  As shown in FIG. 7A, the sampling switch 31 is connected to the column amplifier 23, the clamp capacitor 24 is connected thereafter, and the sampling capacitor 25 is further connected to the output node of the clamp capacitor 24.

  The operation is as described with reference to FIG. 11, and the timing chart shown in FIG. 7B is the same as that shown in FIG.

  Here, for example, in the configuration having no column amplifier 23 as shown in FIG. 4, only the sampling capacitor 25 is connected via the column selection switch 26 before the clamp capacitor 24 (FIG. 4 shows). The signal is propagated using the sampling capacitor 25 as a load. However, when the column amplifier 23 is arranged at the position shown in FIG. 7A, the clamp capacitor 24 is connected to the same node as the sampling capacitor 25. Since they are connected, a circuit in which the capacitance of the clamp capacitor 24 to the substrate is connected as a parasitic capacitance is obtained. In particular, when a MOS capacitor is used, the capacitance is about 10% of the clamp capacitance 24 and cannot be ignored. This has an adverse effect when it is necessary to read out to the horizontal signal line at a high frequency (25 MHz or higher).

  On the other hand, FIG. 8 is a diagram showing the configuration and operation of the solid-state imaging device of the present embodiment. FIG. 8 (a) is a circuit diagram of a portion including a CDS circuit, and FIG. 8 (b) is an operation of this CDS circuit. FIG. 8C is an equivalent circuit diagram of the CDS circuit at the time of signal reading.

  According to the present embodiment, not the clamp capacitor 24 but the sampling switch 31 is connected to the node to which the sampling capacitor 25 is connected. Therefore, the sampling capacitor 25 is connected to the horizontal signal line 27 via the column selection switch 26. When reading, the sampling switch 31 is closed. Therefore, when reading a signal, the capacitance to the substrate in the clamp capacitor 24 is disconnected from the signal line, and the load is reduced, so that the signal reading from the sampling capacitor 25 to the horizontal signal line 27 can be speeded up.

  As described above, according to the amplification type solid-state imaging device of the present invention, since the noise can be greatly improved compared to the conventional amplification type solid-state imaging device, an image with a high S / N ratio can be obtained even if the signal amplitude is low. Can be obtained.

  Therefore, a camera equipped with the solid-state imaging device of the present invention is suitable for high-performance still image shooting applications and high-definition video shooting applications that require high S / N image quality at low illuminance.

  In addition, it is not necessary to make the sampling switch 31 and the pixel driver transistor 36 separately, for example, so that an increase in manufacturing cost can be suppressed and throughput can be improved.

  Note that the amplification type solid-state imaging device of the present invention is not limited to the circuit format of each pixel, and may be provided with a circuit that can perform photoelectric conversion and output the signal component and the signal component after reset. . Further, any of an amplification type solid-state imaging device of an active type that outputs by an amplifier circuit including an amplifier that amplifies a voltage in which signal charges are converted by a floating diffusion capacitor and a passive type that does not include an amplifier may be used. Further, the conductivity type of the MOS transistor used as each switch is not particularly limited.

  The MOS type solid-state image pickup device of the present invention can greatly improve noise compared to the conventional MOS type solid-state image pickup device, and requires a high S / N image quality at low illuminance. It is particularly useful for MOS-type solid-state imaging devices for consumer and professional digital still cameras, MOS-type solid-state imaging devices for broadcasting mainly for high-definition video imaging, astronomical observation cameras, and the like.

Schematic diagram of an amplification type solid-state imaging device according to an embodiment of the present invention The enlarged view of the A section in the amplification type solid-state imaging device in the embodiment of the present invention The figure which showed an example of the column amplifier circuit in embodiment of this invention It is a figure for demonstrating the subject in the conventional solid-state imaging device, (a) is a circuit diagram of the part containing a CDS circuit, (b) is each node and transistor under operation in the circuit shown to (a). Figure showing potential change at It is a figure for demonstrating the subject with the solid-state imaging device when a column amplifier is inserted in the front | former stage of clamp capacity, (a) is a circuit diagram, (b) is each at the time of operation | movement in the circuit shown to (a). Diagram showing potential change under node and transistor It is a figure for demonstrating the effect in the solid-state imaging device in embodiment of this invention, (a) is a circuit diagram of the part containing a CDS circuit, (b) is the time of operation | movement in the circuit shown to (a). Diagram showing potential change under each node and transistor It is the figure which showed the structure and operation | movement of a solid-state imaging device when a column amplifier is inserted in the front | former stage of clamp capacity, (a) is a circuit diagram of the part containing a CDS circuit, (b) demonstrates operation | movement of this CDS circuit. (C) is an equivalent circuit diagram of the CDS circuit at the time of signal reading. It is a figure showing composition and operation of a solid imaging device of this embodiment, (a) is a circuit diagram of a portion containing a CDS circuit, (b) is a timing chart for explaining operation of this CDS circuit, ( c) is an equivalent circuit diagram of the CDS circuit at the time of signal reading. Schematic diagram of an amplification type solid-state imaging device equipped with a conventional CDS circuit Enlarged view of part B in a conventional amplification type solid-state imaging device Timing chart for explaining the operation of a conventional clamp type CDS circuit

Explanation of symbols

20, 120 Semiconductor chip 21, 121 Unit pixel 22, 122 Light receiving unit 23 Column amplifier 24, 124 Clamp capacitor 25, 125 Sampling capacitor 26, 126 Column selection switch 27, 127 Horizontal signal line 28, 128 Horizontal shift register 29, 129 Vertical Shift register 30, 130 Output amplifier 31, 131 Sampling switch 32, 132 Clamp power supply 33, 133 Clamp switch 34, 134 Pixel source follower load transistor 35, 135 Reset transistor 36 Pixel driver transistor 40 Column amplifier load transistor 41 Column amplifier drive transistor 42 Operating point feedback transistor 43 row amplifier coupling capacitance

Claims (1)

Unit pixels including photodiodes that are two-dimensionally arranged and store signal charges obtained by photoelectric conversion of incident light;
A vertical signal line for reading out the signal of the unit pixel for each column;
Column signal amplification means for amplifying the output of the vertical signal line;
A CDS circuit for removing noise from the output of the column signal amplification means;
An amplification type solid-state imaging device having a configuration for outputting an output from the CDS circuit through a horizontal signal line and an output amplifier,
The CDS circuit includes a clamp capacitor directly output to an output of the column signal amplifying unit;
A sampling switch for connecting and separating the unit pixel and the sampling capacitor , which are directly connected to the output of the clamp capacitor;
An amplification type solid-state imaging device, comprising: a clamp power source connected to an output of the sampling switch via a clamp switch.

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