JP4664845B2 - Key matrix circuit - Google Patents

Description

  The present invention relates to a key matrix circuit, and more particularly to a small and light key matrix circuit provided for operating a mobile phone, a PHS, and the like.

  The key matrix circuit is one of circuits that detect key input in the device, and the key matrix circuit has a push key switch at a position where a row and a column intersect. When the key switch is pressed, the row and the column at the arranged position are short-circuited, and the pressed key switch is detected by a control device or the like.

  In general, the number of key switches that can be detected by the key matrix circuit is determined by the product of the number of lines provided in each row and column. For example, if there are three row lines and three column lines, the number of key switches is nine at the maximum.

  2A shows a key matrix circuit 200 having nine key switches, and FIG. 2B shows a time-series signal of each line. The key matrix circuit 200 includes a scan signal transmission port 10 having three row lines, a signal readout port 12 having three column lines, pull-up resistors (R1 to R3) for pulling up each column line, Nine key switches for short-circuiting the row line and the column line.

  In FIG. 2A, the 6th key switch is pressed, and the row and column lines are short-circuited. The scan signal transmission port 10 transmits a scan signal falling from “H” to “L” as shown in FIG. 2B to each column line (KEYOUT 1 to 3). The signal read ports 12 (KEYIN 1 to 3) detect a short circuit of the key switch corresponding to the number key of each column in synchronization with the scan signal. In the case of FIG. 2B, when the row of KEYOUT2 is scanned, the key switch corresponding to the 6th key switch becomes “L” and a short circuit is detected. In this way, the key switch is detected.

  However, when the number of key switches is increased from nine to ten, it is necessary in the prior art to add one row line or one column line and use a 3 × 4 matrix, and the extra three Will have the key input.

  In order to solve such a problem, Patent Document 1 discloses a key switch in which one end is grounded and the other end is short-circuited to the column line side in addition to m × n key switches that short-circuit the row line and the column line. By adding (hereinafter referred to as a short-circuit key switch), there is disclosed a technique capable of providing a key switch without increasing the number of lines.

JP 2000-66822 A FIG.

  The key matrix circuit disclosed in Patent Document 1 has a configuration in which the number of column lines is larger than that of row lines, and one short-circuit key switch is added to each row line. As shown in FIG. 3 of Patent Document 1, the CPU applies each row line so as to be in three states of “H”, “L”, and “high impedance”. The CPU detects that the column line at that time is always in the “L” state, and determines that the short circuit key switch has been pressed.

  However, in the technique of Patent Document 1, when the short-circuit key switch is pressed, the other key switches are always determined to be “L”, and thus the key switch cannot be detected during this time. When such a short-circuit key switch is used as a power switch, there is a problem that other key switches cannot be used while the device is operating.

  In order to solve the above problems, a key matrix circuit according to the present invention transmits a scan signal to a key switch using a plurality of key switches arranged in a matrix by row lines and column lines, and the row lines. In a key matrix circuit having a transmission port and a read port for reading out the state of the key switch using the pulled-up column line, the state of one key switch of the key matrix is output to the column line by a scan signal of the row line And a ground key switch having one terminal connected to the column line with one terminal pulled up via the detection circuit and the other terminal grounded, and the detection circuit is connected to the ground key switch. The open / close state is output to the column line by the scan signal of the row line.

  In the key matrix circuit according to the present invention, the detection circuit is formed of a field effect transistor.

  When the present invention is used, even if a power switch is connected to the key matrix circuit, ON / OFF detection of other key switches and power switches can be performed at the signal readout port.

  Hereinafter, an embodiment (hereinafter referred to as a reference example) which is a reference for understanding the present invention and an embodiment of the present invention (hereinafter referred to as an embodiment) will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same member as the structure mentioned above, and description is abbreviate | omitted.

  3 and 4 show an embodiment in which a power switch is added to a key matrix circuit (300, 400) as a reference example. Normally, the number 9 key switch is provided with a key switch for short-circuiting the row line and the column line, but FIG. 3 shows a configuration in which a power switch is added to the number 9 key switch.

  In such a configuration, when the power switch 24 is turned “ON”, the KEYIN3 column is always “L” even though the 3rd and 5th key switches are not pressed. For this reason, the configuration is the same as that of the detection circuit of only the power switch 24 that is normally in the “ON” state as shown in FIG. 4, and the third and fifth key switches cannot be used.

  FIG. 1 shows a key matrix circuit 100 in which a detection circuit 30 for detecting “ON / OFF” of the power switch 24 is added at the position of the ninth key switch. The detection circuit 30 includes a p-channel FET 16, an n-channel FET 14, a pull-up resistor R4, and pull-down resistors (R5, R6). The power supply of the load 22 is controlled by the p-channel FET 18. The load 22 is connected between the source side of the p-channel type FET 18 and the ground, and the “ON / OFF” of the power supplied to the load is controlled by the “ON / OFF” of the power switch 24 connected to the gate side. The

  Next, the flow of operation by “ON / OFF” of the power switch 24 is shown. When the power switch 24 is “OFF”, the gate of the p-channel FET 18 becomes “H” by the pull-up resistor R4, and the drain-source state is in a high impedance state. For this reason, the load 22 is not energized. The n-channel FET 14 is “OFF”, and the drain potential of the n-channel FET 14 is always “H” regardless of the output of the KEYOUT3.

When the power switch 24 is “ON”, the n-channel FET 14 is “ON”.
Thus, when the output level of KEYOUT3 is “H”, the drain of the n-channel FET 14 is “H”, and when the output level of KEYOUT3 is “L”, the drain of the n-channel FET 14 is “L”.

  Thus, the state of the power switch 24 can be detected from KEYIN3 at the timing of the scan signal of KEYOUT3.

  As described above, by using this embodiment, even when the power switch is connected to the key matrix circuit, other key switches can be detected, and the key for the mobile phone capable of effectively using the key matrix can be used. A matrix circuit can be provided. In the present embodiment, an FET is used, but the present invention is not limited to this, and a transistor switch or other switches may be used.

It is a block diagram of the key matrix circuit to which the power switch which concerns on embodiment of this invention was connected. It is the schematic diagram which shows the block diagram and operation | movement of the conventional key matrix circuit. It is a block diagram of the key matrix circuit in embodiment which becomes reference in understanding this invention. It is a block diagram of the key matrix circuit in embodiment which becomes reference in understanding this invention.

Explanation of symbols

  10 scan signal transmission port, 12 signal readout port, 22 load, 24 power switch, 30 detection circuit, 100, 200, 300, 400 key matrix circuit, 14 n-channel FET, 16, 18 p-channel FET.

Claims (2)

A plurality of key switches arranged in a matrix by row lines and column lines, a send port for sending a scan signal to the key switches using the row lines, and a readout for reading the state of the key switches using the pulled-up column lines A key matrix circuit having ports,
A detection circuit for outputting the state of one key switch of the key matrix to the column line by a scan signal of the row line;
A grounding key switch having one terminal connected to the pulled-up column line via the detection circuit and the other terminal grounded;
With
The detection circuit outputs an open / close state of the ground key switch to a column line by a scan signal of a row line. The key matrix circuit according to claim 1,
A key matrix circuit, wherein the detection circuit comprises a field effect transistor.

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