JP4662744B2 - モンゴメリ乗算におけるsimd命令の使用 - Google Patents

モンゴメリ乗算におけるsimd命令の使用 Download PDF

Info

Publication number
JP4662744B2
JP4662744B2 JP2004269033A JP2004269033A JP4662744B2 JP 4662744 B2 JP4662744 B2 JP 4662744B2 JP 2004269033 A JP2004269033 A JP 2004269033A JP 2004269033 A JP2004269033 A JP 2004269033A JP 4662744 B2 JP4662744 B2 JP 4662744B2
Authority
JP
Japan
Prior art keywords
array
instruction
simd
instructions
modulus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2004269033A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005122141A5 (enExample
JP2005122141A (ja
Inventor
エル.モンゴメリー ピーター
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsoft Corp
Original Assignee
Microsoft Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Corp filed Critical Microsoft Corp
Publication of JP2005122141A publication Critical patent/JP2005122141A/ja
Publication of JP2005122141A5 publication Critical patent/JP2005122141A5/ja
Application granted granted Critical
Publication of JP4662744B2 publication Critical patent/JP4662744B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/728—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic using Montgomery reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)
JP2004269033A 2003-10-15 2004-09-15 モンゴメリ乗算におけるsimd命令の使用 Expired - Lifetime JP4662744B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/686,316 US7532720B2 (en) 2003-10-15 2003-10-15 Utilizing SIMD instructions within montgomery multiplication

Publications (3)

Publication Number Publication Date
JP2005122141A JP2005122141A (ja) 2005-05-12
JP2005122141A5 JP2005122141A5 (enExample) 2007-10-18
JP4662744B2 true JP4662744B2 (ja) 2011-03-30

Family

ID=34377640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004269033A Expired - Lifetime JP4662744B2 (ja) 2003-10-15 2004-09-15 モンゴメリ乗算におけるsimd命令の使用

Country Status (7)

Country Link
US (1) US7532720B2 (enExample)
EP (1) EP1524594B1 (enExample)
JP (1) JP4662744B2 (enExample)
KR (1) KR101103893B1 (enExample)
CN (1) CN100437548C (enExample)
AT (1) ATE413642T1 (enExample)
DE (1) DE602004017559D1 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040249782A1 (en) * 2003-06-04 2004-12-09 International Business Machines Corporation Method and system for highly efficient database bitmap index processing
CN1985458B (zh) * 2003-11-16 2013-05-08 桑迪斯克以色列有限公司 增强的自然蒙哥马利指数掩蔽和恢复的方法和装置
KR100530372B1 (ko) * 2003-12-20 2005-11-22 삼성전자주식회사 사이드채널 공격을 방지할 수 있는 타원곡선 암호화 방법
US7664810B2 (en) * 2004-05-14 2010-02-16 Via Technologies, Inc. Microprocessor apparatus and method for modular exponentiation
JP5027422B2 (ja) * 2006-02-09 2012-09-19 ルネサスエレクトロニクス株式会社 剰余演算処理装置
US8036379B2 (en) * 2006-03-15 2011-10-11 Microsoft Corporation Cryptographic processing
KR20120077164A (ko) 2010-12-30 2012-07-10 삼성전자주식회사 Simd 구조를 사용하는 복소수 연산을 위한 사용하는 장치 및 방법
CN102431508B (zh) * 2011-10-12 2014-06-11 奇瑞汽车股份有限公司 太阳能汽车天窗供电控制方法、系统以及汽车
WO2013089750A1 (en) * 2011-12-15 2013-06-20 Intel Corporation Methods to optimize a program loop via vector instructions using a shuffle table and a blend table
US9268564B2 (en) * 2012-05-30 2016-02-23 Intel Corporation Vector and scalar based modular exponentiation
US10095516B2 (en) 2012-06-29 2018-10-09 Intel Corporation Vector multiplication with accumulation in large register space
US9355068B2 (en) 2012-06-29 2016-05-31 Intel Corporation Vector multiplication with operand base system conversion and re-conversion
JP5852594B2 (ja) * 2013-01-15 2016-02-03 日本電信電話株式会社 多倍長整数演算装置、多倍長整数演算方法、プログラム
CN104951279B (zh) * 2015-05-27 2018-03-20 四川卫士通信息安全平台技术有限公司 一种基于NEON引擎的向量化Montgomery模乘器的设计方法
IL239880B (en) * 2015-07-09 2018-08-30 Kaluzhny Uri Simplified montgomery multiplication
CN106452723B (zh) * 2016-12-13 2017-05-31 深圳市全同态科技有限公司 一种基于模运算的全同态加密处理方法
JP7286239B2 (ja) * 2019-02-28 2023-06-05 ルネサスエレクトロニクス株式会社 演算処理方法、演算処理装置、及び半導体装置
US20230042366A1 (en) * 2021-07-23 2023-02-09 Cryptography Research, Inc. Sign-efficient addition and subtraction for streamingcomputations in cryptographic engines
US12008369B1 (en) 2021-08-31 2024-06-11 Apple Inc. Load instruction fusion
JP7673871B2 (ja) * 2022-04-13 2025-05-09 日本電気株式会社 符号付き整数の剰余積計算装置、符号付き整数の剰余積計算方法及び、プログラム
US12632258B1 (en) 2022-09-22 2026-05-19 Apple Inc. Fused instruction operation for performing an operation and adjusting a sign of the operation result
US12288066B1 (en) 2022-09-23 2025-04-29 Apple Inc. Operation fusion for instructions bridging execution unit types
US12217060B1 (en) 2022-09-23 2025-02-04 Apple Inc. Instruction fusion

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2726667B1 (fr) * 1994-11-08 1997-01-17 Sgs Thomson Microelectronics Procede de mise en oeuvre de multiplication modulaire selon la methode montgomery
US6202077B1 (en) * 1998-02-24 2001-03-13 Motorola, Inc. SIMD data processing extended precision arithmetic operand format
JP3869947B2 (ja) * 1998-08-04 2007-01-17 株式会社日立製作所 並列処理プロセッサ、および、並列処理方法
US7240204B1 (en) 2000-03-31 2007-07-03 State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University Scalable and unified multiplication methods and apparatus
JP2002007112A (ja) * 2000-06-20 2002-01-11 Sony Corp 剰余演算計算方法および剰余演算計算装置
JP3785044B2 (ja) * 2001-01-22 2006-06-14 株式会社東芝 べき乗剰余計算装置、べき乗剰余計算方法及び記録媒体
JP2002229445A (ja) * 2001-01-30 2002-08-14 Mitsubishi Electric Corp べき乗剰余演算器
CN1375765A (zh) * 2001-03-19 2002-10-23 深圳市中兴集成电路设计有限责任公司 一种快速大数模乘运算电路
US7107305B2 (en) * 2001-10-05 2006-09-12 Intel Corporation Multiply-accumulate (MAC) unit for single-instruction/multiple-data (SIMD) instructions
EP1459167B1 (en) * 2001-12-14 2006-01-25 Koninklijke Philips Electronics N.V. Pipelined core in montgomery multiplier
US7266577B2 (en) * 2002-05-20 2007-09-04 Kabushiki Kaisha Toshiba Modular multiplication apparatus, modular multiplication method, and modular exponentiation apparatus

Also Published As

Publication number Publication date
US7532720B2 (en) 2009-05-12
KR101103893B1 (ko) 2012-01-12
ATE413642T1 (de) 2008-11-15
DE602004017559D1 (de) 2008-12-18
US20050084099A1 (en) 2005-04-21
JP2005122141A (ja) 2005-05-12
CN100437548C (zh) 2008-11-26
CN1607518A (zh) 2005-04-20
EP1524594A3 (en) 2006-04-12
EP1524594A2 (en) 2005-04-20
KR20050036698A (ko) 2005-04-20
EP1524594B1 (en) 2008-11-05

Similar Documents

Publication Publication Date Title
JP2005122141A (ja) モンゴメリ乗算におけるsimd命令の使用
US7346159B2 (en) Generic modular multiplier using partial reduction
JP3605181B2 (ja) 掛け算累算命令を使用したデータ処理
Großschädl et al. Instruction set extensions for fast arithmetic in finite fields GF (p) and GF (2 m)
US8977668B2 (en) Calculating unit for reducing an input number with respect to a modulus
Hoeven et al. Modular SIMD arithmetic in Mathemagix
JP7096828B2 (ja) 入力オペランド値を処理するための装置及び方法
JP2019500673A (ja) 冗長表現を用いた、第1および第2のオペランドの積算
Bos et al. Montgomery arithmetic from a software perspective
US8229993B2 (en) Method for performing decimal division
JP2019500672A (ja) 重複ビットを使用する数値の冗長表現
JP2005122141A5 (enExample)
Pornin Optimized binary gcd for modular inversion
Lórencz New algorithm for classical modular inverse
US7558817B2 (en) Apparatus and method for calculating a result of a modular multiplication
US7240204B1 (en) Scalable and unified multiplication methods and apparatus
CN101981542B (zh) 多项式数据处理运算
JP2004227344A (ja) 乗算器及び暗号回路
US8364740B2 (en) Device and method for calculating a result of a modular multiplication with a calculating unit smaller than the operands
US7672990B2 (en) Digital computation method involving euclidean division
Oliveira et al. Koblitz curves over quadratic fields
US20070100926A1 (en) Device and method for calculating a multiplication addition operation and for calculating a result of a modular multiplication
US8364737B2 (en) Device and method for calculating a result of a sum with a calculating unit with limited word length
WO2003096182A1 (en) “emod” a fast modulus calculation for computer systems
JP4223819B2 (ja) べき乗剰余演算装置及びそのプログラム

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070904

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070904

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100903

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101202

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20101224

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110104

R150 Certificate of patent or registration of utility model

Ref document number: 4662744

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140114

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term