JP4660968B2 - Resist pattern manufacturing method and lithography process management method - Google Patents

Description

【００２４】
また、フォーカスをＹ、フォーカスＹのばらつきの標準偏差をα２とすると、フォーカス設定値の存在確率Ｚ２（Ｚ２＜１）は、以下に示す式（２）で表すことができる。
【００２５】
【数２】

【００２６】
露光量設定値とフォーカス設定値とが同時に存在する存在確率は、式（１）に示した露光量の存在確率Ｚ１と、式（２）に示したフォーカス設定値の存在確率Ｚ２とを掛け合わせることによって得ることができる。存在確率Ｚ１と存在確率Ｚ２とを掛け合わせた後、得られる式の両辺について対数をとり、以下に示す式（３）を得る。
【００２７】
【数３】

【００２８】
したがって、式（３）で表される露光量設定値とフォーカス設定値とが同時に存在する存在確率は、露光量方向半径とフォーカス方向半径との比がα１対α２の楕円で表される。露光量設定値およびフォーカス設定値は、楕円形状のＥＤＷを用いて、その楕円の中心が示す露光量を露光量設定値として決定することができ、楕円の中心が示すフォーカスをフォーカス設定値として決定することができる。
【００２９】
次に所望のレジストパターンを作製するために必要な露光量であるパターン領域露光量と、所望のレジストパターンを作製するために必要なフォーカスであるパターン領域フォーカスとの設定条件が存在可能な領域である設定条件存在領域について説明する。
【００３０】
設定条件存在領域は、レジストパターン作製後に最終的に形成するパターン線幅の許容上限値と許容下限値とで決定される範囲である製品としてのスペックなどを考慮して決定される。
【００３１】
図２は決定された設定条件存在領域のひとつの例を示す図である。
例えば、レジストパターン作製の露光量を露光量Ｍに固定した場合、設定条件存在領域２０から求められる可能なフォーカスの設定値はフォーカスＮ１からフォーカスＮ２の範囲になる。すなわち、露光量Ｍでのフォーカスの値がフォーカスＮ１を下回った場合、あるいはフォーカスＮ２を上回った場合には、形成されるパターンの実際の線幅が所望の線幅スペックから外れてしまう。
【００３２】
一方、レジストパターン作製のフォーカスをフォーカスＮに固定した場合、設定条件存在領域２０から求められる可能な露光量の設定値は露光量Ｍ１から露光量Ｍ２の範囲になる。すなわち、フォーカスＮでの露光量の値が露光量Ｍ１を下回った場合、あるいは露光量Ｍ２を上回った場合には、形成されるパターンの実際の線幅が所望の線幅スペックから外れてしまう。
【００３３】
このように、レジストパターンの作製環境、作製条件を考慮して、レジストパターン作製前に、目的の線幅のパターンを形成するために必要な露光量ＭおよびフォーカスＮを調査して設定条件存在領域を決定する。
【００３４】
次に、レジストパターン作製に用いる露光量設定値およびフォーカス設定値の設定方法について説明する。
図１は露光量およびフォーカスの各設定値の設定方法を説明する図であり、（ａ）は作製パターン、（ｂ）は分割したパターン領域、（ｃ）は各パターン領域の設定条件存在領域、（ｄ）はＥＤＷをそれぞれ示している。
【００３５】
また、図１において横軸は露光量を表し、縦軸はフォーカスを表している。
まず、図１（ａ）に示した作製すべきパターン１について、パターン１が疎な部分、パターン１が密な部分を考慮してパターン密度がほぼ同一とみなすことができるパターン領域に分割する。ここでは、図１（ｂ）に示すように、ラインが孤立している領域であるパターン孤立領域２と、パターン同士が密に形成される領域であるパターン密集領域３と、パターン孤立領域２とパターン密集領域３との中間程度にパターン同士が集合している領域であるパターン集合領域４とに分割を行う。
【００３６】
次いで、図１（ｃ）に示すように、分割したパターン孤立領域２、パターン密集領域３、パターン集合領域４のそれぞれの領域について、所望のレジストパターンを作製するために必要な露光量であるパターン領域露光量と、所望のレジストパターンを作製するために必要なフォーカスであるパターン領域フォーカスとの設定条件が存在可能な領域である設定条件存在領域２ａ、３ａ、４ａを、作製すべきレジストパターンの線幅、露光装置の性能、下地基板の平坦度、およびレジストパターン作製後に最終的に形成するパターン線幅の許容上限値と許容下限値とで決定される範囲である製品としてのスペックなどを考慮して決定する。
【００３７】
さらに、図１（ｄ）に示すように、パターン孤立領域２、パターン密集領域３、パターン集合領域４の各領域について決定された設定条件存在領域２ａ、３ａ、４ａをすべて重ね合わせ、重ね合わされた設定条件存在領域である共通設定条件存在領域５ａを作成する。
【００３８】
この共通設定条件存在領域５ａに含まれるすべてのパターン領域に共通する共通設定条件存在領域５ａ内であって、かつ、露光量のばらつきの標準偏差α１とフォーカスのばらつきの標準偏差α２との軸比を有する式（３）で表される楕円のうち、その面積が最大となるような楕円形状の共通ＥＤＷ５ｂを決定する。この共通ＥＤＷ５ｂは、レジストパターンの作製に用いる露光量およびフォーカスの各設定値が存在する領域である設定値存在領域を示している。そして、この共通ＥＤＷ５ｂを示す楕円の中心５ｃによって決定される露光量とフォーカスとをレジストパターン作製の露光量設定値６とフォーカス設定値７とする。
【００３９】
共通ＥＤＷ５ｂは、所望のレジストパターンを作製するのに必要な露光量およびフォーカスの設定条件が存在する領域である共通設定条件存在領域５ａの中心的領域であって、実際のレジストパターン作製の際に露光量やフォーカスの中心５ｃが示す値からのずれが許容される余裕度を示している。すなわち、レジストパターン作製時に露光量やフォーカスにずれが生じた場合でも、ずれた露光量やフォーカスの値が、ＥＤＷ５ｂ内であれば、作製したパターンの線幅を十分スペック内に抑えることができる。
【００４０】
もちろん、あるパターン領域、例えばパターン孤立領域２について、レジストパターン作製時の露光量やフォーカスのずれが、このパターン孤立領域２について決定した設定条件存在領域２ａ内であれば、このパターン孤立領域２に含まれるパターンはスペック内に抑えられる。パターン密集領域３、パターン集合領域４についても同様である。
【００４１】
図３は（ａ）各領域の設定条件存在領域についてＥＤＷを作成した場合と、（ｂ）各領域の共通設定条件存在領域に対して共通ＥＤＷを作成した場合とを示す図である。
【００４２】
パターン孤立領域２、パターン密集領域３、パターン集合領域４の各領域について見ると、図３（ａ）に示した各領域の設定条件存在領域２ａ、３ａ、４ａについて作製したＥＤＷ２ｂ、３ｂ、４ｂの楕円の中心２ｃ、３ｃ、４ｃと、図３（ｂ）に示した各領域の共通ＥＤＷ５ｂの中心５ｃを各領域の設定条件存在領域２ａ、３ａ、４ａに当てはめた場合とでは、各領域について中心２ｃと中心５ｃ、中心３ｃと中心５ｃ、中心４ｃと中心５ｃとはそれぞれ異なっている。すなわち、設定値として決定される露光量とフォーカスとが、ＥＤＷ２ｂ、３ｂ、４ｂを用いて決定した場合と、共通ＥＤＷ５ｂを用いて決定した場合とで異なる。
【００４３】
従来のように、図３（ａ）に示したパターン孤立領域２、パターン密集領域３、パターン集合領域４のうちのいずれかひとつ、例えばパターン孤立領域２を、レジストパターン全体を代表するパターン領域として選択した場合、この選択されたパターン孤立領域２に作成されるＥＤＷ２ｂの中心２ｃが、他のパターン領域に作成されるＥＤＷ３ｂ、４ｂの中心３ｃ、４ｃと一致しない。その結果、選択されたパターン孤立領域２に作成されるＥＤＷ２ｂの中心２ｃから決定された露光量設定値とフォーカス設定値とが、他のパターン領域であるパターン密集領域３の設定条件存在領域３ａ、パターン集合領域４の設定条件存在領域４ａから外れてしまう場合が生じる。
【００４４】
一方、図３（ｂ）に示した共通ＥＤＷ５ｂの中心５ｃは必ずパターン孤立領域２、パターン密集領域３、パターン集合領域４の各領域の設定条件存在領域２ａ、３ａ、４ａ内にあるので、作製するレジストパターン全体について共通して使用することができ、かつ、スペック内の線幅のパターンを形成するためのレジストパターンを作製することのできる露光量設定値６とフォーカス設定値７とを得ることができる。
【００４５】
以上説明したように、パターンをパターン孤立領域２、パターン密集領域３、パターン集合領域４の各領域に分割し、それぞれの領域について設定条件存在領域２ａ、３ａ、４ａを決定し、設定条件存在領域２ａ、３ａ、４ａを重ね合わせ、共通設定条件存在領域５ａを作成した後、この共通設定条件存在領域５ａに共通ＥＤＷ５ｂを決定し、この共通ＥＤＷ５ｂを示す楕円の中心５ｃによって決定される露光量およびフォーカスをレジストパターン作製の露光量設定値６およびフォーカス設定値７とする。
【００４６】
これにより、作製すべきパターン１内に、パターン密度の異なる領域が存在する場合であっても、共通ＥＤＷ５ｂから決定される露光量設定値６とフォーカス設定値７とは、レジストパターン全体について共通して使用することができ、さらに共通ＥＤＷ５ｂの面積が最大となるように決定するので、スペック内のパターンを高い歩留まりで作製することができるようになる。
【００４７】
次に、本発明の実施の形態を、０．１８μｍのゲート長を持つＤＲＡＭ（Dynamic Random Access Memory）ゲートパターンの作製に適用した場合を例にして説明する。ここではＤＲＡＭゲートパターンのゲート線同士の間隔であるゲートピッチが０．４２μｍである場合について説明する。
【００４８】
ＤＲＡＭゲートパターンの作製は、まず、レジストを塗布し、温度９０℃、時間６０秒のポストベークを施した後、露光を行う。露光後、温度１００℃、時間９０秒のポストエクスポージャーベークを行い、パドル現像を時間６０秒施し、純水リンス後、温度９０℃、時間６０秒のプリベイクを行う。次いで、レジストパターン作製後、レジストによってマスクされていない部分のエッチングを行う。
【００４９】
このような手順で進められるＤＲＡＭゲートパターンの作製において、レジストパターン作製後のエッチングの際、ゲート線はマスクされているレジストの外縁からパターンの内側に削られる量であるエッチング変換差が０．０２μｍ存在することがわかっている。したがって、ゲート線幅を目的の０．１８μｍにするためには、レジストパターン作製後のエッチングによって削られてしまうエッチング変換差をあらかじめ考慮してレジスト線幅を０．２０μｍにしておく必要がある。
【００５０】
図４はＤＲＡＭゲートパターンのＥＤＷを示す図である。
図４では、上記のエッチング変換差を考慮したレジストの設計線幅を０．２０μｍとし、この設計線幅に対してレジスト線幅のスペックを、０．２０±０．０２μｍと設定し、設定条件存在領域８を決定する。作成された設定条件存在領域８において、フォーカスが０μｍ、すなわちベストフォーカスで、設計線幅０．２０μｍのレジスト線幅を作製することができる露光量の設計値である設計露光量が決定する。この設計露光量およびベストフォーカスを点Ｐで示す。
【００５１】
ここで、露光装置の露光量のばらつきの標準偏差は１．０ｍＪ／ｃｍ²、フォーカスのばらつきの標準偏差は０．２μｍであり、点Ｐを中心として設定条件存在領域８内に、長軸と短軸との比である軸比が１．０対０．２の楕円形状のＥＤＷ９を作成することができる。
【００５２】
一方、設定条件存在領域８内に軸比１．０対０．２の楕円形状であって、その面積が最大となるＥＤＷ１０を決定した場合、このＥＤＷ１０の中心である点Ｑが示す露光量設定値およびフォーカス設定値によって作製されるレジストパターンの線幅は０．２０７μｍとなる。このように決定したＥＤＷ１０の面積は、設計線幅が中央部にあるＥＤＷ９の面積より大きくなっている。したがって、設計線幅である０．２０μｍに代えて、０．２０７μｍをリソグラフィプロセスのねらい線幅にしてレジストパターンの作製を行うことで、レジストパターン作製時の露光量およびフォーカスの変動に対する余裕度が大きくなり、形成するパターンの線幅がスペックから外れる確率は低くなる。
【００５３】
これに対し、従来のように設計線幅０．２０μｍをねらい線幅にしてレジストパターンの作製を行う場合、ＥＤＷ９が小さいため、レジストパターン作製時の露光量やフォーカスの変動によって設計線幅から外れ、形成されるパターンの線幅がスペックを外れてしまう確率が高くなり、その結果として、歩留まりが低下してしまうことが予想される。
【００５４】
次に、本発明の実施の形態を、０．１５μｍのゲート長を持つロジックゲートパターンの作製に適用した場合を例にして説明する。
図５はロジックゲートパターンの光近接効果補正後のレジスト線幅を示す図である。
【００５５】
まず、形成すべきロジックゲートパターン１１を、孤立ライン領域１２、０．４２μｍピッチ領域１３、０．８０μｍピッチ領域１４の各領域に分割する。これらのパターンは同露光量で作製しなければならない。そのため、光近接効果補正を行う。光近接効果補正により、孤立ライン領域１２のラインは０．１５μｍ、０．４２μｍピッチ領域１３のラインは０．１５５μｍ、０．８０μｍピッチ領域１４のラインは０．１７μｍのマスク線幅を持ったマスクパターンでレジストパターンを作製する。また、レジストパターン作製後のエッチングの際、ゲート線がマスクされているレジストの外縁からパターンの内側に削られてしまう量であるエッチング変換差がないものとし、レジストパターンのねらい線幅はすべてのパターンについて０．１５μｍとする。
【００５６】
図６はロジックゲートパターンの共通ＥＤＷを示す図である。
線幅スペックを０．１５±０．０１５μｍとして、孤立ライン領域１２、０．４２μｍピッチ領域１３、０．８０μｍピッチ領域１４のそれぞれの領域について設定条件存在領域１２ａ、１３ａ、１４ａを決定し、設定条件存在領域１２ａ、１３ａ、１４ａを重ね合わせ、共通設定条件存在領域を決定する。
【００５７】
この共通設定条件存在領域内であって、かつ、露光量のばらつきの標準偏差α１とフォーカスのばらつきの標準偏差α２との軸比を有する式（３）で表される楕円のうち、その面積が最大となるような楕円である共通ＥＤＷ１５ｂを決定する。この共通ＥＤＷ１５ｂはレジストパターンの作製に用いる露光量およびフォーカスの各設定値が存在する領域である設定値存在領域を示している。そして、この共通ＥＤＷ１５ｂである楕円の中心１５ｃによって決定される露光量およびフォーカスをレジストパターン作製の露光量設定値１６およびフォーカス設定値１７とし、露光してレジストパターンを作製する。
【００５８】
この共通ＥＤＷ１５ｂの中心における各パターンのレジスト線幅は、孤立ライン領域１２では０．１５６μｍ、０．４２μｍピッチ領域１３では０．１４９μｍ、０．８０μｍピッチ領域１４では０．１５１μｍとなる。レジストパターン全体を代表するパターン領域として、孤立ライン領域を選んだ場合、０．１５６μｍをねらい線幅とすることになる。
【００５９】
なお、上記の説明では、単純なロジックパターンを例示したが、コンタクトホールパターン、複雑な形状を有するパターンの作製についても適用可能である。
【００６０】
【発明の効果】
以上説明したように本発明では、パターンをパターン密度が略同一とみなせるパターン領域に分割し、パターン領域ごとの設定条件存在領域を決定した後、パターン領域ごとの設定条件存在領域を重ね合わせ、重ね合わせた設定条件存在領域に共通する領域内であって、かつ、面積が最大となるような楕円形状の設定値存在領域を決定し、設定値存在領域が示す楕円の中心から決定される露光量およびフォーカスの値を露光量設定値およびフォーカス設定値とし、露光によってレジストパターンを作製する。
【００６１】
これにより、各パターン領域に共通の露光量およびフォーカスの設定値が存在する領域を求めることができ、さらに、その設定値が存在可能である最大領域を求めることができる。
【００６２】
したがって、形成するパターンにパターン密度の異なる領域が存在する場合であっても、すべての領域に適用可能な設定値を得ることができるとともに、レジストパターン作製時の露光量やフォーカスの変動に対する余裕度を大きくとることができる。これにより、形成したパターンの線幅がスペックから外れる確率は低くなるので、スペック内のパターンを高い歩留まりで作製することができるようになる。
【図面の簡単な説明】
【図１】露光量およびフォーカスの各設定値の設定方法を説明する図であり、（ａ）は作製パターン、（ｂ）は分割したパターン領域、（ｃ）は各パターン領域の設定条件存在領域、（ｄ）はＥＤＷをそれぞれ示している。
【図２】決定された設定条件存在領域のひとつの例を示す図である。
【図３】（ａ）各領域の設定条件存在領域についてＥＤＷを作成した場合と、（ｂ）各領域の共通設定条件存在領域に対して共通ＥＤＷを作成した場合とを示す図である。
【図４】ＤＲＡＭゲートパターンのＥＤＷを示す図である。
【図５】ロジックゲートパターンの光近接効果補正後のレジスト線幅を示す図である。
【図６】ロジックゲートパターンの共通ＥＤＷを示す図である。
【図７】ＥＤＷを利用した露光量およびフォーカス条件の設定方法を説明する図である。
【符号の説明】
１……パターン、２……パターン孤立領域、３……パターン密集領域、４……パターン集合領域、２ａ，３ａ，４ａ……設定条件存在領域、２ｂ，３ｂ，４ｂ……ＥＤＷ、２ｃ，３ｃ，４ｃ，５ｃ……中心、５ａ……共通設定条件存在領域、５ｂ……共通ＥＤＷ、６……露光量設定値、７……フォーカス設定値。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a resist pattern manufacturing method, and more particularly to a pattern manufacturing method for preparing a resist pattern by optimizing conditions in a lithography process.
[0002]
[Prior art]
With the progress of miniaturization and high integration of semiconductor integrated circuits in recent years, there is a demand for miniaturization and high density of resist patterns to be produced by a lithography process.
[0003]
Photolithography is widely used as a lithography technique in such a semiconductor manufacturing process.
For the production of fine patterns by photolithography, shortening the wavelength of the exposure light source, using a projection lens with a large numerical aperture (NA) indicating the brightness of the lens, developing a high-resolution resist, super-resolution technology, etc. Has been studied and put into practical use.
[0004]
However, even when such a technique is used, in the production of a fine pattern in the lithography process, the deviation of the exposure amount from the set value due to the performance of the apparatus, the performance of the lens, the deviation of the substrate to be exposed, and the smoothness in the substrate There may be a case where a deviation from the focus setting value due to a difference in the degree occurs. Furthermore, with the miniaturization of the resist pattern, the margin with respect to the exposure amount and the set value of the focus becomes smaller, the yield decreases, and the chip manufacturing cost increases.
[0005]
Therefore, a method for producing a resist pattern by using an exposure-defocus window (EDW) indicating a relationship between an exposure amount used for production and a focus in producing a resist pattern in a lithography process has been proposed.
[0006]
FIG. 7 is a diagram for explaining a method for setting an exposure amount and a focus condition using EDW.
In FIG. 7, the horizontal axis indicates the exposure amount, and the vertical axis indicates the focus.
[0007]
Further, FIG. 7 shows a setting in which an exposure amount and focus setting conditions necessary for producing a resist pattern having a line width within the specification can exist in the exposure amount and focus when producing a resist pattern. A condition existence area 101 is shown.
[0008]
For example, when the exposure amount for producing the resist pattern is fixed to the exposure amount M, possible focus setting values obtained from the setting condition existence region 101 are in the range from the focus N1 to the focus N2. That is, when the focus value at the exposure amount M falls below the focus N1 or exceeds the focus N2, the actual line width of the pattern to be formed deviates from the desired line width specification.
[0009]
On the other hand, when the focus for producing the resist pattern is fixed to the focus N, the set value of the possible exposure amount obtained from the setting condition existence region 101 is in the range from the exposure amount M1 to the exposure amount M2. That is, when the value of the exposure amount at the focus N falls below the exposure amount M1, or exceeds the exposure amount M2, the actual line width of the formed pattern deviates from the desired line width specification.
[0010]
The setting condition existence region 101 is determined in consideration of the specifications of the product that is a range determined by the allowable upper limit value and the allowable lower limit value of the pattern line width that is finally formed after the resist pattern is manufactured.
[0011]
In the lithography process, an EDW 102 indicated by a graphic such as a rectangle is created inside the setting condition existence area 101. Then, a condition for maximizing the EDW 102 is found, and a resist pattern is produced under the condition. Conventionally, the intended line width of this resist pattern has been made the same as the design value of the pattern to be produced.
[0012]
[Problems to be solved by the invention]
However, there is a problem that the EDW 102 is reduced by making the target line width the same as the design value.
[0013]
Furthermore, a resist pattern such as a logic gate layer manufactured by a lithography process has a mixture of a sparse part and a dense part. Therefore, conventionally, first, the pattern to be formed is divided into pattern regions where the pattern density can be regarded as almost the same, and a condition for maximizing the common EDW 102 for these divided patterns is found, and a resist pattern is produced under these conditions. It was. At that time, the exposure setting value 104 and the focus setting value 105 for producing a pattern representing the entire pattern as designed are determined.
[0014]
Therefore, for example, when a sparse pattern portion is selected as a pattern region representing the entire pattern to be formed, a pattern within the specification can be produced for a sparse portion in the formed pattern. The dense portion in the formed pattern cannot always produce a pattern as designed, and there are cases where it is out of specification. Similarly, when a dense pattern part is selected in the pattern area that represents the entire pattern to be formed, a pattern within the spec can be produced for a sparse part in the formed pattern. There are cases where dense parts in the pattern are out of spec.
[0015]
That is, in the lithography process, there is a problem in that the line width of the formed pattern is out of the specification and the yield is lowered depending on how to select a pattern region that represents the entire pattern to be formed.
[0016]
The present invention has been made in view of these points, and an object of the present invention is to provide a resist pattern manufacturing method that optimizes resist pattern manufacturing conditions in a lithography process and improves yield.
[0017]
[Means for Solving the Problems]
According to the present invention, in a resist pattern production method for producing a resist pattern by a photolithography process, a pattern is divided into pattern areas that can be regarded as having substantially the same pattern density, and pattern area exposure necessary for producing a resist pattern for each pattern area Determine the setting condition existence area, which is the area where the setting condition of the amount and the pattern area focus necessary for creating the resist pattern for each pattern area can exist, and overlay the setting condition existence area for each pattern area Within the area common to the set condition existing area, and the area is the maximum Oval shape like Determine the setting value existence area and set value existence area Ellipse The exposure amount determined from the center of the exposure value is used as the exposure amount setting value used for the production of the resist pattern. Oval Provided is a resist pattern manufacturing method characterized in that a focus determined from the center is used as a focus setting value used for manufacturing a resist pattern, and a resist pattern is manufactured by exposure using an exposure amount setting value and a focus setting value. .
[0018]
According to the above configuration, the pattern is divided into pattern areas that can be regarded as having substantially the same pattern density, and the pattern area exposure amount and pattern area focus setting conditions necessary for the preparation of the resist pattern for each pattern area can exist. A certain setting condition existence area is determined, these setting condition existence areas are overlapped, and the area is within the area common to the overlapped setting condition existence area and has the maximum area. Oval shape like Since the set value existence area is determined, an area where the exposure value and focus set value common to each pattern area exists is obtained.
[0019]
Further, since the set value existence area is created so that the area is maximized, the exposure amount and the focus set value common to each pattern area, and the maximum area where the set value can exist is obtained. It is done.
[0020]
Also, the setting value existence area Ellipse Since the exposure amount and focus determined from the center of the region are set as the exposure amount setting value and the focus setting value for producing the resist pattern, the setting value common to the setting condition existing region of each pattern region can exist. Furthermore, since the center value is indicated and the resist pattern is prepared using the exposure setting value and the focus setting value determined from this center, even if there is a deviation in the actual exposure amount or focus, There is a low probability that the exposure amount and focus during pattern production will deviate from the values in the set value existence region.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a description will be given of the shape of the EDW indicating the set value existence area where the exposure amount set value and the focus set value exist.
[0022]
The performance of the exposure apparatus used for producing the resist pattern, the flatness of the underlying substrate for producing the resist pattern, and the variation in exposure amount and focus caused by the deviation of the underlying substrate can be approximated by a normal distribution. When the exposure amount is X and the standard deviation of the variation of the exposure amount X is α1, the existence probability Z1 (Z1 <1) of the exposure amount setting value can be expressed by the following equation (1).
[0023]
[Expression 1]

[0024]
Further, when the focus is Y and the standard deviation of the variation in focus Y is α2, the focus setting value existence probability Z2 (Z2 <1) can be expressed by the following equation (2).
[0025]
[Expression 2]

[0026]
The existence probability that the exposure amount setting value and the focus setting value exist simultaneously is obtained by multiplying the exposure amount existence probability Z1 shown in Equation (1) by the focus setting value existence probability Z2 shown in Equation (2). Can be obtained. After multiplying the existence probability Z1 and the existence probability Z2, the logarithm is taken for both sides of the obtained equation to obtain the following equation (3).
[0027]
[Equation 3]

[0028]
Therefore, the existence probability that the exposure amount setting value and the focus setting value represented by Expression (3) exist simultaneously is represented by an ellipse in which the ratio of the exposure amount direction radius to the focus direction radius is α1 to α2. The exposure amount setting value and the focus setting value can be determined using an elliptical EDW as the exposure amount setting value indicated by the center of the ellipse, and the focus indicated by the center of the ellipse is determined as the focus setting value. can do.
[0029]
Next, in an area where there can be a setting condition for the pattern area exposure, which is the exposure necessary to produce the desired resist pattern, and the pattern area focus, which is the focus necessary to produce the desired resist pattern. A certain setting condition existence area will be described.
[0030]
The setting condition existence region is determined in consideration of specifications as a product that is a range determined by the allowable upper limit value and the allowable lower limit value of the pattern line width that is finally formed after the resist pattern is manufactured.
[0031]
FIG. 2 is a diagram showing an example of the determined setting condition existence area.
For example, when the exposure amount for producing the resist pattern is fixed to the exposure amount M, possible focus setting values obtained from the setting condition existence region 20 are in the range from the focus N1 to the focus N2. That is, when the focus value at the exposure amount M falls below the focus N1 or exceeds the focus N2, the actual line width of the pattern to be formed deviates from the desired line width specification.
[0032]
On the other hand, when the focus for producing the resist pattern is fixed at the focus N, the set value of the possible exposure amount obtained from the setting condition existence region 20 is in the range of the exposure amount M1 to the exposure amount M2. That is, when the value of the exposure amount at the focus N falls below the exposure amount M1, or exceeds the exposure amount M2, the actual line width of the formed pattern deviates from the desired line width specification.
[0033]
As described above, in consideration of the resist pattern production environment and production conditions, the exposure amount M and the focus N necessary for forming the pattern having the target line width are investigated and the set condition existing region before the resist pattern production. To decide.
[0034]
Next, a method for setting the exposure setting value and the focus setting value used for resist pattern production will be described.
FIG. 1 is a diagram for explaining a method for setting each setting value of exposure amount and focus. (A) is a production pattern, (b) is a divided pattern area, (c) is a setting condition existence area for each pattern area, (D) shows EDW, respectively.
[0035]
In FIG. 1, the horizontal axis represents the exposure amount, and the vertical axis represents the focus.
First, the pattern 1 to be manufactured shown in FIG. 1A is divided into pattern regions that can be regarded as having almost the same pattern density in consideration of a portion where the pattern 1 is sparse and a portion where the pattern 1 is dense. Here, as shown in FIG. 1B, a pattern isolated region 2 which is a region where lines are isolated, a pattern dense region 3 which is a region where patterns are densely formed, and a pattern isolated region 2 The pattern is divided into the pattern collection area 4 which is an area where the patterns are gathered in the middle of the pattern dense area 3.
[0036]
Next, as shown in FIG. 1C, a pattern which is an exposure amount necessary to produce a desired resist pattern for each of the divided pattern isolated region 2, the pattern dense region 3, and the pattern aggregate region 4. The setting condition existence areas 2a, 3a, and 4a, which are areas where the setting conditions of the area exposure amount and the pattern area focus, which is a focus necessary for producing a desired resist pattern, can exist are set as the resist pattern to be produced. Considering the line width, the performance of the exposure apparatus, the flatness of the base substrate, and the specifications of the product as a range that is determined by the allowable upper limit value and allowable lower limit value of the pattern line width that is finally formed after the resist pattern is manufactured And decide.
[0037]
Further, as shown in FIG. 1 (d), the set condition existence areas 2a, 3a, 4a determined for each of the pattern isolated area 2, the pattern dense area 3, and the pattern aggregate area 4 are all overlapped and overlapped. A common setting condition existence area 5a which is a setting condition existence area is created.
[0038]
Within the common setting condition existence area 5a common to all pattern areas included in this common setting condition existence area 5a, and the axial ratio between the standard deviation α1 of the variation in exposure amount and the standard deviation α2 of the variation in focus Among the ellipses represented by the equation (3) having the following, an elliptical common EDW 5b having the largest area is determined. The common EDW 5b indicates a set value existence area, which is an area in which the exposure amount and focus set values used for producing the resist pattern exist. Then, the exposure amount and focus determined by the center 5c of the ellipse indicating the common EDW 5b are set as an exposure amount setting value 6 and a focus setting value 7 for resist pattern production.
[0039]
The common EDW 5b is a central area of the common setting condition existence area 5a, which is an area where an exposure amount and a focus setting condition necessary for producing a desired resist pattern exist, and is used when an actual resist pattern is produced. The margin of allowance for deviation from the values indicated by the exposure amount and the center 5c of the focus is shown. In other words, even if the exposure amount or focus is deviated when the resist pattern is produced, if the deviated exposure amount or focus value is within the EDW 5b, the line width of the produced pattern can be sufficiently suppressed within the specifications.
[0040]
Of course, for a certain pattern area, for example, the pattern isolated area 2, if the exposure amount or focus shift at the time of producing the resist pattern is within the setting condition existence area 2 a determined for this pattern isolated area 2, The included patterns are kept within the spec. The same applies to the pattern dense area 3 and the pattern aggregate area 4.
[0041]
FIG. 3 is a diagram showing (a) a case where an EDW is created for a set condition existing area in each area and (b) a case where a common EDW is created for a common set condition existing area in each area.
[0042]
Looking at each of the pattern isolated region 2, the pattern dense region 3, and the pattern set region 4, the EDWs 2b, 3b, and 4b produced for the setting condition existence regions 2a, 3a, and 4a shown in FIG. When the centers 2c, 3c, 4c of the ellipse and the center 5c of the common EDW 5b of each region shown in FIG. 3B are applied to the setting condition existence regions 2a, 3a, 4a of each region, the center of each region 2c and the center 5c, the center 3c and the center 5c, and the center 4c and the center 5c are different from each other. That is, the exposure amount and the focus determined as the set values are different between the case where they are determined using the EDWs 2b, 3b and 4b and the case where they are determined using the common EDW 5b.
[0043]
As in the prior art, any one of the pattern isolated area 2, the pattern dense area 3, and the pattern aggregate area 4 shown in FIG. 3A, for example, the pattern isolated area 2 is used as a pattern area representing the entire resist pattern. When selected, the center 2c of the EDW 2b created in the selected pattern isolated region 2 does not coincide with the centers 3c and 4c of the EDWs 3b and 4b created in other pattern regions. As a result, the exposure amount setting value and the focus setting value determined from the center 2c of the EDW 2b created in the selected pattern isolated region 2 are set to the setting condition existence region 3a of the pattern dense region 3 which is another pattern region, In some cases, the pattern collection area 4 may be out of the set condition existence area 4a.
[0044]
On the other hand, the center 5c of the common EDW 5b shown in FIG. 3B is always in the set condition existence areas 2a, 3a, and 4a of the pattern isolated area 2, the pattern dense area 3, and the pattern aggregate area 4, so An exposure amount setting value 6 and a focus setting value 7 that can be used in common for the entire resist pattern to be formed and that can form a resist pattern for forming a pattern having a line width within the specification are obtained. Can do.
[0045]
As described above, the pattern is divided into the pattern isolation region 2, the pattern dense region 3, and the pattern collection region 4, and the setting condition existence regions 2a, 3a, and 4a are determined for each region, and the setting condition existence region is determined. 2a, 3a, and 4a are overlapped to create a common setting condition existence area 5a. Then, a common EDW 5b is determined in the common setting condition existence area 5a, and an exposure amount determined by an ellipse center 5c indicating the common EDW 5b and The focus is set to an exposure amount setting value 6 and a focus setting value 7 for resist pattern production.
[0046]
As a result, even if there are regions having different pattern densities in the pattern 1 to be produced, the exposure setting value 6 and the focus setting value 7 determined from the common EDW 5b are common to the entire resist pattern. In addition, since the area of the common EDW 5b is determined to be maximized, a pattern within the specification can be manufactured with a high yield.
[0047]
Next, the case where the embodiment of the present invention is applied to the production of a DRAM (Dynamic Random Access Memory) gate pattern having a gate length of 0.18 μm will be described as an example. Here, a case where the gate pitch, which is the distance between the gate lines of the DRAM gate pattern, is 0.42 μm will be described.
[0048]
In producing the DRAM gate pattern, first, a resist is applied, post-baking is performed at a temperature of 90 ° C. for 60 seconds, and then exposure is performed. After exposure, post-exposure baking at a temperature of 100 ° C. for 90 seconds is performed, paddle development is performed for 60 seconds, and after pure water rinsing, pre-baking is performed at a temperature of 90 ° C. for 60 seconds. Next, after the resist pattern is produced, the portion not masked by the resist is etched.
[0049]
In the fabrication of the DRAM gate pattern proceeding in this manner, the etching conversion difference, which is the amount that the gate line is scraped from the outer edge of the masked resist to the inside of the pattern during the etching after the resist pattern fabrication, is 0.02 μm. I know it exists. Therefore, in order to set the gate line width to the target of 0.18 μm, it is necessary to set the resist line width to 0.20 μm in advance in consideration of the etching conversion difference that is removed by the etching after the formation of the resist pattern.
[0050]
FIG. 4 is a diagram showing an EDW of a DRAM gate pattern.
In FIG. 4, the resist design line width in consideration of the etching conversion difference is set to 0.20 μm, and the resist line width specification is set to 0.20 ± 0.02 μm with respect to the design line width. The existence area 8 is determined. In the created setting condition existence region 8, a design exposure amount that is a design value of an exposure amount that can produce a resist line width of 0.20 μm with a focus of 0 μm, that is, a best focus is determined. This design exposure and best focus are indicated by point P.
[0051]
Here, the standard deviation of the exposure amount variation of the exposure apparatus is 1.0 mJ / cm. ² The standard deviation of the variation in focus is 0.2 μm, and the elliptical shape in which the axial ratio, which is the ratio of the major axis to the minor axis, is 1.0 to 0.2 in the set condition existence region 8 with the point P as the center. EDW9 can be created.
[0052]
On the other hand, when the EDW 10 having an elliptical shape with an axial ratio of 1.0 to 0.2 in the setting condition existence area 8 and having the largest area is determined, the exposure amount setting indicated by the point Q that is the center of the EDW 10 is determined. The line width of the resist pattern produced by the value and the focus setting value is 0.207 μm. The area of the EDW 10 determined in this way is larger than the area of the EDW 9 whose design line width is in the center. Therefore, instead of the design line width of 0.20 μm, the resist pattern is formed by setting the target line width of 0.207 μm to the lithography process. The probability that the line width of the pattern to be formed deviates from the specification becomes low.
[0053]
On the other hand, when a resist pattern is manufactured with a target line width of 0.20 μm as in the prior art, since the EDW 9 is small, it deviates from the design line width due to exposure amount and focus fluctuations during the resist pattern preparation. The probability that the line width of the pattern to be formed will deviate from the specification increases, and as a result, the yield is expected to decrease.
[0054]
Next, the case where the embodiment of the present invention is applied to the production of a logic gate pattern having a gate length of 0.15 μm will be described as an example.
FIG. 5 is a diagram showing the resist line width after the optical proximity effect correction of the logic gate pattern.
[0055]
First, the logic gate pattern 11 to be formed is divided into the isolated line region 12, the 0.42 μm pitch region 13, and the 0.80 μm pitch region 14. These patterns must be produced with the same exposure amount. Therefore, optical proximity effect correction is performed. By the optical proximity correction, the isolated line region 12 has a line width of 0.15 μm, the 0.42 μm pitch region 13 has a line width of 0.155 μm, and the 0.80 μm pitch region 14 has a mask line width of 0.17 μm. A resist pattern is produced with a pattern. In addition, there is no etching conversion difference that is the amount that the gate line is scraped from the outer edge of the masked mask to the inside of the pattern at the time of etching after the formation of the resist pattern, and the target line width of the resist pattern is all The pattern is 0.15 μm.
[0056]
FIG. 6 is a diagram showing a common EDW of logic gate patterns.
Setting condition existence regions 12a, 13a, and 14a are determined and set for each of the isolated line region 12, the 0.42 μm pitch region 13, and the 0.80 μm pitch region 14 with a line width specification of 0.15 ± 0.015 μm. The condition existing areas 12a, 13a, and 14a are overlapped to determine the common setting condition existing area.
[0057]
Of the ellipses represented by the equation (3) within the common setting condition existence area and having an axial ratio between the standard deviation α1 of the variation in exposure amount and the standard deviation α2 of the variation in focus, the area thereof is The common EDW 15b that is an ellipse that maximizes is determined. The common EDW 15b indicates a set value existence area, which is an area where the exposure amount and the focus set values used for producing the resist pattern exist. Then, the exposure amount and focus determined by the center 15c of the ellipse that is the common EDW 15b are set as the exposure amount setting value 16 and the focus setting value 17 for forming the resist pattern, and exposure is performed to prepare a resist pattern.
[0058]
The resist line width of each pattern at the center of the common EDW 15 b is 0.156 μm in the isolated line region 12, 0.149 μm in the 0.42 μm pitch region 13, and 0.151 μm in the 0.80 μm pitch region 14. When an isolated line region is selected as a pattern region representing the entire resist pattern, the target line width is 0.156 μm.
[0059]
In the above description, a simple logic pattern is exemplified, but the present invention can also be applied to the production of a contact hole pattern or a pattern having a complicated shape.
[0060]
【The invention's effect】
As described above, in the present invention, the pattern is divided into pattern areas that can be regarded as having substantially the same pattern density, the setting condition existence area for each pattern area is determined, and then the setting condition existence area for each pattern area is overlaid and overlapped. It is in the area common to the combined setting condition existence area and the area is the maximum Oval shape like Determine the setting value existence area and set value existence area Ellipse Using the exposure amount and focus value determined from the center of the exposure amount as the exposure amount setting value and the focus setting value, a resist pattern is produced by exposure.
[0061]
Thus, it is possible to obtain an area where there is a common exposure amount and focus setting value in each pattern area, and it is possible to obtain a maximum area where the setting value can exist.
[0062]
Therefore, even if there are regions with different pattern densities in the pattern to be formed, it is possible to obtain set values applicable to all regions, and allowance for variations in exposure amount and focus during resist pattern fabrication Can be greatly increased. As a result, the probability that the line width of the formed pattern deviates from the spec is reduced, and thus the pattern within the spec can be manufactured with a high yield.
[Brief description of the drawings]
FIGS. 1A and 1B are diagrams illustrating a method for setting exposure value and focus setting values, where FIG. 1A is a production pattern, FIG. 1B is a divided pattern area, and FIG. 1C is a setting condition existence area for each pattern area; , (D) show EDW, respectively.
FIG. 2 is a diagram illustrating an example of a determined set condition existence region.
FIGS. 3A and 3B are diagrams showing a case where an EDW is created for a setting condition existence area of each area, and a case where a common EDW is created for a common setting condition existence area of each area.
FIG. 4 is a diagram showing an EDW of a DRAM gate pattern.
FIG. 5 is a diagram showing a resist line width after optical proximity effect correction of a logic gate pattern.
FIG. 6 is a diagram showing a common EDW of logic gate patterns.
FIG. 7 is a diagram illustrating a method for setting an exposure amount and a focus condition using EDW.
[Explanation of symbols]
1... Pattern 2. , 4c, 5c... Center, 5a... Common setting condition existence area, 5b... Common EDW, 6... Exposure amount setting value, 7.

Claims (4)

In a resist pattern production method for producing a resist pattern by a photolithography process,
Divide the pattern into pattern areas where the pattern density can be regarded as substantially the same,
Setting condition existence area which is an area where a setting condition of a pattern area exposure amount necessary for producing the resist pattern for each pattern area and a pattern area focus necessary for producing the resist pattern for each pattern area can exist. Decide
Superimposing the setting condition existence area for each pattern area,
Determine an elliptical set value existence area that is within the area common to the overlapped setting condition existence area and has the largest area,
The exposure amount determined from the center of the ellipse indicated by the set value existing area is set as the exposure amount setting value used for the preparation of the resist pattern, and the focus determined from the center of the ellipse is used for the preparation of the resist pattern. age,
Creating the resist pattern by exposure using the exposure setting value and the focus setting value ;
Resist pattern manufacturing method. The ellipse is
  The ratio between the standard deviation of the exposure amount at the time of producing the resist pattern and the standard deviation of the focus is the ratio between the major axis and the minor axis, or the ratio between the minor axis and the major axis.
  The resist pattern preparation method according to claim 1. The resist pattern is
  A pattern portion etching amount, which is an amount of a pattern portion masked with the resist pattern being simultaneously etched in an etching process after the formation of the resist pattern, is added to the design line width of the resist pattern in advance.
  The resist pattern preparation method according to claim 1. A lithography process management method for managing the lithography process using the resist pattern manufacturing method according to claim 1.

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