JP4659621B2 - Wireless transmitter - Google Patents

Description

  The present invention relates to a wireless transmitter having a function of correcting a timing shift between an I phase and a Q phase generated in an analog quadrature modulator.

  A conventional wireless transmitter in a mobile communication system such as a W-CDMA (Wideband-Code Division Multiple Access) system is configured as shown in FIG.

  In FIG. 14, reference numeral 11 denotes a digital modulation unit which performs band limitation on an input baseband signal, up-sampling to a desired sampling frequency, digital quadrature modulation to each carrier frequency, and multicarrier synthesis. The signal digitally modulated by the digital modulator 11 is converted to an analog signal by the D / A converter 12 and sent to the analog quadrature modulator 13. The analog quadrature modulator 13 up-converts the output signal of the D / A converter 12 to a target RF (Radio Frequency) frequency band and outputs a modulated wave signal in the RF band. This RF band modulated wave signal is amplified by the power amplifier 14 and transmitted to the outside from an antenna (not shown).

  FIG. 15 shows a configuration example of the digital modulation unit 11 in FIG. The digital modulation unit 11 includes band limiting filters 111a to 111n, up-sampling filters 112a to 112n, digital quadrature modulation units 113a to 113n, and a multicarrier synthesizer 114.

  The band limiting filters 111a to 111n perform band limitation on the input baseband signal corresponding to each carrier. The signals output from the band limiting filters 111a to 111n are upsampled by the upsample filters 112a to 112n, sent to the digital quadrature modulation units 113a to 113n, and digital quadrature modulation (complex frequency conversion) to different carrier frequencies. Is done. The N signals frequency-converted by the digital quadrature modulation units 113a to 113n are synthesized by the multicarrier synthesizer 114 and output.

  As described above, a wireless transmitter using a digital modulation method such as the W-CDMA method is configured using the analog quadrature modulator 13.

  The analog quadrature modulator 13 has a problem that when the timings of the I (In-phase) phase and the Q (Quadrature) phase are shifted, the modulation accuracy is deteriorated, the transmission signal is distorted, and the signal quality is deteriorated.

  It is sufficient to use a high-precision analog quadrature modulator that does not cause a difference in timing between the I phase and the Q phase, but such an analog quadrature modulator is usually expensive, and costs are high when mass-producing radio transmitters. End up.

For this reason, in a conventional radio transmitter, for example, an I-signal suppression filter and a Q-signal suppression filter are provided before the quadrature modulator, and a delay correction circuit is provided on the output side of each suppression filter. The quality of the transmitted signal can be improved even when a simple analog quadrature modulator is used by correcting the signal so that there is no delay time difference between the I signal and Q signal and performing quadrature modulation on the corrected signal. (For example, refer to Patent Document 1).
JP-A-11-46222

  However, in the conventional method in which the delay correction circuit is provided to correct the delay time difference between the I signal and the Q signal and then input to the analog quadrature modulator to perform quadrature modulation, the delay time difference between the I signal and the Q signal is reduced. For example, since it is necessary to perform measurement using an expensive network analyzer and adjust the circuit constant of the delay correction circuit based on the measurement result, adjustment of the delay correction circuit is very troublesome.

  The present invention has been made to solve the above-described problems. By providing a timing detection means for I and Q signals, timing adjustment between IQs can be easily performed, and an inexpensive analog quadrature modulator is provided. An object of the present invention is to provide a wireless transmitter capable of transmitting a high-quality signal with reduced distortion even when used.

The wireless transmitter according to the present invention affine-transforms the digitally modulated complex IF signals I (t) and Q (t) based on the affine transformation coefficients, and outputs compensated signals a (t) and b (t). To adjust the timing between IQs by giving a delay to the I phase or the Q phase by using an FIR filter for the affine transformation unit that performs and the compensated signals a (t) and b (t) output from the affine transformation unit An IQ timing adjustment unit, a D / A converter that converts the signal output from the IQ timing adjustment function unit from digital to analog, and outputs the signal, and a carrier signal is orthogonally modulated based on the output signal of the D / A converter an analog quadrature modulator for outputting an RF signal, a power amplifier and output the power-amplifying the RF signal output from the analog quadrature modulator, the output signal of the power amplifier A frequency converting unit for converting to the F frequency band, a band limiting filter for performing band limiting on the IF signal frequency-converted by the frequency converting unit, and converting the IF signal output from the band limiting filter from analog to digital A / D converter that outputs the signal and digital quadrature detection of the output signal of the A / D converter, and complex feedback signals I ′ (t) and Q ′ (t) having an IF frequency substantially equal to that of the digital modulation unit A digital quadrature detection unit that outputs a linear distortion remaining in the complex feedback signals I ′ (t) and Q ′ (t) as a distortion coefficient, and the current affine transformation according to an update equation including the distortion coefficient A control unit that updates a coefficient to a new affine transformation coefficient and resets the coefficient to the affine transformation unit, and a timing between IQs by an output signal of the digital quadrature detection unit An IQ timing shift detection unit that detects a shift of the output signal separately from an IQ orthogonality shift and outputs a control signal to the IQ timing adjustment unit to adjust a timing shift between IQs. To do.

  According to the present invention, by providing a timing adjustment function between IQs with respect to an output signal of a digital modulation unit, it is possible to eliminate distortion generated due to a shift in timing between IQs in an analog unit such as an analog quadrature modulator. It is possible to transmit a high-quality signal without distortion.

  In addition, after the distortion compensation is performed on the output signal of the digital modulation unit by the affine converter, the timing deviation during IQ is further adjusted by the IQ timing adjustment unit, so that distortion remains only by the processing of the affine converter. Even in such a case, distortion generated in an analog unit such as an analog quadrature modulator can be reliably removed, and a higher quality signal can be obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
In the present embodiment, the present invention is applied to, for example, a wireless transmitter (wireless base station) that transmits a 4-carrier W-CDMA (Wide-Code Division Multiple Access) signal.

  FIG. 1 is a block diagram showing a configuration of a wireless transmitter according to the first embodiment of the present invention, and shows only a transmission system after baseband processing.

  In FIG. 1, reference numeral 21 denotes a digital modulation unit, which performs band limitation on four input baseband signals, up-sampling to a desired sampling frequency, digital quadrature modulation to each carrier frequency, and multi-carrier synthesis. . The signal digitally modulated by the digital modulation unit 21 is converted into an analog signal by the D / A converter 22 and sent to the IQ timing adjustment unit 23. The IQ timing adjusting unit 23 adjusts the timing between the I signal and the Q signal, and details thereof will be described later. The signal whose timing is adjusted by the IQ timing adjusting unit 23 is sent to the analog quadrature modulator 24. The analog quadrature modulator 24 up-converts the signal adjusted by the IQ timing adjustment unit 23 to a target RF frequency band, and outputs a modulated wave signal in the RF band. This RF band modulated wave signal is amplified by the power amplifier 25 and transmitted to the outside from an antenna (not shown).

  Next, details of each part will be described. In the present embodiment, since the digital modulation unit 21 is equivalent to 11, refer to FIG.

A digital complex baseband signal (IQ signal) having a sampling rate of a chip rate (3.84 MHz) is input to the digital modulator 21 for four carriers. Each digital complex baseband signal is a composite signal of a plurality of channels multiplexed with a spreading code, and each channel is power-controlled and has a different amplitude, so each digital complex baseband signal has an arbitrary value on the IQ plane. Can take. Each digital complex baseband signal is first subjected to filtering of the root roll-off characteristic individually for the I and Q components by the band limiting filters 111a to 111d which are FIR filters. Next, 0 is inserted by the up-sampling filters 112a to 112d, the sampling frequency is oversampled to 122.88 MHz (32.times.3.84 MHz), and the image component is removed. Next, the outputs (IQ signals) of the up-sample filters 112a to 112d are expressed by (cos (2πf _i ), sin (2πf _i )), (i = 1... 4) by the digital quadrature modulators 113a to 113d. Complex multiplication is performed on each of the complex local signals. Since complex multiplication is performed, no new image is generated by this, and the frequency is simply converted to the IF band. For example, f1 to f4 are arranged at a frequency of about 30 MHz or less with a detuning of 5 MHz. Next, the complex multiplication output (IQ signal) of each carrier is synthesized additively.

  The IQ signal (digital signal) output from the digital modulation unit 21 is converted into an analog signal by the D / A converter 22 and sent to the IQ timing adjustment unit 23.

The IQ timing adjustment unit 23 is configured as shown in FIG.
The IQ timing adjustment unit 23 shown in FIG. 2 shows an analog system that adjusts the timing between IQs by increasing the I-phase or Q-phase conductor length with respect to the output signal of the D / A converter 22. It is. Various methods are conceivable for adjusting the timing between IQs by changing the conductor length, and FIG. 2 shows an example thereof.

  In FIG. 2, 31a and 31b are input terminals to which I-phase and Q-phase signals output from the D / A converter 22 are input. Cables 32a and 32b are connected to the input terminals 31a and 31b, respectively. On the analog quadrature modulator 24 side, wirings 33 and 34 are provided on the substrate so that the conductor lengths to the analog quadrature modulator 24 are sequentially different in a certain length unit L for both the I phase and the Q phase. In addition, connectors 35a to 35d and 36a to 36d are provided at the respective tips so that the cables 32a and 32b can be connected. For example, if the time for the signal to flow through the lead wire of length L is T, when the I-phase side cable 32a is connected to the connector 35b, the signal timing is delayed by the time T as compared to the analog time delay. Input to the quadrature modulator 24.

  Therefore, if the I-phase side cable 32a is connected to the connector 35b and the Q-phase side cable 32b is connected to the connector 36a, the I-phase is only time T with respect to the Q-phase when input to the analog quadrature modulator 24. The timing is delayed. Conversely, when it is desired to delay the Q phase relative to the I phase by a time T, the I phase side cable 32a may be connected to the connector 35a and the Q phase side cable 32b may be connected to the connector 36b. As described above, the cables 32a and 32b are connected to the optimally connected connectors 35a to 35d and 36a to 36d, and the IQ timing is adjusted to the optimum value.

  As described above, the IQ timing adjusting unit 23 can adjust the timing between IQs by connecting the cables 32a and 32b to the connectors 35a to 35d and 36a to 36d having optimum wirings. The difference in length between the shortest wiring and the longest wiring in the wirings 33 and 34 to be applied to the substrate may be determined within a range that can sufficiently cover the expected timing shift between IQs. Further, the unit L of the difference between the lengths of the wirings 33 and 34 may be determined depending on the degree of accuracy (time interval) for adjusting the timing deviation. For example, when it is desired to correct distortion due to timing deviation between IQs to a lower level, the value of L is set small. For example, it is set to a value smaller than the length that generates a delay of 1 ns.

  The IQ signal whose timing is adjusted by the IQ timing adjusting unit 23 is sent to the analog quadrature modulator 24 and subjected to analog quadrature modulation. The analog quadrature modulator 24 is realized by, for example, an MMIC (Microwave Monolithic Integrated Circuit). In the system in which the I and Q phases are individually D / A converted and analog quadrature modulation is performed as in this embodiment, a high C / N (Carrier-to-Noise Ratio) can be obtained with inexpensive components.

  Since the analog IF signal has a frequency of 100 MHz or less and is not so high, a relatively inexpensive cable or connector can be used. Specifically, the cable is a small-diameter shield or coaxial cable, and the surface mount type connector can be used. Moreover, since the length of the cable is not changed, the number of parts can be reduced.

  According to the above embodiment, by providing the IQ timing adjustment unit 23, it is possible to eliminate distortion that occurs due to a shift in the timing between IQs in the analog quadrature modulator, and it is possible to transmit a high-quality signal.

(Second Embodiment)
Next, a radio transmitter according to the second embodiment of the present invention will be described.
FIG. 3 is a block diagram showing a configuration of a wireless transmitter according to the second embodiment of the present invention. In the wireless transmitter according to the second embodiment, in the wireless transmitter according to the first embodiment, a feedback system is provided to control the inter-IQ timing adjustment unit so as to automatically adjust the timing deviation of the IQ signal. It is a thing.

  As shown in FIG. 3, the digital modulation unit 21 performs multi-carrier synthesis by performing band limitation, up-sampling to a desired sampling frequency, and digital quadrature modulation for each carrier frequency for an input baseband signal. The signal digitally modulated by the digital modulation unit 21 is converted into an analog signal by the D / A converter 22 and sent to the IQ timing adjustment unit 23A. The IQ timing adjustment unit 23A is output from an IQ timing shift detection unit 46, which will be described later, for example, the connection between the cables 32a and 32b and the connectors 35a to 35d and 36a to 36d in the IQ timing adjustment unit 23 shown in the first embodiment. It is switched electronically by a control signal.

  The signal whose timing is adjusted by the IQ timing adjusting unit 23A is sent to the analog quadrature modulator 24. The analog quadrature modulator 24 up-converts the signal adjusted by the IQ timing adjustment unit 23 to a target RF frequency band, and outputs a modulated wave signal in the RF band. This RF band modulated wave signal is amplified by the power amplifier 25 and transmitted to the outside from an antenna (not shown).

  A part of the signal amplified by the power amplifier 25 is extracted by the coupler 41 and input to the mixer 42 which is a frequency converter of the feedback system. The mixer 42 down-converts the signal amplified by the power amplifier 25 to the IF frequency band. The IF signal down-converted by the mixer 42 is band-limited by the band-limiting filter 43, and frequency components other than the target IF frequency are removed. The analog signal band-limited by the band-limiting filter 43 is converted into a digital signal by the A / D converter 44 and sent to the digital quadrature detection unit 45. The digital quadrature detection unit 45 performs digital quadrature detection on the digital signal converted by the A / D converter 44 and converts it into an IQ signal.

  The IQ signal output from the digital quadrature detection unit 45 is sent to the IQ timing shift detection unit 46. The IQ timing shift detection unit 46 detects the timing shift between the I signal and the Q signal, and based on the detected value, the cables 32a and 32b and the connectors 35a to 35d and 36a to 36d in the IQ timing adjustment unit 23A. The connection is switched and the timings of the I signal and the Q signal are matched.

  Next, details of each part in the feedback system will be described. Since the digital modulator 21, D / A converter 22, IQ timing adjuster 23A, analog quadrature modulator 24, and power amplifier 25 have the same configuration as in the first embodiment, detailed description thereof is omitted.

When a part of the output of the power amplifier 25 taken out by the coupler 41 is input, the mixer 42 multiplies the local signal of the local oscillator (not shown) and down-converts it to the IF frequency. Here, the local oscillator has a different oscillation frequency from that of the local oscillator in the analog quadrature modulator 24. Thereby, the DC offset of the A / D converter 44 and the D / A converter 22 can be distinguished.
Further, the feedback system from the mixer 42 to the IQ timing deviation detection unit 46 needs to have at least the same bandwidth as the transmission system.

  The band limiting filter 43 performs band limitation on the output of the mixer 42 to remove frequency components other than the target IF frequency band. The bandwidth of the target IF frequency band is about ½ of the sampling frequency of the A / D converter 44.

  The A / D converter 44 undersamples the IF analog signal input from the band limiting filter 43 at a sampling frequency of 2 × 66.14 MHz, for example, and converts it into a digital signal.

  The digital quadrature detection unit 45 multiplies the output of the A / D converter 44 by digital local signals cos (2πfb) and sin (2πfb) having a relationship of perfect quadrature and equal amplitude, and the multiplication results are respectively I phase and Q phase. Output as. For example, fb is (1/2) × 66.14 MHz.

Next, details of the IQ timing shift detection unit 46 will be described.
The level of distortion that occurs due to timing deviation between IQs has the property of changing depending on the frequency of the signal to be transmitted. This is because the amount of phase fluctuation in a certain time increases as the frequency of the signal increases from 0 MHz. By utilizing this property and obtaining a correlation coefficient using the I-phase component and the Q-phase component of the feedback signal as sample sequences X and Y, respectively, it is possible to detect a timing shift between IQs.

(A) Definition formula of correlation coefficient ρ for two sample sequences X and Y

(B) Correlation coefficient for unmodulated wave IQ data When no distortion component exists If the amplitude of the unmodulated wave is A, the frequency is f, and ω = 2πf, the IQ component of the unmodulated wave is as follows: I can express.

I = Acos (ωt), Q = Asin (ωt) (3)
Assuming that the sample trains X and Y are the I-phase component and Q-phase component of the unmodulated wave, respectively, and assuming that the number of samples N is sufficiently large, the average value of the sample data represented by Equation (2) is zero. Thereby, the correlation coefficient for the IQ data of the unmodulated wave is

Here, as a property of a sine wave having an amplitude of 1, the following expression (6) is established.

  Since the numerator is a value in the range of −1 to +1, the correlation coefficient ρ is 0 if the number of samples N is sufficiently large.

When orthogonality deviation and IQ delay exist If the orthogonality deviation is φ and IQ delay is τ, the IQ component of the unmodulated wave can be expressed as follows:
I = Acos (ωt), Q = Asin (ω (t + τ) + φ) (9)
Substituting equation (9) into equation (4) to obtain the correlation coefficient,

  Since the first term of equation (10) is 0 if the number of samples N is sufficiently large, ρ = sin (ωτ + φ) is obtained.

(C) Correlation coefficient of modulated wave with IQ data By considering the modulated wave as a composite signal of a number of unmodulated waves of arbitrary frequency ω in the band, the same result as before can be obtained for the modulated wave. I can say that.

(D) Detection of IQ delay Using equation (12), signals are transmitted at _two different frequencies (ω ₁ , ω ₂ ) to obtain respective correlation coefficient values ρ ₁ and ρ ₂ .

ρ ₁ = sin (ω ₁ τ + φ)
ρ ₂ = sin (ω ₂ τ + φ)
By solving the following simultaneous equations, the unknown number φ (orthogonality shift) and τ (IQ delay) can be obtained separately.

を得る。なお、３以上のωとρを用い、最小２乗法によりφとτを求めてもよい。あるいは連立方程式を解くのでは無く、周波数を大きくなるように変化させたときにρが大きくなったときはτを減らし、逆にρが小さくなったときはτを大きくするようにＩＱタイミング調整部を反復的に制御してもよい。 ω ₁ τ + φ = arcsin (ρ ₁ )
ω ₂ τ + φ = arcsin (ρ ₂ )
Solving this

Get. Note that φ and τ may be obtained by a least square method using three or more ω and ρ. Alternatively, instead of solving simultaneous equations, the IQ timing adjustment unit reduces τ when ρ increases when the frequency is increased, and conversely increases τ when ρ decreases. May be iteratively controlled.

  The IQ timing shift detector 46 detects the IQ timing shift as described above, and adjusts the IQ timing adjuster 23A based on the detected value τ.

As shown in the second embodiment, the IQ timing shift detection unit 46 is provided to automatically detect IQ timing shift and automatically adjust timing between IQs without using a spectrum analyzer. Even if an inexpensive analog quadrature modulator is used, distortion can be reduced and a high quality signal can be transmitted. It is particularly suitable for a wideband signal such that Δω | τ _s |> | φ _v | with respect to the bandwidth Δω, the standard orthogonality deviation φ _v and the IQ delay τ _{s of} the analog quadrature modulator.

(Third embodiment)
Next, a third embodiment of the present invention will be described.
FIG. 4 is a block diagram showing a configuration of a wireless transmitter according to the third embodiment of the present invention. The wireless transmitter according to the first embodiment uses the analog IQ timing adjustment unit 23, whereas the wireless transmitter according to the third embodiment uses the digital IQ timing adjustment unit 23 </ b> B. It is a thing. The IQ timing adjustment unit 23B is provided between the digital modulation unit 21 and the D / A converter 22.

  As shown in FIG. 4, the digital modulation unit 21 performs band limitation, up-sampling to a desired sampling frequency, digital quadrature modulation to each carrier frequency, and multi-carrier synthesis for an input baseband signal. .

  The signal digitally modulated by the digital modulation unit 21 is sent to the IQ timing adjustment unit 23B to adjust the timing between IQs. Details of the IQ timing adjustment unit 23B will be described later. The signal whose timing is adjusted by the IQ timing adjusting unit 23B is converted into an analog signal by the D / A converter 22 and then sent to the analog quadrature modulator 24. The analog quadrature modulator 24 up-converts the analog signal D / A converted by the D / A converter 22 to a target RF frequency band, and outputs a modulated wave signal in the RF band. This RF band modulated wave signal is amplified by the power amplifier 25 and transmitted to the outside from an antenna (not shown).

  Next, a detailed configuration of the IQ timing adjustment unit 23B will be described with reference to FIG. In addition, since the structure of each other part is the same structure as 1st Embodiment, detailed description is abbreviate | omitted.

  The IQ timing adjustment unit 23B includes a digital FIR filter in at least one of the I phase and the Q phase, and generates a designated delay in the input signal. A phase having no FIR filter is provided with a delay generation unit that generates a delay equivalent to the processing delay of the FIR filter.

  In the example of FIG. 5, a delay generation FIR filter 231 that generates an arbitrary delay in the I-phase signal, a delay generation unit 232 that generates a delay equivalent to the processing delay of the delay generation FIR filter 231 in the Q-phase signal, A tap coefficient generation unit 233 that provides the delay generation FIR filter 231 with a tap coefficient for generating a delay corresponding to τ in Expression (11).

  Although it is conceivable to use a shift register to change the signal timing in the digital part, the timing deviation between IQs generated in the analog part such as a D / A converter, a filter, an analog quadrature modulator, etc. is from the time width of one sample. Is much smaller, the FIR filter 231 capable of timing variation with an accuracy of less than one sample is used. Unlike the timing adjustment by changing the conducting wire length like the IQ timing adjustment unit 23 of the first embodiment, the FIR filter 231 can delay or advance the timing. Therefore, the FIR filter 231 has the FIR filter 231. Only one of the I phase or Q phase is sufficient. However, considering the processing delay of the filter, a shift register having about half the number of taps of the FIR filter 231 is used for the phase not having the FIR filter 231, for example.

  Here, the tap coefficient of the FIR filter 231 capable of changing the signal timing will be described. As an example, the characteristics of a filter that delays the timing by a time corresponding to 1/4 sample (about 2 nsec at a sampling frequency of 122.88 MHz) will be described. Actually, the inter-IQ timing shift generated in the analog quadrature modulator 24 is a small one less than 1 nsec, but here, in order to make the effect of the timing variation due to the filter easier to see from the figure, a ¼ sample (sampling) is used. A case of a large timing fluctuation (frequency 122.88 MHz) will be described as an example.

  Since the FIR filter 231 for timing adjustment only changes the timing, there is no need to worry about frequency characteristics outside the signal pass band. However, if it is considered to reduce the tap coefficient by reducing the processing delay of the FIR filter 231, the gain outside the passband has such a characteristic that it gradually decreases as shown in the FIR filter transfer function of FIG. Good. FIG. 6 shows the frequency [MHz] on the horizontal axis and the gain [dB] on the vertical axis.

  Next, the tap coefficient of the FIR filter 231 is considered using the impulse response diagram shown in FIG. FIG. 7 is an impulse response curve of the FIR filter 231 having the transfer function shown in FIG. 6. The horizontal axis indicates [sample] and the vertical axis indicates the tap count value. In this impulse response curve, the black point is a tap coefficient when there is no timing variation, and the white point shifted by 1/4 sample from the black point is a tap coefficient when the timing variation is 1/4.

  That is, the tap coefficient generation unit 233 sets tap coefficients that can generate arbitrary timing fluctuations in the FIR filter by calculating tap coefficients by shifting the timing fluctuations to be generated as described above. Next, FIG. 8 shows a time waveform of input / output signals of the FIR filter 231 when a tap coefficient that delays the timing of 1/4 sample is used. In FIG. 8, the horizontal axis represents a sample, and the vertical axis represents the signal level. In FIG. 8, the broken line a indicates the input signal of the FIR filter 231, and the solid line b indicates the output signal of the FIR filter 231, and it can be confirmed that the timing of the filter output signal is accurately delayed by 1/4 sample. .

  By using the digital IQ timing adjustment unit 23B as shown in the third embodiment, the timing between IQs can be arbitrarily adjusted by the tap coefficient, and the occurrence of distortion in the analog quadrature modulator 24 is reduced. A high quality signal can be transmitted.

  Note that FIR filters may be provided for both the I-phase and Q-phase, and may have filter characteristics that compensate for the frequency characteristics of the D / A converter 22 and subsequent analog circuits.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described.
FIG. 9 is a block diagram showing a configuration of a wireless transmitter according to the fourth embodiment of the present invention. In the wireless transmitter according to the fourth embodiment, an affine converter (carrier leak canceller) 51 is provided in front of the IQ timing adjustment unit 23B and a feedback system is provided in the wireless transmitter shown in the third embodiment. The device 51 and the IQ timing adjustment unit 23B are controlled to automatically adjust the deviation of the orthogonality and the timing of the IQ signal.

  The digital modulator 21 performs band limitation on the input baseband signal, up-sampling to a desired sampling frequency, digital quadrature modulation to each carrier frequency, and multi-carrier synthesis.

As shown in FIG. 9, distortion compensation is performed on the signal digitally modulated by the digital modulator 21 by the affine converter 51. The affine transformer 51 is configured as shown in FIG. 10, and by giving a ₀ , b ₀ , α, and θ, the DC offset, IQ gain difference, and quadrature inherent in the analog unit such as the analog quadrature modulator 24 are given. It functions to correct the degree deviation.

  The signal corrected by the affine converter 51 is sent to the IQ timing adjustment unit 23B to adjust the timing between IQs. The signal whose timing is adjusted by the IQ timing adjustment unit 23B is converted into an analog signal by the D / A converter 22 and then sent to the analog quadrature modulator 24. The analog quadrature modulator 24 up-converts the analog signal D / A converted by the D / A converter 22 to a target RF frequency band, and outputs a modulated wave signal in the RF band. This RF band modulated wave signal is amplified by the power amplifier 25 and transmitted to the outside from an antenna (not shown).

  A part of the signal amplified by the power amplifier 25 is extracted by the coupler 41 and input to the mixer 42 which is a frequency converter of the feedback system. The mixer 42 down-converts the signal amplified by the power amplifier 25 to the IF frequency band. The IF signal down-converted by the mixer 42 is band-limited by the band-limiting filter 43, and frequency components other than the target IF frequency are removed. The analog signal band-limited by the band-limiting filter 43 is converted into a digital signal by the A / D converter 44 and sent to the digital quadrature detection unit 45. The digital quadrature detection unit 45 performs digital quadrature detection on the digital signal converted by the A / D converter 44, and complex feedback signals I ′ (t) and Q ′ (t) having substantially the same IF frequency as the digital modulation unit 21. ) Is output.

  The output signal of the digital quadrature detection unit 45 is sent to the IQ timing shift detection unit 46 and the control unit 52. The IQ timing shift detection unit 46 detects the timing shift between the I signal and the Q signal, adjusts the tap coefficient in the IQ timing adjustment unit 23B based on the detected value, and corrects the timing shift between IQs.

  Further, the control unit 52 updates each distortion compensation coefficient used by the affine transformer 51 based on the signal detected by the digital quadrature detection unit 45.

  Hereinafter, an algorithm for updating each distortion compensation coefficient in the control unit 52 will be described. In addition, since the structure of each other part is the structure similar to 2nd and 3rd embodiment, detailed description is abbreviate | omitted.

  In principle, the control unit 52 uses the detection outputs I ′ (t) and Q ′ (t) of the digital quadrature detection unit 45 that are outputs based on the affine transformation coefficients set in the affine transformer 51 at a certain time. Then, the correction error is extracted and drawn into the optimum value with an update formula.

Initial state of n times, the coefficient update by performing the DC offset of the I (t) side determined a _n, Q (t) side of the DC offset to b _n, the IQ gain ratio alpha _n, IQ orthogonality deviation The sine of the angle is set as sin θ _n , the DC offset on the I (t) side remaining in the current digital quadrature detection output is a ′, the DC offset on the Q (t) side is b ′, and the IQ gain ratio is When the sine of α ′ and IQ orthogonality deviation angle is set as sin′θ, the following calculation is performed using the digital quadrature detection outputs I ′ (t) and Q ′ (t).

  First, the phase difference φ between the modulation signal (I (t), Q (t)) and the corresponding digital quadrature detection signal (I ′ (t), Q ′ (t)) is obtained, and the phase Compensate for rotation.

φ = Arg [(I (t) + jQ (t)) (I ′ (t) −jQ ′ (t))] (12)
I _r (t) = I ′ (t) cos φ−Q ′ (t) sin φ (13)
Q _r (t) = Q ′ (t) cos φ + I ′ (t) sin φ (14)
Here, Arg [] represents a complex argument. In the above formulas (12) to (14), the delay in the affine converter 51, the analog quadrature modulator 24, and the mixer 42 is not particularly considered.

  Next, a strain coefficient indicating each residual strain is obtained by the following equation.

a ′ = <I _r (t)> (15)
b ′ = <Q _r (t)> (16)
α ′ = (<I _r (t) ² > / <Q _r (t) ² >) ^1/2 (17)
sin θ ′ = − <I _r (t) Q _r (t)> / {<I _r (t) ² ><Q _r (t) ² >} ^1/2 (18)
Here, <> represents a long-term average value.

  Next, the affine transformation coefficient is updated using the distortion coefficient obtained by Expression (15) to Expression (18).

a _n = a _n−1 −μa ′ (19)
b _n = b _n−1 −μb ′ (20)
α _n = α _n−1 × (α ′) ^{1 / m} (21)
sin θ _n = sin θ _n−1 + μsin θ ′ (22)
(If θ≈0, it can be assumed that sinθ≈θ, so approximation can be used.)
cos θ _n = (1-sin ² θ _n ) ^1/2 (23)
tan θ _n = sin θ _n / cos θ _n (24)
However, μ and m are step parameters, usually μ is about ¼ to 1/512, and m is an integer of 1 or more.

Next, a specific configuration example of the control unit 52 will be described with reference to FIG.
In this case, the affine converter 51 controlled by the control unit 52 configures a distortion correction unit 62 by connecting a DPD (Digital PreDistortion) unit 61 in series. The DPD unit 61 calculates the instantaneous power of the input IF signal, reads the distortion corresponding to the power from the distortion compensation table, and multiplies the input IF signal. The distortion compensation table stores reverse characteristics of nonlinear distortion generated by the power amplifier 25 and the like. The distortion compensation table of the DPD unit 61 and the four affine transformation coefficients a, b, tan θ, 1 / (α cos θ) of the affine transformer 51 are updated by the control unit 52 so that the distortion is reduced. Input / output of the DPD unit 61 and the affine converter 51 is performed in real time, but the distortion compensation table and the coefficient may be updated by batch processing.

  Buffers 71 and 72 provided in the control unit 52 are input from the digital modulation unit 21 (IF signals I (t) and Q (t)) and input from the digital quadrature detection unit 45 (digital quadrature detection signal I). '(t), Q' (t)) are temporarily stored. The buffer 72 functions as variable delay means because the read timing is controlled.

  A DLL (Delay Locked Loop) 73 reads signals temporarily stored from the buffers 71 and 72, and controls the read (or write) timing so that the correlation between the signals is maximized. The sliding correlator (SC) in the DLL 73 performs complex conjugate multiplication as expressed by the equation (12) and a weighted average of the multiplication result, and converts the real part and the imaginary part of the SC output to the SC output. Dividing by the size corresponds to cos φ and sin φ in the equations (13) and (14), respectively. When the local oscillation signal based on the common source oscillation is used in the transmission system and the return system, there is almost no fluctuation of φ, so it is not always necessary to update and output cos φ and sin φ for each sample.

  The decimator 74 reduces the sample rate to about 2 to 4 times the chip rate (that is, the sample rate of the modulation signal) by thinning out the digital quadrature detection signal read out by the DLL 73. This is because even if there are more sample rates, only the same modulation signal is calculated redundantly, which is statistically meaningless and accuracy is not improved much.

  Multiplier 75 performs operations of equations (13) and (14) on the digital quadrature detection signal output from decimator 74 to compensate for phase rotation.

  The linear distortion detection unit 76 performs calculations of Expressions (15) to (18) using the output of the multiplier 75, and outputs a ′, b ′, α ′, and sin θ ′ for each time averaged over a long period of time. .

  Expression (18) corresponds to the case where τ = 0 and φ = 0 in Expressions (4) and (10), and the sign for updating the Affine transform coefficient is inverted. Note that also in Equation (4), it is necessary to use feedback signals Ir (t) and Qr (t) after phase rotation compensation. Further, φ in equation (11) may be used instead of sin θ ′ in equation (18).

  According to the simulation, in order to suppress the linear distortion by 60 dB or more, it is necessary to perform an average for a long period of about 5000 chips (about 2 to 4 times as many samples). Compared with the weighted average for the long-term average, it is better in terms of convergence to add all the samples after the last update of the affine transformation coefficient and divide by the number of samples at the end.

  The coefficient updating unit 77 performs calculations of Expressions (19) to (24), updates the four affine transformation coefficients, and outputs them.

In addition, approximation can be appropriately used as long as an appropriate approximation is given in θ → 0 and α → 1. In the present embodiment, the four affine transformation coefficients a, b, tan θ, 1 / (α cos θ) are distortion coefficients a ′, b ′, α ′, sin θ ′ representing residual distortion that cannot be compensated by the affine transformer 51. The parameters a _n , b _n , α _n , sin θ _n indicating the inverse characteristics of the distortion of the analog quadrature modulator 24 (or the distortion itself) are first updated to be close to the true values. The affine transformation coefficient is uniquely determined from the measured parameters. That is, the affine transformation coefficient is updated via the parameter.

The test signal generator 78 generates various test signals used for distortion detection during non-operation. For example, tone signals corresponding to ω ₁ and ω ₂ in Expression (11) are generated. The test signal may be given as a baseband signal to the digital modulation unit 21 or may be given as an IF signal to the distortion correction unit 62.

  As described above, in the fourth embodiment, the signal output from the digital modulation unit 21 is input to the affine converter 51 and distortion compensation is performed under the control of the control unit 52. The affine transformer 51 and the control unit 52 collectively correct the orthogonality deviation of the IQ signal and the deviation of the IQ timing, that is, detect and correct the combined distortion value. In this case, there is a difference in properties between the orthogonality deviation and the IQ timing deviation, that is, the IQ timing has a distortion value that varies depending on the frequency, but the orthogonality deviation is invariant regardless of the frequency, Only affine transformation processing leaves a slight IQ timing shift. For this reason, in the fourth embodiment, the signal compensated for distortion by the affine converter 51 is input to the IQ timing adjustment unit 23B and controlled by the detection signal of the IQ timing shift detection unit 46 to match the timing between IQs. In the quadrature modulator 24 and the like, distortion caused by timing shift between IQs is eliminated. As a result, it is possible to reliably remove the deviation of the orthogonality of the IQ signal and the deviation of the IQ timing.

  FIG. 12 shows the frequency spectrum waveform of the output signal of the analog quadrature modulator 24 when there is a timing shift between IQs, and FIG. 13 shows the frequency spectrum waveform of the output signal of the analog quadrature modulator 24 after adjusting the timing shift between IQs. Show. In FIG. 12 and FIG. 13, the horizontal axis represents frequency [MHz] and the vertical axis represents level [dB]. When there is a timing shift between IQs, distortion occurs due to a timing shift between IQs as shown in FIG. After adjusting the timing deviation between IQs, the distortion is eliminated as shown in FIG. As a result, it is possible to transmit a high-quality signal without distortion.

  According to the fourth embodiment, after the distortion compensation is performed on the output signal of the digital modulation unit 21 by the affine converter 51, the IQ timing adjustment unit 23B further adjusts the timing shift during IQ. A deviation in orthogonality and a deviation in IQ timing signal generated in an analog unit such as the analog quadrature modulator 24 can be reliably removed, and a high-quality signal can be obtained.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying constituent elements without departing from the scope of the invention in the implementation stage. For example, the IQ timing deviation detection unit 46 and the control unit 52 can partially share the calculations, and may be configured integrally.

It is a block diagram which shows the structure of the wireless transmitter which concerns on 1st Embodiment of this invention. It is a figure which shows the structural example of the timing adjustment part (analog system) between IQ in the embodiment. It is a block diagram which shows the structure of the wireless transmitter which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the structure of the wireless transmitter which concerns on 3rd Embodiment of this invention. It is a figure which shows the structural example of the timing adjustment part (digital system) between IQ in the same embodiment. It is a figure which shows the example of a transfer function of the FIR filter for timing fluctuations in the same embodiment. It is a figure which shows the impulse response curve of the FIR filter for timing fluctuations in the same embodiment. It is a figure which shows the time waveform of the input-output signal of the FIR filter in the same embodiment. It is a block diagram which shows the structure of the wireless transmitter which concerns on 4th Embodiment of this invention. It is a figure which shows the structural example of the affine converter in the same embodiment. It is a figure which shows the structural example of the control part in the embodiment. It is a figure which shows the frequency spectrum waveform of the output signal of an analog quadrature modulator when the timing shift between IQ exists. It is a figure which shows the frequency spectrum waveform of the output signal of an analog quadrature modulator after the timing shift adjustment between IQ. It is a block diagram which shows the structure of the conventional radio transmitter. It is a block diagram which shows the structural example of the digital modulation part in the conventional radio transmitter.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 21 ... Digital modulation part, 22 ... D / A converter, 23, 23A, 23B ... Timing adjustment part between IQ, 24 ... Analog quadrature modulator, 25 ... Power amplifier, 31a, 31b ... Input terminal, 32a, 32b ... Cable, 33, 34 ... wiring, 35a-35d, 36a-36d ... connector, 41 ... coupler, 42 ... mixer, 43 ... band limiting filter, 44 ... A / D converter, 45 ... digital quadrature detector, 46 ... IQ timing shift Detecting unit 51 ... Affine converter 52 ... Control unit 61 ... DPD unit 62 ... Distortion correcting unit 71, 72 ... Buffer, 73 ... DLL (Delay Locked Loop), 74 ... Decimator, 75 ... Multiplier, 76 ... Linear distortion detector, 77 ... Coefficient updater, 78 ... Test signal generator, 231 ... FIR filter for delay generation, 232 ... Delay generator, 233 ... Tap coefficient Formed part.

Claims (1)

An affine transformation unit that affine-transforms the digitally modulated complex IF signals I (t) and Q (t) based on affine transformation coefficients and outputs compensated signals a (t) and b (t);
An IQ timing adjustment unit for adjusting the timing between IQs by giving a delay to the compensated signals a (t) and b (t) output from the affine transformation unit using an FIR filter in the I phase or the Q phase; ,
A D / A converter for converting a signal output from the IQ timing adjustment function unit from digital to analog and outputting the analog signal;
An analog quadrature modulator that quadrature modulates a carrier wave signal based on an output signal of the D / A converter and outputs an RF signal;
A power amplifier that amplifies and outputs an RF signal output from the analog quadrature modulator;
A frequency conversion unit for converting an output signal of the power amplifier to an IF frequency band,
A band limiting filter that performs band limiting on the IF signal frequency-converted by the frequency converter;
An A / D converter for converting the IF signal output from the band limiting filter from analog to digital and outputting the analog signal;
A digital quadrature detection unit for performing digital quadrature detection on the output signal of the A / D converter and outputting complex feedback signals I ′ (t) and Q ′ (t) having an IF frequency substantially equal to the digital modulation unit;
Linear distortion remaining in the complex feedback signals I ′ (t) and Q ′ (t) is extracted as a distortion coefficient, and the current affine transformation coefficient is updated to a new affine transformation coefficient according to an update formula including the distortion coefficient. A control unit resetting the affine transformation unit,
IQ that detects a timing shift between IQs separately from a shift in IQ orthogonality by an output signal of the digital quadrature detection unit, and outputs a control signal to the IQ timing adjustment unit to adjust a timing shift between IQs A timing shift detection unit;
A wireless transmitter characterized by comprising:

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