JP4647202B2 - diode - Google Patents

Description

  The present invention particularly relates to high speed diodes.

A fast recovery diode (abbreviated as “FRD”, including Free Wheel Diode (abbreviated as “FWD”)) is a switching element such as a MOSFET or IGBT in a power control device such as an inverter device for motor control. It has a wide range of uses, such as being connected in reverse parallel to.
As expressed by Equation 2 described in paragraph 0028 of Patent Document 1, there is a view that the switching energy J at the time of ON (and therefore at the time of FRD turn-off) is proportional to the square of the reverse recovery time (trr), The FRD reverse recovery time (trr) greatly affects not only high response but also switching loss. In addition, current / voltage oscillation during reverse recovery of FRD causes element destruction and noise, which affects the low noise property of the power control apparatus.
As a power control device, a device having high response, low loss, and low noise switching characteristics is desired. However, in power control devices that have become increasingly forced to control large voltages and large currents with the development of the electronic and electrical industry in recent years, it has become difficult to maintain and improve their switching characteristics. Market demands for cheap and compact products in addition to the demands for characteristics have spurred this situation.
Under such circumstances, in FRD, shortening the reverse recovery time (trr) and improving the soft recovery characteristics are becoming increasingly important. As is well known, an FRD having a high breakdown voltage and a low forward voltage drop (VF) is desired.

Conventionally, various structures have been proposed as FRDs.
Non-Patent Document 1 discloses SPEED ( Self Adapting P-Emittor Efficiency Diode) shown in FIG.

Patent Documents 2 to 4 disclose a semiconductor device in which a layer having a high impurity concentration (N ₁ layer in Patent Document 4) is provided on the N ⁺ substrate side of an N ⁻ epitaxial semiconductor layer formed on an N ⁺ semiconductor substrate. Is disclosed. According to Patent Document 4, the maximum amplitude I _RM of reverse current, reverse voltage surge V _RM, and transient vibration during reverse recovery are reduced by using a diode including an N ₁ layer. I can hope.
JP-A-6-253529 Japanese Patent Laid-Open No. 57-37886 JP 58-39070 A JP 58-182277 A [ISPSD'93, pp.199-204, Comparison of High Voltage Power Rectifier Structures, by M. Mehretra & BJBaliga]

  However, in the above prior art, in order to provide a product that meets strict market needs, there are many points to be overcome with respect to the pressure withstand structure, reverse recovery characteristics, and applicability to a simple manufacturing process.

  The present invention has been made in view of the above problems in the prior art, and has a high-speed and soft reverse recovery characteristic, a high breakdown voltage, a reverse blocking characteristic with little reverse leakage current, and a low VF characteristic, and a simple planer. It is an object to provide a high-speed diode that can be manufactured at a low cost by a manufacturing process of technology.

The invention according to claim 1 for solving the above problem is (1) a diode in which a semiconductor film is formed by epitaxial growth on the surface of an N-type semiconductor substrate,
(2) The semiconductor film is
An N-type semiconductor layer (hereinafter referred to as “N-type intermediate concentration layer”) having an impurity concentration lower than that of the semiconductor substrate;
An N-type semiconductor layer (hereinafter referred to as “N-type low-concentration layer”) formed on the opposite side of the semiconductor substrate to the surface of the semiconductor film continuously to the N-type intermediate concentration layer and having a lower impurity concentration than the N-type intermediate concentration layer. And)
(3) By selectively introducing P-type impurities into the surface of the N-type low concentration layer using an oxide film mask having one pattern, a P-type region and a P-type guard ring surrounding the P-type region are formed. And
(4) A plurality of P-type high-concentration regions that are higher in concentration and shallower than the P-type region by selectively introducing P-type impurities into the surface of the P-type region using another oxide mask of another pattern Formed,
(5) an anode electrode metal film connected to the P-type region and the P-type high concentration region;
A cathode electrode metal film deposited on the back surface of the semiconductor substrate;
(6) Lifetime killer is introduced by electron beam irradiation,
(7) The number of the guard rings is m, the guard ring that hits the i-th outward from the innermost guard ring is GRi (where i = 1 to m), and the P-type region and the innermost guard when the distance between the distance between the ring GR1 d1, GRi and GR (i + 1) was d (i + 1), a di <d (i + 1) ( where, i = 1~ (m-1 )),
(8) When the line width of GRi is gi, gi = g (i + 1) <gm (where i = 1 to (m−2)),
(9) The guard ring excluding the outermost guard ring is covered with an insulating film, and the ring-shaped electrode metal film and the anode electrode metal film connected to the outermost guard ring through the opening of the insulating film are A field plate is formed on the insulating film,
(10) The field plates are isolated from each other in a region on the insulating film and above the guard ring excluding the outermost guard ring,
(11) The insulating film of (9) is an oxide film formed by oxidizing the oxide film mask of (3) and the surface of the semiconductor film exposed in the opening of the oxide film mask of (3). It is a diode containing.

  According to the second aspect of the present invention, there are a total of six other P-type high concentration regions closest to one P-type high concentration region (excluding those arranged on the outermost periphery), and the other P-type high concentration regions An arrangement rule in which the center of the region is distributed to each vertex of a regular hexagon centering on the center of the one P-type high concentration region is applied to all or part of the plurality of P-type high concentration regions. The diode according to claim 1, wherein

According to the third aspect of the present invention, the impurity concentration distribution of the N-type intermediate concentration layer is continuous on the one hand with the impurity concentration distribution of the N-type low concentration layer and on the other hand with the impurity concentration distribution of the N-type high concentration layer on the semiconductor substrate side. but as a whole, a diode according to claim 1 or claim 2, characterized in that it forms a gradually increasing the distributed sloped with respect to the impurity concentration of the N-type low concentration layer.

  According to the present invention, an excellent ON / OFF characteristic can be obtained by introducing an N-type intermediate concentration layer, a SPEED structure, and a lifetime killer by electron beam irradiation, and an excellent breakdown voltage maintaining structure by a multiple guard ring can be obtained in the P-type region. Since it is formed together with the forming process, it has high-speed, soft reverse recovery characteristics, high withstand voltage, reverse blocking characteristics with little reverse leakage current, and low VF characteristics, and can be manufactured at low cost with a simple planar technology manufacturing process There is an effect that a high-speed diode can be realized.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following is one embodiment of the present invention and does not limit the present invention. FIG. 1 is a half-body sectional view (lower part of the drawing) and a half-body plan view (upper part of the drawing) showing the FRD of one embodiment of the present invention.

(1) Basic Configuration As shown in FIG. 1, this FRD is a wafer in which a semiconductor film 2 made of silicon containing phosphorus as an N-type impurity is epitaxially grown on a semiconductor substrate 1 made of silicon containing phosphorus as an N-type impurity. It is configured using.
An n-type intermediate concentration layer (hereinafter referred to as “N ₁ layer”) 3, an N-type low concentration layer (hereinafter referred to as “N ⁻ layer”) 4, and a P ⁻ -type active region 5 are formed on the semiconductor film 2 in m layers. Further, guard rings GR1 to GRm, a P ⁺ type active region 6 and an N ⁺ channel stop region 7 are formed.

The N ₁ layer 3 has a lower impurity concentration than the semiconductor substrate 1. The N ₁ layer 3 can be formed at a higher concentration than the N ⁻ layer 4 by the process of forming the semiconductor film 2 and subsequent impurity redistribution several times. The N ₁ layer 3 is formed at a high concentration so that the impurity concentration distribution of the N ₁ layer 3 is higher than the impurity concentration distribution of the N ⁻ layer 4 in a stepped or sloped manner.
The N ⁻ layer 4 is formed to the surface of the semiconductor film 2 continuously from the N ₁ layer 3 on the opposite side of the semiconductor substrate 1. N ⁻ layer 4 has a lower impurity concentration than the N-type intermediate concentration layer.

The P ⁻ -type active region 5 and the guard rings GR1 to GRm are formed by introducing P-type impurities using an oxide film mask having the same pattern, and can be formed by the same process.
The P ⁻ -type active region 5 is formed at the center of the element. The periphery of the P ⁻ -type active region 5 is surrounded m times by m guard rings GR1 to GRm.
The i-th guard ring that hits the outer side from the innermost guard ring GR1 is GRi (where i = 1 to m), and the distance between the P ⁻ -type active region 5 and the innermost guard ring GR1 is d1, GRi And GR (i + 1) and d (i + 1), where di <d (i + 1) (where i = 1 to (m−1)). That is, the distance di (i = 1 to m) gradually increases toward the outside.
Further, when the line width of GRi is gi, gi = g (i + 1) <gm (where i = 1 to (m−2)). That is, the line width gm of the outermost guard ring GRm is the largest, and the line widths g1 to g (m−1) of the other guard rings GR1 to GR (m−1) are equal.

The P ⁺ -type active region 6 is formed by introducing P-type impurities into the surface of the P ⁻ -type active region 5 using an oxide film mask of another pattern, and has a higher concentration than the P ⁻ -type active region 5. Shallowly formed.
The plurality of P ⁺ -type active regions 6 are distributed at regular intervals within the formation range of the P ⁻ -type active regions 5 according to a predetermined arrangement rule.
The N ⁺ type channel stop region 7 is formed by introducing impurities at the outermost peripheral portion of the surface layer of the semiconductor layer 2 with a gap d (m + 1) from the guard ring GRm. d (m + 1)> dm.

The FRD further includes a silicon oxide film 8, an anode electrode 9, a field plate electrode 10, a channel stopper side equipotential ring electrode 11, and a cathode electrode 12.
Silicon oxide film 8 has an opening at the center and periphery. The central opening is opened inside the outer peripheral edge of the P ⁻ -type active region 5 and exposes a plurality of P ⁺ -type active regions 6. The outer peripheral opening is opened in a ring shape with a line width narrower than that of the guard ring GRm so as to expose the center of the outermost guard ring GRm. Further, since the outer peripheral edge of the silicon oxide film 8 is formed inside the outer periphery of the element, the N ⁺ type channel stop region 7 is exposed. A PSG (phosphorus / silicate / glass) protective film (not shown) is laid on the silicon oxide film 8 in the same range.
The anode electrode 9 is connected to the P ⁺ type active region 6 and the P ⁻ type active region 5 (excluding the outer peripheral edge) through the central opening of the silicon oxide film 8. The outer peripheral edge of the anode electrode 9 is formed on an insulating film made of a silicon oxide film 8 and a PSG film.

The field plate electrode 10 is an equipotential ring electrode on the anode side connected to the guard ring GRm through the outer peripheral opening of the silicon oxide film 8. The inner and outer peripheral edges of the field plate electrode 10 are formed on an insulating film made of the silicon oxide film 8 and the PSG film.
The channel stopper side equipotential ring electrode 11 is connected to the N ⁺ type channel stop region 7 exposed outside the outer peripheral edge of the silicon oxide film 8, and is held at substantially the same potential as the cathode. It is formed on the insulating film made of the film 8 and the PSG film.
The field plate electrode 10 and the channel stopper side equipotential ring electrode 11 are formed at equal intervals over the entire circumference. As a result, local breakdown due to local discharge is less likely to occur. The cathode electrode 11 is attached to the back surface of the semiconductor substrate 1. Aluminum is used as the main material as the material of the above electrodes. For example, a composite film such as Al / Ti / Ni / Au and Al / Ti / Ni / Ag is applied.

  A final insulating protective film (not shown) is laid from the edge of the anode electrode 9 to the outer periphery of the element, covers the field plate electrode 10 and the channel stopper side equipotential ring electrode 11, and is electrically and mechanically loaded. The surface of the element is protected from. A silicon nitride or PSG film can be used as the final insulating protective film.

As shown in FIG. 1, this FRD is manufactured by planar technology. The lower edge of the P ⁻ -type active region 5, the guard rings GR1 to GRm and the P ⁺ -type active region 6 is rounded and has a curved surface. Constitute.

(2) Manufacturing Method Next, main manufacturing steps of the FRD will be described with reference to FIGS. 2 and 3 are cross-sectional views in the main process for manufacturing the FRD of one embodiment of the present invention.

First, as shown in FIG. 2A, a wafer having an N ⁻ type semiconductor layer 2 epitaxially grown on an N ⁺ type semiconductor substrate 1 is oxidized, and silicon oxide films 21a and 22 are formed on both sides thereof. .

Next, as shown in FIG. 2B, the silicon oxide film 21a on the surface of the semiconductor layer 2 is opened using a known lithography / etching technique to form an oxide film mask pattern 21b. Further, boron is ion-implanted into the semiconductor layer 2 using the oxide film mask pattern 21b as a mask. After the boron implantation, the silicon oxide film 21c is formed by thermally diffusing and activating boron and reoxidizing the wafer surface. Thus, the P ⁻ type active region 5 and the guard rings GR1 to GRm are formed.

Next, as shown in FIG. 2 (3), the silicon oxide film 21c is opened with a predetermined dot pattern using a well-known lithography etching technique, and boron is ion-implanted into the P ⁻ -type active region 5 using this as a mask. . After boron implantation, thermal diffusion is performed to activate boron and the wafer surface is re-oxidized to form a silicon oxide film 21d. Thereby, a plurality of P ⁺ -type active regions 6 are formed.

Next, the periphery of the semiconductor oxide film 21d is etched and opened using a well-known photolithography technique. Thus, phosphorus is ion-implanted through the opening, thereby forming the N ⁺ type channel stop layer 7. After phosphorus ion implantation, thermal diffusion is performed to activate phosphorus, and the wafer surface is re-oxidized to form a silicon oxide film 21e.

  Next, as shown in FIG. 3D, a PSG film 23a is formed.

Next, as shown in FIG. 3 (5), the PSG film 23a and the silicon oxide film 21e are opened to form the PSG film 23b and the silicon oxide film 8 by using a known lithography / etching / metal film forming technique. The electrode metal films 9, 10 and 11 described above are formed through the openings of the PSG film 23b and the silicon oxide film 8 so that the P ⁻ type active region 5, the P ⁺ type active region 6, the guard ring GRm, and the N ⁺ type channel stop region, respectively. 7 to be connected.

  Next, the back surface of the wafer is ground. Thereby, the silicon oxide film 22 on the back surface is removed.

  Thereafter, the cathode electrode 12 described above is formed on the back surface of the wafer as shown in FIG. Further, a final insulating protective film 24 is formed as shown in FIG. The central anode electrode 9 is exposed. As the final insulating protective film 24, silicon nitride or a PSG film can be used.

  Electron beam irradiation for introducing a lifetime killer is performed on the element formed as described above. In addition, although it is sufficient to irradiate the electron beam from the front surface side, the inventors of the present application have confirmed by experiments that there is no great difference in the result even when the electron beam is irradiated from the back surface side.

(3) Planar structure of P-type active region Next, the arrangement of the P ⁺ -type active region 6 in plan view will be described. FIG. 4 is a partially enlarged view of the surface of the semiconductor layer 2 in the region where the P ⁻ -type active region 5 and the P ⁺ -type active region 6 are formed in FIG.
As shown in FIG. 4A, dot-like P ⁺ -type active regions 6 are arranged in an evenly distributed manner. The arrangement rule applied to this embodiment is a total of six other P ⁺ type active regions 6b closest to one P ⁺ type active region 6a (excluding those arranged on the outermost periphery). The arrangement rule is such that the center of each P ⁺ -type active region 6b is distributed to each vertex of a regular hexagon centering on the center of the one P ⁺ -type active region 6a. As a result, the P-type active region can be formed uniformly, and local concentration of electric field and current is prevented, which is particularly effective for improving the breakdown voltage.

Here, as shown in FIG. 4A, the pattern pitch is a, and the pattern interval is b. In addition, c shows the diameter of the opening of an oxide film mask. Since the impurity introduced from the opening diffuses in the lateral direction, c <a.
Since a regular hexagon can be divided into six congruent regular triangles, one regular triangle is taken out from the regular hexagon shown in FIG. 4A as shown in FIG. 4B. When the area of the equilateral triangle is S, and the area of the P ⁺ -type active region 6 is Sp ⁺ and the area of the P ⁻ -type active region 5 is Sp ^{− in the} equilateral triangle, the following expressions 1 to 6 are established.
<Formula 1>: S = (√3) a 2/4
<Expression ^{2>: Sp + = π (} a-b) 2/8
<Expression 3>: Sp ⁻ = S−Sp ⁺ = (√3) a ² / 4−π {(ab) ² } / 8
<Formula 4>: Sp ⁺ / S = π {(ab) ² } / {2 (√3) a ² }
<Formula 5>: Sp ⁻ / S = 1−Sp ⁺ / S
<Formula 6>: Sp ⁺ / Sp ⁻ = π {(ab) ² } / [2 (√3) a ² −π {(ab) ² }]

P ⁺ -type active whole distribution area of the region 6, because can be approximated as being formed in a repeating pattern in units of equilateral triangle shown in FIG. 4 (b), the ratio of the above formula 4-6 P ⁺ -type active The entire distribution region of the region 6 can also be treated as being approximately established.

(4) Simulation (4-1) Conditions and Results Next, a simulation performed on the breakdown voltage structure of the device according to the above embodiment will be disclosed. FIG. 5 shows a cross-sectional structure of the calculation target region of this simulation. The calculation target area is an area of 0 to 450 μm in the X direction and −2.5 to 130 μm in the Y direction. A two-dimensional impurity concentration distribution line is shown in the same region. The guard ring number m = 8.
FIG. 6 shows a vertical impurity concentration curve. As shown in FIG. 6, the impurity concentration curve changes in a step shape in which flat portions and inclined portions are alternately continued. The inclined portion between the flat portion of the N ₁ layer 3 and the flat portion of the N ⁻ layer 4 is evaluated as the N ⁻ layer 4 side, and the steep portion between the flat portion of the N ⁻ layer 4 and the flat portion of the N ⁺ layer is evaluated. The slanted part is evaluated as the N ⁺ layer side. Therefore, the boundary line between the N ₁ layer 3 and the N ⁻ layer 4 can be evaluated as 65 μm, and the boundary line between the N ⁻ layer 4 and the N + layer can be evaluated as 115 μm. The depth of the P ⁻ layer, that is, the P ⁻ type active region 5 and the guard rings GR1 to GR8 is 5 μm in common. Note that the impurity concentration distribution of the N ⁻ layer 4 can be obtained by adopting a step shape composed of an inclined portion and a flat portion, or a slope shape having only an inclined portion as indicated by a broken line in FIG.

  Reverse voltage application simulation (withstand voltage calculation simulation) was performed. The potential distribution and electric field distribution when applying a reverse voltage of 1200 V were calculated. A two-dimensional potential distribution diagram (FIG. 7), a lateral potential distribution diagram (FIG. 8) and an electric field distribution diagram (FIG. 9) having a depth of 0.1 μm, and a vertical electric field distribution diagram (FIG. 10) are shown. A reverse voltage-current curve (withstand voltage calculation result) is shown in FIG.

(4-2) Evaluation The FRD of the present invention is di <d (i + 1) (where i = 1 to (m−1)). Since m = 8 in the present simulation, d1 <d2 <d3... D6 <d7 <d8. As can be seen from FIGS. 7 and 8, the nonuniformity of the potential line spacing can be eliminated and the locality of the potential line can be increased as compared with the case of di ≧ d (i + 1). Therefore, concentration of potential lines, that is, local concentration of electric field can be prevented, and a high breakdown voltage structure can be obtained.

As shown in FIG. 9, the maximum point of the electric field intensity was 10 points. The first point from the inside was about 1.7E + 05 (V / cm) at the side end of the main junction (that is, the PN junction comprising the P ⁻ -type active region 5 and the N ⁻ layer 4). The second and third points showed a maximum electric field strength of about 2.24E + 05 (V / cm) at the outer end of GR1 and the outer end of GR2. The 4th to 9th points gradually decreased at the outer ends of GR3 to GR8, and were about 6E + 05 (V / cm) at the outer end of GR8, which was the minimum value. The tenth point slightly increased at the outer end of the field plate electrode 10 to about 8E + 05 (V / cm), but the maximum value was the second lowest value. As a whole, the distribution of the local maximum points from the first point to the ninth point was close to an upwardly convex arc shape.

During the device operation, the outermost guard ring GR8 becomes one weak part (a place where breakage is likely to occur) that is exposed to severe conditions such as the generation point of the maximum charge or the concentration of residual carriers. The end of the field plate electrode is susceptible to the electric field on the surface and becomes another weak part. The main junction end portion tends to concentrate current when the main current is recovered, and becomes another weak portion. On the other hand, GR1 to GR7 are protected by the silicon oxide film 8 and are easily electrically stable.
The device's breakdown voltage maintaining structure suppresses the electric field strength at the three weak points described above, and places a relatively large burden on the stable midboard GR1 to GR7, so that a higher and more stable breakdown voltage characteristic can be obtained.
Further, as shown in FIG. 11, according to this device, the breakdown voltage is sufficiently high as 1400 V, and a reverse voltage-current curve with a small reverse leakage current at the time of reverse blocking is obtained. Less excellent reverse blocking properties can be obtained.
The above effects were obtained in accordance with the present invention, where di <d (i + 1) (where i = 1 to (m−1)) and gi = g (i + 1) <gm (where i = 1). To (m-2)), by utilizing the electric field relaxation effect by the field plate (the portion of the field plate electrode 10 on the oxide film 8 and the portion of the anode electrode 9 on the oxide film 8).

(5) Experiment (5-1) Conditions and Results Next, experiments conducted on the pressure-resistant structures of Examples and Comparative Examples according to the above embodiment will be disclosed. In this experiment, we fabricated a device and measured various characteristics. FIG. 12A shows a table summarizing the specifications of the wafer used, FIG. 12B shows a table summarizing the conditions of each sample, and FIG. 13 shows sample dimensions. The P ⁺ -type active region 6 was formed in a dot pattern having a diameter of 6 μm with the diameter c = 4 of the oxide film mask opening, and the pattern pitch a = 20 μm and the pattern interval b = 14 μm.
In the ion implantation for forming the P ⁻ -type active region 5, the implantation amount is set to 1 × 10 ¹³ (1 / cm ² ) or 5 × 10 ¹³ (1 / cm ² ), and in either case, 200 (KeV) 1
Annealing was performed at 150 ° C. for 300 minutes. The P ⁺ type active region 6 was subjected to 150 (KeV) with an implantation amount of 5 × 10 ¹⁴ (1 / cm ² ) and annealed at 1050 ° C. for 60 minutes. FIG. 14 shows the impurity concentration distribution of each P-type layer.

FIG. 15 shows a table summarizing the results of measuring the main characteristics. The measurement items are voltage VR (V) when energizing reverse IR = 10 (μA), voltage VF (V) when energizing forward IF = 400 (A), reverse recovery time trr (ns), and the following: These are ta, tb, Irrm, Qrr, dIr / dt, and Err.
FIG. 16 shows a waveform diagram supplementing the explanation of each characteristic parameter. The maximum value of the reverse recovery current is Irrm. T0 to t1 is ta (ns), where t1 is the point of intersection of current waveform and t-axis, t1 is the point when Irrm is reached, t2 is the point of intersection of the t-axis with the straight line passing the 0.5 Irrm and 0.9 Irrm points on the current waveform. ), T1 to t2 are tb (ns). It is assumed that trr = ta + tb. Qrr represents the area surrounded by the current waveform during reverse recovery and the t-axis. The slope of the straight line passing through the points at 0.5 Irrm and 0.9 Irrm on the current waveform is dIr / dt. Err is a product of current and voltage at the time of reverse recovery, and corresponds to a loss at turn-off.
The turn-off condition was measured as a condition for switching from IF = 400 (A) to VR = 750 (V) at a speed of −dIF / dt = 1000 (A / ns).
The reverse recovery waveform of sample No. 27 is shown in FIG. 17, and the reverse recovery waveform of sample No. 30 is shown in FIG. In addition, the reverse recovery waveform of sample No. 27 and the reverse recovery waveform of sample No. 30 are displayed superimposed on FIG.

(5-2) Evaluation For all of VR, trr, Irrm, Qrr, dIr / dt, and Err shown in FIG. 15, sample No. 30 is better than sample No. 27, as shown in FIGS. As shown in the results that sample No. 30 has a better reverse recovery waveform than sample No. 27, sample No. 30 has higher reverse withstand voltage, soft recovery and shorter trr and loss. It was confirmed that the reverse recovery characteristic was small.

FIG. 1 is a half-body sectional view (lower part of the drawing) and a half-body plan view (upper part of the drawing) showing the FRD of one embodiment of the present invention. It is sectional drawing in the main process which manufactures FRD of one Embodiment of this invention. It is sectional drawing in the main processes following FIG. 2 which manufactures FRD of one Embodiment of this invention. It is the elements on larger scale of the surface of the semiconductor layer 2 which concerns on one Embodiment of this invention. It is a sectional structure figure of the calculation object field of simulation. It is the impurity concentration curve of the vertical direction of the simulation object device. It is a two-dimensional electric potential distribution figure at the time of reverse voltage 1200V application of the simulation object device. It is a potential distribution diagram in the lateral direction with a depth of 0.1 μm when a reverse voltage of 1200 V is applied to the simulation target device. It is a horizontal electric field distribution map of depth 0.1 micrometer at the time of reverse voltage 1200V application of the simulation object device. It is a vertical direction electric field distribution map at the time of reverse voltage 1200V application of a simulation object device. It is a reverse direction voltage-current curve of the simulation object device. It is the table | surface which described the trial production conditions of the experiment sample. It is the top view which showed the dimension of the experiment sample. It is an impurity concentration distribution map of each P-type layer in an experimental sample. It is the table | surface which put together the result of having measured the main characteristics of the experiment sample. It is a wave form diagram which supplements description of each characteristic parameter employ | adopted in experiment. It is a reverse recovery waveform figure of experiment sample No.27. It is a reverse recovery waveform figure of experiment sample No.30. FIG. 14 is a waveform diagram in which a reverse recovery waveform of experimental sample No. 27 and a reverse recovery waveform of sample No. 30 are displayed in an overlapping manner. It is sectional drawing which shows SPEED of a prior art.

Explanation of symbols

1 ... semiconductor substrate 2 ... semiconductor layer 3 ... N-type intermediate concentration layer (abbreviated "N ₁ layer") 4 ... N-type low concentration layer (abbreviated "N ^- layer") 5 ... P ^- -type active region GR1～GRm ... guard Ring 6 ... P ⁺ type active region 7 ... N ⁺ channel stop region 8 ... silicon oxide film 9 ... anode electrode 10 ... field plate electrode 11 ... channel stopper side equipotential ring electrode 12 ... cathode electrode 23b ... PSG film 24 ... final Insulating protective film

Claims (3)

(1) A diode in which a semiconductor film is formed by epitaxial growth on the surface of an N-type semiconductor substrate,
(2) The semiconductor film is
An N-type semiconductor layer (hereinafter referred to as “N-type intermediate concentration layer”) having an impurity concentration lower than that of the semiconductor substrate;
An N-type semiconductor layer (hereinafter referred to as “N-type low-concentration layer”) formed on the opposite side of the semiconductor substrate to the surface of the semiconductor film continuously to the N-type intermediate concentration layer and having a lower impurity concentration than the N-type intermediate concentration layer. And)
(3) By selectively introducing P-type impurities into the surface of the N-type low concentration layer using an oxide film mask having one pattern, a P-type region and a P-type guard ring surrounding the P-type region are formed. And
(4) A plurality of P-type high-concentration regions that are higher in concentration and shallower than the P-type region by selectively introducing P-type impurities into the surface of the P-type region using another oxide mask of another pattern Formed,
(5) an anode electrode metal film connected to the P-type region and the P-type high concentration region;
A cathode electrode metal film deposited on the back surface of the semiconductor substrate;
(6) Lifetime killer is introduced by electron beam irradiation,
(7) The number of the guard rings is m, the guard ring that hits the i-th outward from the innermost guard ring is GRi (where i = 1 to m), and the P-type region and the innermost guard when the distance between the distance between the ring GR1 d1, GRi and GR (i + 1) was d (i + 1), a di <d (i + 1) ( where, i = 1~ (m-1 )),
(8) When the line width of GRi is gi, gi = g (i + 1) <gm (where i = 1 to (m−2)),
(9) The guard ring excluding the outermost guard ring is covered with an insulating film, and the ring-shaped electrode metal film and the anode electrode metal film connected to the outermost guard ring through the opening of the insulating film are A field plate is formed on the insulating film,
(10) The field plates are isolated from each other in a region on the insulating film and above the guard ring excluding the outermost guard ring,
(11) The insulating film of (9) is an oxide film formed by oxidizing the oxide film mask of (3) and the surface of the semiconductor film exposed in the opening of the oxide film mask of (3). Including diodes. There are a total of six other P-type high-concentration regions closest to one P-type high-concentration region (excluding those arranged on the outermost periphery), and the center of the other P-type high-concentration region is the one P-type high-concentration region. The arrangement rule distributed one by one to each vertex of a regular hexagon centering on the center of the type high concentration region is applied to all or part of the plurality of P type high concentration regions. 1. The diode according to 1. On the other hand, the impurity concentration distribution of the N-type intermediate concentration layer, which is continuous with the impurity concentration distribution of the N-type low concentration layer and on the other hand, is continuous with the impurity concentration distribution of the N-type high concentration layer on the semiconductor substrate side. 3. The diode according to claim 1, wherein the diode has a slope-like distribution with respect to the impurity concentration of the concentration layer.

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