JP4639210B2 - A / D converter - Google Patents

Description

  The present invention relates to a technique for enabling highly accurate signal conversion processing in an interleaved A / D converter.

  As a technique for sampling analog signals at high speed, a plurality of M A / D converters that commonly receive the analog signals are used, and the plurality of M A / D converters sample the analog signals at a predetermined period T. There is known an interleaving method performed at a timing shifted by T / M.

  In this interleaved A / D converter, as shown in FIG. 9, for example, an input analog signal X (t) is branched into a plurality of M (in this example, M = 4) by a signal distributor 11 and each A / D is converted. It inputs into converter 12 (1)-12 (4).

  Since each of the A / D converters 12 (1) to 12 (4) is provided with clock signals C1 to C4 whose phases are shifted by T / 4 at a period T from the clock generator 13, the analog signal X (T) is sampled substantially at a quarter of the clock period T and converted into digital values D1 to D4, and high-speed analog signal sampling is possible.

  Such an interleaved A / D converter is disclosed in, for example, the following Patent Document 1.

Japanese Patent No. 3756237

  However, as the frequency of the analog signal increases, the sampling timing error due to variations in the signal path, operation delay of each A / D converter, etc. cannot be ignored, and the digital signal obtained by the A / D conversion process There was a problem that spurious was generated in the column and high-precision signal conversion processing could not be performed.

  FIG. 10 shows the result of obtaining the spurious component by performing FFT processing on the output value obtained by sampling with an interleaved A / D converter using two A / D converters. Yes, the spurious level of the signal increases according to the phase error, and in order to reduce the spurious level to 60 dB or less, for example, the phase error needs to be 1/1000 or less. It was difficult to obtain the phase error constantly.

  The present invention solves this problem and enables A / D to perform highly accurate signal conversion processing even when there are variations in the signal path, the signal path of the sampling clock signal, the operation delay of each A / D converter, and the like. The object is to provide a conversion device.

In order to achieve the above object, an A / D conversion device according to claim 1 of the present invention comprises:
Signal branching means (23) for branching an analog input signal into a plurality of M;
A plurality of M A / D converters (25 (1) to 25 (4)) that respectively receive the branched signals, sample the clock signals at the input timing, and convert them into digital values;
In the A / D converter of an interleave type in which the A / D converter performs sampling of a predetermined period T with respect to the branched input signal by relatively shifting by T / M,
A reference signal generating means (21) for outputting a reference signal of a known frequency;
When the reference signal is input to the signal branching means, the output value of the plurality of M A / D converters is acquired, and the phase difference of the signal having the output value for each A / D converter as the instantaneous amplitude is calculated. Phase difference calculating means (31) for performing,
An error calculating means (32) for obtaining an error of the phase difference calculated by the phase difference calculating means;
A variable delay device (34 (1) to 34 (4)) for relatively varying each sampling timing with respect to an input signal of each A / D converter;
Control means (35) for controlling the delay amount of the variable delay device so that the error of the phase difference obtained by the error calculation means is reduced ,
The reference signal generating means is configured to be able to selectively output a first reference signal and a second reference signal having different arbitrarily designated frequencies,
In the control means, the absolute value of the phase difference error calculated when the first reference signal is input is substantially equal to the absolute value of the phase difference error calculated when the second reference signal is input. As described above, the delay amount of the variable delay device is controlled .

Further, A / D converter according to claim 2 of the present invention,
Signal branching means (23) for branching an analog input signal into a plurality of M;
A plurality of M A / D converters (25 (1) to 25 (4)) that respectively receive the branched signals, sample the clock signals at the input timing, and convert them into digital values;
In the A / D converter of an interleave type in which the A / D converter performs sampling of a predetermined period T with respect to the branched input signal by relatively shifting by T / M,
A reference signal generating means (21) for outputting a reference signal of a known frequency;
When the reference signal is input to the signal branching means, the output value of the plurality of M A / D converters is acquired, and the phase difference of the signal having the output value for each A / D converter as the instantaneous amplitude is calculated. Phase difference calculating means (31) for performing,
An error calculating means (32) for obtaining an error of the phase difference calculated by the phase difference calculating means;
A variable delay device (34 (1) to 34 (4)) for relatively varying each sampling timing with respect to an input signal of each A / D converter;
Control means (35) for controlling the delay amount of the variable delay device so that the error of the phase difference obtained by the error calculation means is reduced,
The reference signal generating means is configured to output a reference signal on which a plurality of frequency components are superimposed,
The phase difference calculating means is configured to calculate a phase for each frequency component included in the reference signal and calculate the difference, respectively.
The error calculation means is configured to obtain an error of a phase difference for each frequency component,
The control means controls the delay amount of the variable delay device so that absolute values of phase difference errors for the respective frequency components are substantially equal .

The A / D converter according to claim 3 of the present invention is the A / D converter according to claim 1 or 2 ,
The control means makes the absolute value of the error relative to the reference signal of the frequency equal to or close to the upper limit frequency and the lower limit frequency within the frequency band of the allowable input signal or the frequency component included in the reference signal to be equal and opposite in sign. In addition, the delay amount of the variable delay device is controlled to set a small error region that crosses the error 0 at the center of the frequency band .

As described above, the A / D converter according to the present invention instantaneously outputs the output values of a plurality of M A / D converters when a reference signal having a different frequency or a reference signal including a plurality of frequency components is input to the signal branching means. The phase difference of the amplitude signal is calculated for each frequency component , the calculated phase difference error is obtained, and the delay amount of the variable delay device is controlled so that the phase difference error is small and the frequency characteristics are flat. Therefore, even if there are variations in the analog signal path, the sampling clock signal path, the operation delay of the A / D converter, etc., highly accurate signal conversion processing can be performed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration of an A / D conversion apparatus 20 to which the present invention is applied.

  This A / D conversion device 20 switches one of an analog signal X (t) to be converted and a reference signal R having a predetermined frequency fr and a constant amplitude output from the reference signal generator 21 to a switch 22. The signal is selected and input to the signal branching unit 23.

  The signal branching unit 23 branches the input signal into a plurality of Ms in the same phase (hereinafter described in the case of M = 4), and the branched signals X1 to X4 are respectively A / D converters 25 (1) to 25 (1) to 25. Input in (4).

  On the other hand, the clock generator 26 is used for sampling to provide the A / D converters 25 (1) to 25 (4) with four-phase clock signals C1 to C4 whose phases are shifted by T / 4 at a predetermined period T. Generated as a clock signal.

  The clock signals C1 to C4 are phase-controlled by variable delay devices 34 (1) to 34 (4), which will be described later, and supplied to A / D converters 25 (1) to 25 (4).

  Output values D1 to D4 of the A / D converters 25 (1) to 25 (4) are input to the phase difference calculation means 31.

  The phase difference calculation means 31 acquires the output values D1 to D4 of the A / D converters 25 (1) to 25 (4) in a state where the reference signal R is input instead of the analog signal X (t). Then, the phases of the four-phase signals whose instantaneous values are the output values of the respective A / D converters are obtained, and the difference is calculated.

  The calculation of the phase is, for example, orthogonal transformation processing for the input value, that is, when the frequency of the reference signal R is fr, the following orthogonal transformation operation is performed on the input value Di, and the phase value θi for each A / D converter is calculated. Ask for.

I = Σ [Di · cos (2πfrt)]
Q = Σ [Di · sin (2πfrt)]
θi = tan (Q / I)
Here, the symbol Σ represents the total sum for the number of samples.

  Then, one of the four A / D converters 25 (1) to 25 (4), here, the phase θ1 of the output value D1 of the A / D converter 25 (1) is set as a reference phase, and each of the other A / D converters 25 (1) to 25 (4). The phase differences φ1 to φ3 of the output values D2 to D4 of the D converters 25 (2) to 25 (4) and the phases θ2 to θ4 are calculated by the following calculation.

φ1 = θ2-θ1
φ2 = θ3-θ1
φ3 = θ4-θ1

  Note that the phase difference obtained here is only required to obtain the relative phase difference of the four-phase signals, and only the method of obtaining the relative phase difference of the other signals on the basis of the phase of one signal as described above. Alternatively, a method of obtaining the phase difference of each signal in the order of sampling may be used.

  The error calculation means 32 obtains errors Δφ1 to Δφ3 with respect to the theoretical values of the phase differences φ1 to φ3 calculated by the phase difference calculation means 31.

  Phase difference errors [Delta] [phi] 1 to [Delta] [phi] 3 obtained by the error calculation means 32 are input to the control unit 35 described later, and A / D converters 25 (1) to 25 (1) to 25 (1) to 25 (1) with respect to the reference signal R are reduced. Each sampling timing of 4) is corrected.

  The phase correction is performed by control of variable delay units 34 (1) to 34 (4) that give delays corresponding to the control signals d1 to d4 to the four-phase clock signals C1 to C4 output from the clock generator 26. The delay-controlled clock signals C1 'to C4' are input to the A / D converters 25 (1) to A / D converters 25 (4).

  The control unit 35 connects the switch 22 to the reference signal side at a predetermined timing, for example, a timing at which a phase correction processing instruction is received from an operation unit (not shown) or the power-on timing of the apparatus, and the level calculated at that time. After controlling the delay amount of the variable delay devices 34 (1) to 34 (4) so that the phase difference error is reduced, the switch 22 is switched to perform the A / D conversion process on the unknown analog signal X (t). Make it.

  Here, the reference A / D converter 25 (1) prevents the phase of the clock signals C1 ′ to C4 ′ from relatively changing even if the delay amount of the variable delay device fluctuates due to a temperature change or the like. ) Also through the variable delay device 34 (1), but if the change in the delay amount due to temperature change or the like does not matter, the reference A / D converter 25 (1) Alternatively, a clock signal may be given through a fixed delay device or without delay.

  In the A / D conversion device 20 configured as described above, for example, when a phase correction process is instructed, the control unit 35 sets the delay amounts of the variable delay devices 34 (1) to 34 (4) to a constant value d0. 2 is connected to the reference signal generator 21 side, and the reference signal R shown in FIG.

  In this state, the A / D converters 25 (1) to 25 (4) are supplied with clock signals C1 'to C4' whose phases are shifted by about T / 4 in a cycle T together with the branch output of the reference signal. Then, the reference signal R is sampled in synchronization with the clock signal, and the values Di (0), Di (1),... Shown in (b1) to (b4) of FIG. = 1 to 4).

  The phase difference calculating means 31 acquires a certain number of these output values, and the output values D1 of the A / D converters 25 (1) to 25 (4) as shown in (c1) to (c4) of FIG. The phases θ1 to θ4 of the signals Y1 to Y4 respectively determined by D4 to D4 are obtained as described above, and the phase difference with the phase θ1 as the reference phase is obtained.

  The phase differences φ1 to φ3 obtained by these calculations should be equal if the device is in an ideal state, but actually, from the signal branching unit 23 to each of the A / D converters 25 (1) to 25 (4). An error occurs due to a difference in signal path length, a phase error when generating clock signals C1 to C4, a difference in signal path length, and the like.

The phase differences φ1 to φ3 are the phase angles of the reference signal R. If the period of the reference signal R is Tr, the delay times Td1 to Td3 corresponding to the phase differences φ1 to φ3 are
Td1 = Tr · φ1 / 2π
Td2 = Tr · φ2 / 2π
Td3 = Tr · φ3 / 2π
It can be expressed as.

  In the ideal state, each of the delay times Td1 to Td3 should be equal to ¼ of the cycle T of the sampling clock signals C1 to C4.

When the time T / 4 is converted into the phase angle φr of the reference signal R,
φr = πT / (2Tr) (radian)
It is expressed.

That is, the error calculation means 32 calculates the phase difference error by the following calculation.
Δφ1 = φ1-φr (radians)
Δφ2 = φ2-φr (radians)
Δφ3 = φ3-φr (radians)

Note that the phase difference error may be determined by time instead of the phase angle.
Δφ1 = Td1−T / 4 (seconds)
Δφ2 = Td2−T / 4 (seconds)
Δφ3 = Td3−T / 4 (seconds)
You may obtain | require by calculation of.

  Upon receiving the phase difference error obtained in this way, the control unit 35 controls the delay amounts of the variable delay devices 34 (2) to 34 (4) so that the error is reduced.

  By this control, the relative sampling timing with respect to the input signals of the A / D converters 25 (1) to 25 (M) is accurately shifted by ¼ of the predetermined period T, and accurate data acquisition is possible. It becomes possible.

  Then, at the stage when the phase control operation is finished and the error is minimized, the switch 22 is switched to input the analog signal X (t) to be converted, thereby interleaving the signal X (t). A / D conversion processing can be performed accurately, and spurious can be suppressed.

  In the above description, the frequency fr of the reference signal R is fixed. However, as the frequency fr, the A / D converter 20 as a whole so that a phase error due to variations in line length and the like appears remarkably. The frequency may be equal to (or close to) the upper limit frequency fa of the allowable input signal, and the error may be minimized at this frequency fa as shown in FIG.

  Also, as shown in FIG. 4, two reference signals having arbitrary different frequencies, for example, the upper limit frequency fa and the lower limit frequency fb of the allowable band of the input signal are equal (or close) by the control of the control unit 35 or the like. The first reference signal Ra and the second reference signal Rb having a frequency sine wave are selectively output from the reference signal generator 21, and the first reference signal having the frequency fa is input in the same manner as described above. The phase difference errors Δφ1 (fa) to Δφ3 (fa) are obtained, and the phase difference errors Δφ1 (fb) to Δφ3 (fb) are obtained with the second reference signal having the frequency fb being input.

  Then, the control unit 35 performs control so that the absolute value of each error becomes equal as follows, for example, as shown in FIG. 5, to reduce each error between the A / D converters and flatten the frequency characteristics. Let

| Δφ1 (fa) | = | Δφ1 (fb) |
| Δφ2 (fa) | = | Δφ2 (fb) |
| Δφ3 (fa) | = | Δφ3 (fb) |

  Here, as described below, if the control is performed so that the absolute values of the errors are equal and the signs are opposite, a region with a small error can be set at the center of the band as shown in FIG.

Δφ1 (fa) = − Δφ1 (fb)
Δφ2 (fa) = − Δφ2 (fb)
Δφ3 (fa) = − Δφ3 (fb)

  Further, the reference A / D converter 25 (1) is similarly changed as described above while changing the frequency fr of the reference signal R within the frequency range of the input signal allowed for the A / D converter 20 as a whole, for example, at a predetermined step Δf. The phase difference error of the outputs of the A / D converters 25 (2) to 25 (4) with respect to the output of each of the A / D converters is obtained for each frequency, and the absolute value of the error is small and the frequency characteristics are reduced using a least square method or the like. It is also possible to give a delay amount that is flat.

  Further, a reference signal R generated by the reference signal generator 21 may be a pulse waveform having a plurality of frequency components superimposed thereon.

  In this case, a fundamental wave component and a harmonic component that is an integral multiple of the fundamental wave component are included, but components outside the band of the input signal are folded back into the band by the action of the A / D converter. The frequency of the fundamental wave is set so that the component and its aliasing component do not overlap.

  In this case, the phase of a plurality of frequency components cannot be calculated by the orthogonal transformation operation for a single sinusoidal wave as in the above embodiment. Therefore, in this case, the phase difference calculation means 31 performs FFT (Fast Fourier Transform) processing on the output signals of the A / D converters 25 (1) to 25 (4), respectively, and each frequency component (for example, f1, f2, and f3) phases θ1 (f1) to θ1 (f3), θ2 (f1) to θ2 (f3), θ3 (f1) to θ3 (f3), θ4 (f1) to θ4 (f3) And the phase differences φ1 to φ3 for each frequency are obtained by the following calculation.

φ1 (f1) = θ2 (f1) −θ1 (f1)
φ1 (f2) = θ2 (f2) −θ1 (f2)
φ1 (f3) = θ2 (f3) −θ1 (f3)

φ2 (f1) = θ3 (f1) −θ1 (f1)
φ2 (f2) = θ3 (f2) −θ1 (f2)
φ2 (f3) = θ3 (f3) −θ1 (f3)

φ3 (f1) = θ4 (f1) −θ1 (f1)
φ3 (f2) = θ4 (f2) −θ1 (f2)
φ3 (f3) = θ4 (f3) −θ1 (f3)

  Then, the delay amounts of the variable delay devices 34 (2) to 34 (4) are controlled so that the absolute value of the phase difference error obtained as described above is small and the frequency characteristics are flat.

  Even in this case, as shown in FIG. 6, by setting the delay amount so as to cross the error 0 in the central region of the frequency band, a region having a small error is set in the central portion of the band. Can do.

  In the embodiment, the phases of the four-phase clock signals input to the A / D converters 25 (1) to 25 (4) are finely adjusted using the variable delay units 34 (1) to 34 (4). In this way, the sampling timing for the input signals of the A / D converters 25 (1) to 25 (4) is adjusted. As shown in FIG. The variable delay devices 34 (1) to 34 (4) are supplied to the A / D converters 25 (1) to 25 (4), and the phase difference error is controlled as a delay amount of the input signal. It is also possible to make it smaller.

  Furthermore, as shown in FIG. 8, between the signal branching unit 23 and the A / D converters 25 (1) to 25 (4), a fixed delay device in which the delay time for the input signal is different by ¼ of the period T. 51 (1) to 51 (4) are inserted, the analog signal is phase-shifted by T / 4, and each A / D converter 25 (1) is passed through each variable delay device 34 (1) to 34 (4). ) To 25 (4), and the clock generator 26 'may input the clock signal C having the period T to the A / D converters 25 (1) to 25 (4) in phase.

  Further, the above-described fixed delay devices 51 (1) to 51 (4) shift the phase of the analog signal by T / 4, and the variable delay devices 34 (1) to 34 (4) are replaced with those shown in FIGS. Similarly to the embodiment, the phase adjustment may be performed by providing the clock signals C1 to C4.

  In the embodiment, the example in which the frequency fr of the reference signal R does not exceed the Nyquist frequency 1 / (2T) of each of the A / D converters 25 (1) to 25 (4) has been described. When the frequency fr exceeds the Nyquist frequency 1 / (2T) of each of the A / D converters 25 (1) to 25 (4), a result equivalent to that obtained by sampling a signal having the difference frequency due to the aliasing phenomenon is obtained. The phase and phase difference of the difference frequency signal can be obtained, and the phase error can be suppressed as described above.

Configuration diagram of an embodiment of the present invention Signal diagram for explaining the operation of the embodiment Diagram showing error frequency characteristics The figure which shows the structure when changing the frequency of the reference signal Diagram showing error frequency characteristics Diagram showing error frequency characteristics Diagram showing the configuration for fine adjustment of the phase on the input signal side The figure which shows the structure in the case of performing T / 4 phase-shift processing and fine adjustment on the input signal side Configuration diagram of conventional equipment Diagram showing the relationship between phase error and spurious

Explanation of symbols

  DESCRIPTION OF SYMBOLS 20 ... A / D converter, 21 ... Reference signal generator, 22 ... Switch, 23 ... Signal distribution part, 25 (1) -25 (4) ... A / D converter, 26, 26 ' ... Clock generator, 31... Phase difference calculating means, 32... Error calculating means, 34 (1) to 34 (4)... Variable delay element, 35. ) …… Delay device

Claims (3)

Signal branching means (23) for branching an analog input signal into a plurality of M;
A plurality of M A / D converters (25 (1) to 25 (4)) that respectively receive the branched signals, sample the clock signals at the input timing, and convert them into digital values;
In the A / D converter of an interleave type in which the A / D converter performs sampling of a predetermined period T with respect to the branched input signal by relatively shifting by T / M,
A reference signal generating means (21) for outputting a reference signal of a known frequency;
When the reference signal is input to the signal branching means, the output value of the plurality of M A / D converters is acquired, and the phase difference of the signal having the output value for each A / D converter as the instantaneous amplitude is calculated. Phase difference calculating means (31) for performing,
An error calculating means (32) for obtaining an error of the phase difference calculated by the phase difference calculating means;
A variable delay device (34 (1) to 34 (4)) for relatively varying each sampling timing with respect to an input signal of each A / D converter;
Control means (35) for controlling the delay amount of the variable delay device so that the error of the phase difference obtained by the error calculation means is reduced ,
The reference signal generating means is configured to selectively output a first reference signal and a second reference signal having different frequencies that are arbitrarily designated,
In the control means, the absolute value of the phase difference error calculated when the first reference signal is input is substantially equal to the absolute value of the phase difference error calculated when the second reference signal is input. As described above , the A / D conversion apparatus controls the delay amount of the variable delay device. Signal branching means (23) for branching an analog input signal into a plurality of M;
A plurality of M A / D converters (25 (1) to 25 (4)) that respectively receive the branched signals, sample the clock signals at the input timing, and convert them into digital values;
In the A / D converter of an interleave type in which the A / D converter performs sampling of a predetermined period T with respect to the branched input signal by relatively shifting by T / M,
A reference signal generating means (21) for outputting a reference signal of a known frequency;
When the reference signal is input to the signal branching means, the output value of the plurality of M A / D converters is acquired, and the phase difference of the signal having the output value for each A / D converter as the instantaneous amplitude is calculated. Phase difference calculating means (31) for performing,
An error calculating means (32) for obtaining an error of the phase difference calculated by the phase difference calculating means;
A variable delay device (34 (1) to 34 (4)) for relatively varying each sampling timing with respect to an input signal of each A / D converter;
Control means (35) for controlling the delay amount of the variable delay device so that the error of the phase difference obtained by the error calculation means is reduced,
The reference signal generating means is configured to output a reference signal on which a plurality of frequency components are superimposed,
The phase difference calculating means is configured to calculate a phase for each frequency component included in the reference signal and calculate the difference, respectively.
The error calculation means is configured to obtain an error of a phase difference for each frequency component,
The control means, the phase difference absolute value substantially to control the delay amount of the variable delay unit to equal you, wherein A / D converter error of each frequency component. The control means makes the absolute value of the error relative to the reference signal of the frequency equal to or close to the upper limit frequency and the lower limit frequency within the frequency band of the allowable input signal or the frequency component included in the reference signal to be equal and opposite in sign. 3. The A / D converter according to claim 1 , wherein a small error region that crosses error 0 is set at a central portion of the frequency band by controlling a delay amount of the variable delay unit.

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