JP4635482B2 - Arbitration device, arbitration method, mediation method program, recording medium recording mediation method program, and electronic still camera - Google Patents

Description

  The present invention relates to an arbitration device, an arbitration method, an arbitration method program, a recording medium on which an arbitration method program is recorded, and an electronic still camera. For example, the present invention can be applied to a configuration in which a plurality of processing circuits share a memory. The present invention is based on the assumption that the access right is set according to the priority, and when the access request from the reference circuit and the access request from the processing circuit having a lower priority than the reference circuit compete, By setting access rights so that the number of access rights set to a processing circuit with a lower priority with respect to the number of access rights is set according to the bandwidth limit value in advance, multiple access rights to the memory, etc. The processing circuit can be set appropriately and efficiently.

  Conventionally, in an electronic still camera, imaging results are sequentially recorded in a memory, and the imaging results recorded in the memory are displayed on a display unit, and the imaging results recorded in the memory are compressed in response to a user operation. The data is recorded on a recording medium such as a memory card. For this reason, in an electronic still camera, an access request to a memory from a plurality of processing circuits related to each of these processes is arbitrated by an arbitration circuit, whereby an imaging result is reliably processed by each processing circuit. .

  In such an arbitration circuit, conventionally, a method of setting an access right according to a fixed priority set in advance, and a round robin method for rotating the priority are adopted.

  However, in the case of arbitration with a fixed priority, there is a problem that the memory access is monopolized by the processing circuit having a high priority, and the memory cannot be accessed in the processing circuit having a low priority. On the other hand, in the case of the round robin method, although such a situation can be effectively avoided, the priority of the processing circuit having a high access frequency is lowered by the change of the priority, and thereby the processing speed in this processing circuit is remarkably increased. There is a problem that decreases.

  As one method for solving these problems, a method of providing a dedicated memory for each processing circuit is also conceivable. However, this method has a problem that the overall configuration becomes complicated and the shape becomes large.

  On the other hand, in JP-A-8-180027, when there is an access request from a low speed processor having a low operating speed, the low speed processor is made to wait for a predetermined number of clocks based on the system clock of the high speed processor having a high operating speed. Methods have been proposed for setting access rights to memory for low speed processors.

However, in this method, even when the high-speed processor is not accessing the memory, the low-speed processor is made to wait for a predetermined clock cycle with respect to the access request. There is a problem that loses. There is also a problem that cannot be applied when there are three or more processing circuits related to a memory access request.
JP-A-8-180027

  The present invention has been made in consideration of the above points. An arbitration device, an arbitration method, an arbitration method program, and an arbitration method that can appropriately and efficiently set an access right to a memory or the like in a plurality of processing circuits. It intends to propose a recording medium on which a program is recorded.

  In order to solve such a problem, the invention of claim 1 is applied to an arbitration device that selectively sets access rights for access requests from a plurality of processing circuits and arbitrates access requests from the plurality of processing circuits. If the access request does not conflict, the access right is set for the processing circuit related to the access request. If the access request conflicts, the access right is set for the access request from the plurality of processing circuits according to the priority order. Thus, when the access request of the reference circuit and the access request of the processing circuit having a lower priority than the reference circuit compete, the priority order is higher than that of the reference circuit and the reference circuit by comparing the count value of the counter with the bandwidth limit value. The access right is selectively set to the processing circuit having a lower priority, the access request of the reference circuit and the access request of the processing circuit having a lower priority than the reference circuit. There in the case of conflict, for setting the number of access to the reference circuit, a predetermined number of access to the lower processing circuit having priority over the reference circuit is set to a value corresponding to the band limit.

  In the invention of claim 11, the access request is applied to an arbitration method for selectively arbitrating access requests from a plurality of processing circuits by selectively setting an access right for the access requests from the plurality of processing circuits. If the access request does not conflict, the access right is set for the processing circuit related to the access request. If the access request conflicts, the access right is set for the access request from the plurality of processing circuits according to the priority order. The access right setting step includes a step of comparing the count value of the counter with the bandwidth limit value when the access request of the reference circuit and the access request of the processing circuit having a lower priority than the reference circuit compete. Access rights are selectively set for the reference circuit and a processing circuit having a lower priority than the reference circuit, and the access request for the reference circuit and the reference circuit are prioritized. The number of access rights set to a processing circuit with a lower priority than the reference circuit is set according to the bandwidth limit value with respect to the number of access rights set to the reference circuit when there is a conflict with an access request of a lower processing circuit. Set to value.

  According to the twelfth aspect of the present invention, an arbitration method for arbitrating access requests from a plurality of processing circuits by selectively setting an access right for the access requests from the plurality of processing circuits by execution by the arithmetic processing means. When the access request does not conflict, the access right is set in the processing circuit related to the access request. When the access request conflicts, the access request from a plurality of processing circuits is processed according to the priority order. An access right setting step for setting an access right. In the access right setting step, when the access request of the reference circuit and the access request of the processing circuit having a lower priority than the reference circuit compete, the count value of the counter And the bandwidth limit value, the access right is selectively set to the reference circuit and the processing circuit having a lower priority than the reference circuit. When the access request of the reference circuit and the access request of the processing circuit having a lower priority than the reference circuit conflict, the access right to the processing circuit having a lower priority than the reference circuit is set for the number of times the access right to the reference circuit is set. Set the number of settings to a value according to the bandwidth limit value.

  Further, in the invention of claim 13, an arbitration method for arbitrating access requests from a plurality of processing circuits by selectively setting an access right for the access requests from the plurality of processing circuits by execution by the arithmetic processing means. When the access request does not conflict, the arbitration method program sets the access right to the processing circuit related to the access request, and the access request conflicts according to the priority order. An access right setting step for setting an access right for an access request from a plurality of processing circuits. The access right setting step includes an access request for a reference circuit and an access to a processing circuit having a lower priority than the reference circuit. In case of contention with the request, the priority order is higher than the reference circuit and reference circuit by comparing the count value of the counter with the bandwidth limit value. When the access right is selectively set to a lower processing circuit and the access request of the reference circuit and the access request of the processing circuit having a lower priority than the reference circuit compete, the reference for the number of times of setting the access right to the reference circuit The number of times of setting the access right to the processing circuit having a lower priority than the circuit is set to a value corresponding to the bandwidth limit value.

  According to the fourteenth aspect of the present invention, the arbitration circuit is applied to an electronic still camera that displays an imaging result on a recording medium and records it on a recording medium, and displays the imaging result recorded on the recording medium on the monitor. If there is no conflict, the access right is set for the circuit related to the access request. If the access request conflicts, the access right is set for the access request from a plurality of circuits according to the priority order. When access requests of lower priority circuits than the reference circuit compete, the access right is selectively set to the reference circuit and lower priority circuits than the reference circuit by comparing the count value of the counter with the bandwidth limit value. The access right to the reference circuit when the access request of the reference circuit and the access request of the circuit having a lower priority than the reference circuit conflict For the set number of times, the set number of access to the lower circuit of priority than the reference circuit is set to a value corresponding to the band limit.

  According to the configuration of claim 1, when the access request does not conflict when applied to the arbitration device, an access right is set in the processing circuit related to the access request, and when the access request conflicts, a plurality of processing circuits are arranged according to the priority order. When the access right is set to the access request from the reference circuit and the access request of the reference circuit and the access request of the processing circuit having a lower priority than the reference circuit conflict, the count value of the counter and the bandwidth limit value By comparison, the access right is selectively set to the reference circuit and the processing circuit having a lower priority than the reference circuit, and the access request of the reference circuit and the access request of the processing circuit having the lower priority than the reference circuit compete. The number of access rights set to a processing circuit with a lower priority than the reference circuit is set to the bandwidth limit value with respect to the number of access rights set to the reference circuit. If set to Flip value can be set by distributing the access in accordance with the band-limit value and lower processing circuit priority than a reference circuit and a reference circuit. Thereby, the access right can be appropriately set by the bandwidth limit value in the reference circuit and the processing circuit having a lower priority than the reference circuit. In addition, when the access right does not conflict, the access right can be set in the processing circuit related to the access request, so that the access right can be efficiently set by effectively avoiding the occurrence of idle time. Access rights to memories and the like can be set appropriately and efficiently in a plurality of processing circuits.

  As a result, according to the configurations of claims 11, 12, 13, and 14, the arbitration method, the arbitration method program, and the arbitration method can set the access right to the memory and the like appropriately and efficiently. A recording medium on which a program is recorded and an electronic still camera can be provided.

  According to the present invention, an access right to a memory or the like can be set appropriately and efficiently in a plurality of processing circuits.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 2 is a block diagram showing an arbitration system applied to this embodiment. The arbitration system 1 is applied to a configuration in which data recorded in the memory 2 is processed by, for example, a plurality of MPUs (Micro Processing Units) c1 to cn + 2, and more specifically, the data recorded in the memory 2 is an image. It is applied to electronic still cameras that are data.

  Thereby, in this arbitration system 1, MPUc1 to cn + 2 execute the processing procedure assigned to each MPUc1 to cn + 2, respectively, and sends access request signals a1 to an + 2 requesting access to the memory 2 to the control circuit 3, Further, the memory 2 is accessed via the bus BUS by access permission signals b1 to bn + 2 that permit access to the memory 2 in response to the access request signals a1 to an + 2.

  The control circuit 3 controls access to the memory 2 according to access requests from the MPUs c1 to cn + 2. That is, in this control circuit 3, the transceiver circuit 4 receives the address to be written and read from the MPUc1 to cn + 2 related to access permission via the bus BUS and outputs it to the memory controller 6 under the control of the arbitration circuit 5. Data relating to this address is input / output between the MPUs c1 to cn + 2 and the memory controller 6. The memory controller 6 records the sequentially input data in the memory 2 by the memory transfer start signal e output from the arbitration circuit 5, and the data recorded in the memory 2 by the address output from the transceiver circuit 4. Read out and output to the transceiver circuit 4.

  The arbitration circuit 5 arbitrates access requests from the MPUs c1 to cn + 2, sets access rights, and outputs access permission signals b1 to bn + 1 and a memory transfer start signal e. In this embodiment, as shown in FIG. 3, the arbitration circuit 5 gives priority orders P1 and P2 for granting access permission to the MPUc1 to cn + 2 to an upper controller (not shown) that controls the operation of the entire arbitration system 1. A plurality of types are held, and the controller sets one of the priority orders P1 and P2 in the arbitration circuit 5.

  In the bandwidth setting register 7, a reference circuit for specifying one of MPUc1 to cn + 2, which is a processing circuit to be arbitrated, is registered by a controller that controls the operation of the arbitration system 1 as a whole. Bandwidth limitation that indicates the number of access rights set to an MPU having a lower priority than the reference circuit, relative to the number of access rights set to the reference circuit, when an access request conflicts with an MPU having a lower priority A value L is set.

  The arbitration circuit 5 is provided with an access right setting counter that is set to an initial value by setting the access right to the reference circuit and counts the access right setting to the MPU having a lower priority than the reference circuit. The access right to the memory 2 is set to each of the MPUc1 to cn + 2 by the access request from the MPUc1 to cn + 2 based on the count value N of the right setting counter, the priority orders P1 and P2, the reference circuit, and the band limit value L. In this embodiment, the arbitration circuit 5 determines the access right to the MPU having a lower priority by the access right setting counter only when the access request conflicts between the reference circuit and the MPU having a lower priority than the reference circuit. Count settings.

  FIG. 4 is a state transition diagram showing the transition of the count value N of the access right setting counter. Immediately after activation, the arbitration circuit 5 sets the count value N of the access right setting counter to the value 0, and in this state, when receiving an access request from the reference circuit, as shown by an arrow A1, The count value N of the counter is set to an initial value of value 1. On the other hand, when the count value N of the access right setting counter is 0 and the access request is not received from the reference circuit, the count value N of the access right setting counter is set as indicated by an arrow A2. Hold at zero. In the case where the access request is not received from the reference circuit in this way, if the access request cannot be obtained from the reference circuit, the access request competes between the reference circuit and the MPU having a higher priority than the reference circuit. This is the case where an access right is set for a high MPU.

  When an access request from the reference circuit is received and the count value N of the access right setting counter is set to an initial value of 1, an access right is set for this access request and the access request is accepted. When completed, as indicated by the arrow A3, the count value N of the access right setting counter is held as it is.

  On the other hand, when an access request is received from an MPU having a lower priority than the reference circuit while the count value N of the access right setting counter is held, the access right setting counter When the count value N is incremented by 1 and acceptance of this access request is completed, the count value N of the access right setting counter is held as indicated by an arrow A5.

  On the other hand, when the access right is set to an MPU having a higher priority than the reference circuit while the count value N of the access right setting counter is held, the access right is set to the reference circuit by an access request that does not conflict at all. If no access right is set, the count value N of the access right setting counter is held at the previous value as indicated by an arrow A6.

  On the other hand, when the count value N of the access right setting counter is held and the count value N matches the band limit value L and an access request from the reference circuit is received, as shown by an arrow A7, The count value N of the access right setting counter is set to an initial value of value 1.

  On the other hand, when the contents of the band setting register 7 are updated by the controller that controls the overall operation of the arbitration system 1, the count value N of the access right setting counter is set to 0 as indicated by arrows A8 and A9. Set.

  Thus, the arbitration circuit 5 sets the count value N to an initial value of 1 by setting the access right to the reference circuit, and sets the access right to the MPU having a lower priority than the reference circuit. The set number of times is sequentially counted by a counter.

  The arbitration circuit 5 executes the processing procedure shown in FIGS. 1 and 5 on the basis of the count value N, the priority orders P1 and P2, the reference circuit, and the band limit value L, thereby storing the memory 2 in each MPUc1 to cn + 2. Set access rights to. In this embodiment, the programs relating to the processing of FIGS. 1 and 5 and the processing of the counter described above with reference to FIG. 4 are installed and provided in advance, but via a network such as the Internet. It may be provided by downloading, or may be provided via various recording media. In such a recording medium, various recording media such as a memory card and an optical disk can be widely applied.

  That is, when the arbitration circuit 5 starts this processing procedure by starting up the power supply, the process proceeds from step SP1 to step SP2, and the controller that controls the operation of the entire arbitration system 1 receives the priority and the specification of the reference circuit. In response to the setting of the limit value L, the contents of the band setting register 7 are updated, and in the following step SP3, the arbitration process is started. In the subsequent step SP4, the arbitration circuit 5 determines whether or not an access request is obtained from any MPU. If a negative result is obtained here, the arbitration circuit 5 repeats step SP4. Thereby, the arbitration circuit 5 waits for an access request from the MPU, and when an access request is obtained from any of the MPUs, the process proceeds from step SP4 to step SP5.

  In step SP5, the arbitration circuit 5 determines whether or not the band limit value L of the band setting register 7 is set to an effective value equal to or greater than 2, and when a negative result is obtained, the process proceeds to step SP6. Then, based on the priority order P1 or P2 set in step SP2, it is determined whether or not the MPU related to the access request includes a processor having a higher priority order than the reference circuit. If an affirmative result is obtained here, the arbitration circuit 5 moves from step SP6 to step SP7, and after setting the access right for the MPU having the highest priority among the MPUs requested to access according to the priority, Control goes to step SP8.

  On the other hand, if a negative result is obtained in step SP6, the arbitration circuit 5 moves to step SP9, where it determines whether or not the MPU related to the access request includes a reference circuit. If a positive result is obtained here, the arbitration circuit 5 moves from step SP9 to step SP10, sets the access right to the reference circuit, and then moves to step SP8.

  On the other hand, if a negative result is obtained in step SP9, the arbitration circuit 5 moves to step SP11, and determines whether or not the MPU related to the access request includes an MPU having a lower priority than the reference circuit. . If an affirmative result is obtained here, the arbitration circuit 5 moves from step SP11 to step SP12, and after setting the access right to the MPU having the highest priority among the MPUs requested to access according to the priority, Control goes to step SP8. Even if a negative result is obtained in step SP11, the arbitration circuit 5 proceeds to step SP8.

  As a result, when the bandwidth limit value L of the bandwidth setting register 7 is not set to a valid value, the arbitration circuit 5 sets the access right according to the priority order instructed by the host controller and requests access from the MPUs c1 to cn + 2. Has been made to mediate. When the arbitration circuit 5 arbitrates the access request in this way, in step SP8, it determines whether or not the priority order P1 and P2 in the upper controller is instructed, and whether or not the upper controller has instructed to change the band setting register 7. If an affirmative result is obtained here, the process proceeds to step SP2, where the update of the priority order change contents and the contents of the band setting register 7 are updated, and the priority order and the change of the reference circuit are accepted. If a negative result is obtained, the process proceeds to step SP3 and the subsequent processing is executed.

  On the other hand, when the band limit value L of the band setting register 7 is set to an effective value of 2 or more, the arbitration circuit 5 obtains an affirmative result at step SP5, so that the process proceeds from step SP5 to step SP14. Move (Figure 5). Here, the arbitration circuit 5 determines whether the MPU related to the access request includes a processor having a higher priority than the reference circuit. If a positive result is obtained here, the arbitration circuit 5 moves from step SP14 to step SP15, and after setting the access right to the MPU having the highest priority among the MPUs requested to access according to the priority, Control goes to step SP8. As a result, the arbitration circuit 5 sequentially sets access rights according to the priority setting when there is an access request from an MPU having a higher priority than the reference circuit.

  On the other hand, if a negative result is obtained in step SP14, the arbitration circuit 5 proceeds from step SP14 to step SP16. Here, the arbitration circuit 5 determines whether or not the MPU related to the access request is a reference circuit. If an affirmative result is obtained, the arbitration circuit 5 proceeds from step SP16 to step SP17, and the MPU related to the access request has a higher priority than the reference circuit. Determine whether lower-level processors are included. If an affirmative result is obtained here, the arbitration circuit 5 proceeds from step SP17 to step SP18, determines whether the count value N of the access right setting counter is a value 0 or a value L, and here an affirmative result is obtained. Then, the process proceeds to step SP19, an access right is set for the access request from the reference circuit, and the process proceeds to step SP8.

  As a result, the arbitration circuit 5 is provided on condition that the count value N of the access right setting counter is 0 or 1 when an access request conflicts between the reference circuit and a processor having a lower priority than the reference circuit. The access right is set in the reference circuit.

  On the other hand, if a negative result is obtained in step SP18, the arbitration circuit 5 proceeds from step SP18 to step SP20. Here, the arbitration circuit 5 determines whether or not the access request from the reference circuit is an access request for a read request related to cache write-back, and when a negative result is obtained, the process proceeds from step SP20 to step SP21, The access request is made to wait, and the access right is set in accordance with the priority order in the processor whose remaining priority order is lower than that of the reference circuit, and the process proceeds to step SP8.

  As a result, the arbitration circuit 5 is in the case where the access request conflicts between the reference circuit and the processor having a lower priority than the reference circuit, and the count value N of the access right setting counter is a value other than 0 or 1 The access request from the reference circuit is made to wait, and the access right is set to the lower processor according to the priority order.

  Therefore, in the count value N of the access right setting counter which is the determination criterion in step SP18, as described above with reference to FIG. When the access right is set, the bandwidth limit value L related to the count value N of the access right setting counter is set to the value 5, and the reference circuit is set to MPUcn. As shown in FIG. 6 with reference to the clock CK of FIG. 5 (FIG. 6A), for example, at the time T1, the access request of the MPUcn that is the reference circuit and the lower priority MPUcn + 1 and cn + 2 competes in the initial state. In the case (FIG. 6 (B1), (C1) and (D1)), the arbitration circuit 5 sets the access right to the reference circuit (FIG. 6 (B2 , (C2), (D2) and (E)), and updates the count value N of the counter for access right setting from the value 0 to the value 1 (FIG. 6 (F)).

  When the processing for setting the access right is completed, the access request of the reference circuit cn is waited until the count value N of the access right setting counter reaches the bandwidth limit value L, and the upper and lower processors are made to wait. The access right is sequentially set according to the priority order, and the count value N of the access right setting counter is incremented by setting the access right for the lower processor. Accordingly, in the example of FIG. 6, the access request for the lower order MPUcn + 1, cn + 2 is waiting in the setting of the access right related to the processing cycle at the time point T1, so that the lower order MPUcn + 1, cn + 2 An access right is set to MPUcn + 1 having a higher priority with respect to the access request, and the count value N of the access right setting counter is updated from the value 1 to the value 2. At the subsequent time T3, the access request from the reference circuit cn rises despite the fact that the access request from the reference circuit cn has risen, and the access right is set for the access request of MPUcn + 2, in which case the access request is also obtained from the reference circuit. As a result, the count value N of the access right setting counter is updated from the value 2 to the value 3.

  Further, at the subsequent time T4, the access request of the reference circuit cn is further waited, and the access right is set for the access request of MPUcn + 1. In this case as well, the access right setting counter counts due to the conflicting access requests. The value N is updated from the value 3 to the value 4. Further, at the subsequent time T5, the access request of the reference circuit cn is further waited, the access right is set for the access request of MPUcn + 2, the count value N of the access right setting counter is updated from the value 4 to the value 5, Here, when the count value N coincides with the bandwidth limit value L, the access right is set for the access request of the reference circuit cn that has been waiting until then at time T6.

  As a result, the reference circuit cn sets the access right in response to the access request of the host processor, and the remaining access right bandwidth is stored in the memory 2 at least once in a plurality of processing cycles according to the bandwidth limit value L. It has been made accessible. As a result, in the arbitration system 1, the access right is set according to the priority order so that the access right to the memory 2 can be secured at least for the reference circuit by the bandwidth limit value L. Thus, the access right to the memory can be set appropriately and efficiently in a plurality of processing circuits. Further, even in the MPU having a lower priority than the reference circuit, it is possible to secure the remaining bandwidth by setting the access right to the reference circuit in the same manner, and thereby the access right to the memory can be set appropriately and efficiently. It has been made possible.

  On the other hand, if a negative result is obtained in step SP17, the arbitration circuit 5 moves from step SP17 to step SP22. In this case, the access request is not obtained from a processor other than the reference circuit, so that the reference circuit The access right is set, and the process proceeds to step SP8. If a negative result is obtained in step SP16, in this case, the process moves from step SP16 to step SP23, the access right is set according to the priority order, and the process returns to step SP8. As a result, in the arbitration system 1, when there is a margin in the bandwidth related to the access to the memory 2, the access right is set in the reference circuit beyond the bandwidth limit by the bandwidth limit value L. An access right is set to the processor, and the access to the memory 2 is efficiently executed accordingly.

  That is, in contrast to FIG. 6, when the bandwidth limit value L related to the count value N of the access right setting counter is set to 3 and the reference circuit is set to MPUcn, as shown in FIG. When the access request of MPUcn, which is the reference circuit, and MPUcn + 1, which has a lower priority, competes at T1 (FIGS. 7A, 7B, 1C1 and 1D1), the arbitration circuit 5 becomes the reference circuit. The access right is set (FIG. 7 (B2), (C2), (D2) and (E)), and the count value N of the access right setting counter is set from 0 to 1 (FIG. 7 (F)). . At the subsequent time T2, the access right is set for the access request of the lower order MPUcn + 1 waiting for the access request. In this case, the access request conflicts with the reference circuit. The count value N is updated from the value 1 to the value 2. Accordingly, also in this case, the arbitration circuit 5 sequentially sets the access right according to the priority order while sequentially updating the count value N of the access right setting counter.

  When an access request is obtained only from the reference circuit at time T3 that continues in this manner, the arbitration circuit 5 sets an access right for the access request from the reference circuit cn. In this case, the count value N of the access right setting counter is held at the value 2 by the transition indicated by the symbol A6 described above with reference to FIG. As a result, the arbitration circuit 5 prevents unnecessary idle periods and sets an extra access right to the reference circuit cn.

  At the subsequent time point T4, when access requests of the lower processors cn + 1 and cn + 2 are competing, the access right is set to the processor cn + 1 having the higher priority, and the count value N of the access right setting counter is set from the value 2. Update to value 3. Further, at the subsequent time T5, an access request is obtained only from the processor cn + 2 of the subsequent priority level, so that an access right is set for the access request of the processor cn + 2, and this case is also indicated by the symbol A6 described above with reference to FIG. By the transition, the count value N of the access right setting counter is held at the value 3. As a result, the arbitration circuit 5 also prevents useless idle periods and sets the access right for processors other than the reference circuit cn.

  Therefore, the arbitration circuit 5 obtains an access request from the reference circuit at the subsequent time T6 when the count value N of the access right setting counter coincides with the bandwidth limit value L in the processing cycle related to the time T4. Then, the access right is set to the access request of the reference circuit, and the count value N of the access right setting counter is set to an initial value of 1.

  On the other hand, if a positive result is obtained in step SP20, in this case, the arbitration circuit 5 moves from step SP20 to step SP19 and sets the access right in the reference circuit.

  As a result, when the band limit value L is set to 3 and the reference circuit is set to MPUcn by comparison with FIG. 6, the arbitration circuit 5 has the MPUcn which is the reference circuit at the time T1, for example, as shown in FIG. When the access requests of the lower priority MPUcn + 1 and cn + 2 compete (FIG. 8 (A), (B1), (C1) and (D1)), the access right is set in the reference circuit (FIG. 8 (B2 ), (C2), (D2) and (E)), and the count value N of the access right setting counter is set from the value 0 to the value 1 (FIG. 8F). At a subsequent time T2, when a read request after receiving a write-back memory access request is obtained from the reference circuit, the access right is transferred to the reference circuit while the count value N of the access right setting counter is held at 1. Set.

  As a result, the arbitration circuit 5 writes back the data in the cache to the memory if the reference circuit is a write-back type cache system and a cache miss occurs when the cache system is read. Thereafter, when reading from the memory, an access right is set preferentially for an access request related to the read, thereby improving the efficiency of the cache system in the reference circuit.

  In the example of FIG. 8, at the subsequent time points T3 and T4, the access rights are sequentially set to the MPUcn + 1 and cn + 2 waiting for the access requests, respectively, and the count value N of the counter is sequentially incremented. Yes.

  In comparison with FIG. 8, the band limit value L is set to 2, the reference circuit is set to MPUcn, and the higher and lower priority processors than the reference circuit are set to MPUcn-1 and MPUcn + 1. As shown in FIG. 9, in the preferential processing of the read request related to such write back, the arbitration circuit 5 has an access request from a higher priority processor for the higher priority processor. Priority is given to the setting of access rights.

  In other words, in this case, the arbitration circuit 5 causes the MPUcn that is the reference circuit and the access request of the MPUcn + 1 having the lower priority to compete at the time T1, for example, at the time T1 (FIGS. 9A, 9B, and 1C1). And (D1)), the access right is set in the reference circuit (FIG. 9 (B2), (C2), (D2) and (E)), and the count value N of the access right setting counter is changed from the value 0 to the value 1. The setting is made (FIG. 9F). Further, at a subsequent time T2, when a write-back memory access request is generated and there is an access request from an MPUcn-1 having a higher priority than the reference circuit, an access right is set to the MPUcn-1 having a higher priority. The access request related to the read request from the reference circuit is made to wait. At the subsequent time T3, when the access request of the MPUcn + 1 with the lower priority is competing with the reference circuit, the access request related to the read request of the reference circuit is set with priority.

  In the example of FIG. 9, when an access request is obtained again from MPUcn-1 having a higher priority at the subsequent time point T4, the arbitration circuit 5 sets an access right to this MPUcn-1, and at the subsequent time point T5. The access right is set to MPUcn + 1 having the lowest priority, and at this time, the count value N of the counter is updated from the value 1 to the value 2 for the first time.

  Thus, the access right is set for each access request in this way, and in step SP8, the arbitration circuit 5 instructs to change the priority order P1, P2 in the upper controller, and the bandwidth setting register from the upper controller. 7 is determined, and by executing the processing of step SP2 and step SP3 based on the determination result, the priority order setting, the reference circuit setting, and the bandwidth limit value L for this series of processing are obtained. In accordance with the instruction from the host controller, it is changed as appropriate according to the overall processing status, and this also allows the right to access the memory to be set appropriately and efficiently in a plurality of processing circuits. Yes.

(2) Operation of the embodiment In the above configuration, in the arbitration system 1, the access right is selectively set to the MPUc1 to cn + 2 that has transmitted the access request by the arbitration circuit 5 in response to the access request from the MPUc1 to cn + 2. The addresses are sent to the bus BUS by the MPUs c1 to cn + 2 to which the access right is set, and the memory 2 is accessed.

  In the arbitration system 1, when such arbitration processing is started, a reference circuit for identifying one of the priority orders P1, P2, and MPUc1 to cn + 2 of the access right setting processing is registered by the host controller. When access requests compete between the circuit and the MPU having a lower priority than the reference circuit, the number of access rights set to the MPU having a lower priority than the reference circuit is set with respect to the number of access rights set to the reference circuit. Is set.

  In the arbitration system 1, when the access request does not conflict, the access right is set for the MPU related to the access request, whereas when the access request conflicts, the access right is set according to the priority order. . As a result, for example, MPUs related to real-time processing that are required to shorten the waiting time until an access right is issued after issuing an access request, set a high priority, and conversely, for example, back For MPUs related to processing that does not require real-time processing such as ground processing, priority can be set low, and access rights can be set appropriately for each MPU.

  However, if this is done, an MPU with a low priority may not be able to acquire an access right at all. Thereby, in this embodiment, when the access right competes between the reference circuit and the MPU having a lower priority than the reference circuit, the access right is set in the reference circuit and the count value of the access right setting counter is set to the value. When the access right competes with the MPU having a lower priority than the reference circuit and the reference circuit, the setting of the access right to the processing circuit having a lower priority than the reference circuit is counted. When the count value N is 1, the setting of the access right to the reference circuit is stopped, the access right is set to the MPU having a lower priority than the reference circuit according to the priority, and the count value N of the counter is the bandwidth limit value. When the access right conflicts between the reference circuit and the MPU having a lower priority than the reference circuit, the access right is set in the reference circuit.

  As a result, an access right is set to an MPU having a higher priority than the reference circuit, and the remaining bandwidth related to access to the memory 2 is changed to a MPU having a lower priority than the reference circuit and the reference circuit by the ratio of the bandwidth limit value L. The access right can be secured even in the MPU having a low priority. As a result, the access right can be set appropriately.

  In addition, when there is no contention between access requests, it is possible to effectively avoid the generation of useless idling time by setting the access right to the MPU related to the access request, thereby efficiently setting the access right. Can do.

  Thus, by setting the access right to the reference circuit according to the count value N of the counter as described above, the access right is set to the MPU having the lower priority, and the access right is set for the MPU having the lower priority. Are set in accordance with the priority order, the access right is set to the MPU having a high priority order, and the bandwidth related to the access to the remaining memory 2 is set to the priority order of the reference circuit and the reference circuit by the ratio of the bandwidth limit value L. By assigning to lower MPUs, it is possible to appropriately allocate access rights among MPUs having lower priority than the reference circuit by setting priorities, and this also makes it possible to set access rights more appropriately. it can.

  Also, even on the higher priority side than the reference circuit, by setting the access right according to the priority order, it is possible to appropriately distribute the access right on the higher priority side by setting the priority order. It is possible to set the access right more appropriately.

  In this way, the access right is set based on the count value of the counter as a reference N, and in this counter, only when access requests compete in the reference circuit and the MPU having a lower priority than the reference circuit. The access right setting to the processing circuit having a lower priority than the reference circuit is counted, and if the access request from the reference circuit or the MPU having the lower priority than the reference circuit does not compete, the access request The access right is set in the reference circuit or the MPU, and when the access right does not conflict at all, the access right is set in the MPU related to the access request and the access right is set efficiently. Bandwidth limitation only when access requests compete with the MPU having a lower priority than the reference circuit L makes it possible to distribute the access rights. As a result, the access right can be allocated by the bandwidth limit value L only when there is no allowance for access to the memory 2, and the access right can be set appropriately accordingly.

  In the case where the reference circuit is a write-back cache system, when the cache system is read, data in the cache is written back to the memory 2 due to a cache miss, and access related to the read immediately after this write-back is performed. With respect to the request, the access value is preferentially set in the reference circuit while ignoring the counter value N, thereby improving the efficiency of the cache system in the reference circuit.

  Also, when an access request related to such a read conflicts with an access request of an MPU having a higher priority than the reference circuit, an access right is set for the MPU having a higher priority, thereby processing the MPU having a higher priority. Priority can be set and access right can be set appropriately.

  In the arbitration system 1, the access right is sequentially set by setting the priority order, setting the reference circuit, the bandwidth limit value L, and the count value N as described above, and these values are set according to an instruction from the host controller. The access right setting can be appropriately changed according to the status of the entire process, and accordingly, the access right to the memory can be set appropriately and efficiently in a plurality of processing circuits. It has been made possible.

(3) Effects of the embodiment According to the above configuration, on the premise that the access right is set according to the priority order, the access request from the reference circuit and the access request from the processing circuit having a lower priority order than the reference circuit If there is a conflict, the access right should be set so that the number of times the access right is set to the processing circuit with a lower priority with respect to the number of times the access right is set to the reference circuit becomes a value corresponding to the bandwidth limit value in advance. Thus, the access right to the memory or the like can be set appropriately and efficiently in a plurality of processing circuits.

  In addition, by setting the access right to the processing circuit having a lower priority than the reference circuit in accordance with the priority order, the number of times of setting the access right to the reference circuit and the access right to the processing circuit having the lower priority are set in this way. By setting the access right so that the number of times of setting is a value corresponding to the bandwidth limit value in advance, it is possible to appropriately set the access right according to the priority even on the lower priority side.

  Also, when there is an access request from a processing circuit having a higher priority than the reference circuit, the access right is set to the processing circuit having a higher priority than the reference circuit according to the priority, so that the higher priority is given. Also, the access right can be set appropriately according to the priority order.

  In addition, when the access request setting count by the counter which is a reference for setting the access right has a lower priority than the reference circuit and the processing circuit having a lower priority than the reference circuit, a process having a lower priority than the reference circuit It is the number of times the access right is set to the circuit, and when the access request from the processing circuit having a lower priority than the reference circuit or the reference circuit does not compete, by setting the access right to the reference circuit or the processing circuit related to the access request, Only when there is no allowance for access to the memory 2, the access right can be assigned by the bandwidth limit value, and the access right can be set appropriately accordingly.

  Also, when the reference circuit is a write-back cache system, an access right is set for an access request related to a write-back to the memory, and an access request related to a subsequent read request from the memory is prioritized. By setting the access right to the reference circuit, the efficiency of the cache system in the reference circuit can be improved.

  Also, when an access request related to such a read conflicts with an access request of an MPU having a higher priority than the reference circuit, an access right is set for the MPU having a higher priority, thereby processing the MPU having a higher priority. Priority can be set and access right can be set appropriately.

  Also, by updating the priority setting, reference circuit setting, and bandwidth limit value related to such processing, the access right setting can be changed as appropriate according to the overall processing status, thereby making access The right can be set appropriately and efficiently in a plurality of processing circuits.

  FIG. 10 is a block diagram illustrating an electronic still camera according to Embodiment 2 of the present invention. In the electronic still camera 11, the arbitration of the access request to the memory according to the first embodiment is applied to the arbitration of the access request to the bus BUS.

  That is, in the electronic still camera 11, the image sensor 12 is a solid-state image sensor such as a CCD (Charge Coupled Device), a CMOS (Complementary Metal-Oxide Semiconductor), and the like, and is output from a V driver 14 provided in the preprocessing circuit 13. It operates according to various timing signals and outputs imaging results.

  The preprocessing circuit 13 processes the output signal of the imaging element 12 and outputs image data based on the imaging result. That is, in the preprocessing circuit 13, the timing generator (TG) 15 generates and outputs various timing signals necessary for the operation of the electronic still camera 11, and the V driver 14 generates various timing signals generated by the timing generator 15. A timing signal used to drive the image sensor 12 is generated and output from the timing signal. The signal processing circuit 16 corrects the gain by AGC (Automatic Gain Control) after performing correlated double sampling (CDS) on the output signal of the image sensor 12. Further, it is converted into a digital signal by an ADC (Analog to Digital Converter) circuit, thereby outputting image data.

In this electronic still camera 11, image data obtained as a result of imaging is acquired via the preprocessing circuit 13, and a central processing unit (CPU: Central) is activated in response to an operation by the user.
By controlling the operation of a DSP (Digital Signal Processor) 19 or the like by the Processing Unit) 18, the imaging result obtained by the pre-processing circuit 13 is confirmed by the monitor 20, recorded on the recording medium 21, and recorded in this way. The imaging result recorded on the medium 21 can be confirmed on the monitor 20.

  For this reason, the central processing unit 18 responds to the operation of the operator 23 which is a user interface, and uses an EEPROM (Electrically Erasable Programmable Read-Only Memory) using a random access memory (RAM) 24 which is a work memory. ) Control the operation of each unit by executing the program recorded in 25. In this control, the central processing unit 18 controls the operation of the DSP 19 by data communication with the DSP 19, and the external memory of the DSP 19 A memory 27 temporarily stores image data related to the imaging result and processes the image data.

  That is, the monitor 20 is formed by a liquid crystal display (LCD) or the like, and displays an image based on image data output from the DSP 19. The recording medium 21 is recording means that is detachably held in the electronic still camera 11. For example, a so-called memory card using a semiconductor memory, an optical disk such as a DVD (Digital Versatile Disk), a CD (Compact Disc), or a hard disk device. Etc. apply. The memory 27 is composed of, for example, an SDRAM (Synchronous Dynamic Random Access Memory), and temporarily records and holds image data related to the processing of the DSP 19.

  On the other hand, the DSP 19 executes a predetermined processing program under the control of the central processing unit 18 to process the image data output from the preprocessing circuit 13 and display it on the monitor 20 and record it on the recording medium 21. To do. On the contrary, the image data recorded on the recording medium 21 is displayed on the monitor 20. In this embodiment, the DSP 19 processing program is installed and provided in advance, but may be provided by downloading via a network such as the Internet. It may be provided via a recording medium. In such a recording medium, various recording media such as a memory card and an optical disk can be widely applied.

  That is, in the DSP 19, a bus interface unit (BIU) 29 is an interface used for data communication with the central processing unit 18, and commands from the central processing unit 18 to each part of the DSP 19 via the bus BUS. In addition, the response of each part by the notification of this command is acquired via the bus BUS and notified to the central processing unit 18.

  The camera signal processing circuit 30 switches its operation according to a command from the central processing unit 18 obtained via the bus BUS, and is sequentially output in synchronization with driving of the image sensor 12 from the preprocessing circuit 13 when capturing image data. Image data is acquired, subjected to white balance adjustment and gamma correction, and recorded in the memory 27 via the memory control circuit 31. When the capture processing is completed in this way, the image data recorded in the memory 27 is acquired via the memory control circuit 31, and the image data is converted into image data using red, green, and blue color data. The image data based on the color data is recorded in the memory 27 via the memory control circuit 31. As a result, the camera signal processing circuit 30 processes the image data by real-time processing synchronized with the driving of the image sensor 12 at the time of capture and stores it in the memory 27, while such real-time processing is performed after the capture. And the image data recorded in the memory 27 is sequentially processed.

  The resolution conversion circuit 32 switches the operation by a command from the central processing unit 18 obtained through the same bus BUS, acquires the image data stored in the memory 27 through the memory control circuit 31, and converts the resolution. Then, it is stored in the memory 27 via the memory control circuit 31. The codec 33 switches its operation in accordance with a command from the central processing unit 18 obtained via the same bus BUS, acquires the image data held in the memory 27 via the memory control circuit 31, and obtains JPEG (Joint Photographic Coding). Data is compressed by an Experts Group), MPEG (Moving Picture Experts Group), etc., and output to the media control circuit 35. Further, the image data output from the media control circuit 35 is acquired and decompressed and stored in the memory 27 via the memory control circuit 31. The media control circuit 35 switches the operation according to a command from the central processing unit 18 obtained via the same bus BUS, and records the output data of the codec 33 on the recording medium 21. On the contrary, the image data recorded on the recording medium 21 is read, and this image data is output to the codec 33. Accordingly, the resolution conversion circuit 32, the codec 33, and the media control circuit 35 sequentially process the image data recorded in the memory 27 or the recording medium 21.

  The display control circuit 36 switches the operation by a command from the central processing unit 18 obtained through the same bus BUS, acquires the image data stored in the memory 27 through the memory control circuit 31, and this image data. To drive the monitor 20. Thus, the display control circuit 36 processes the image data recorded in the memory 27 by real-time processing synchronized with the drive of the monitor 20.

  Thus, in the DSP 19, the image data output from the preprocessing circuit 13 is processed by the camera signal processing circuit 30 and stored in the memory 27 at the time of capture by the operations of these units 30 to 36. Further, the image data held in the memory 27 by this capture is processed by the camera signal processing circuit 30 and temporarily stored in the memory 27. Then, the image size is changed by the resolution conversion circuit 32 and stored in the memory 27, and then displayed. This image data is read out by the control circuit 36 and used for driving the monitor 20, whereby the imaging result can be confirmed on the monitor 20.

  In parallel with these processes, the image data held in the memory 27 by capture is separately stored in the memory 27 after the image size is changed by the resolution conversion circuit 32, and then the data is compressed by the codec 33 to the media. Recording is performed on the recording medium 21 by the control circuit 35.

  On the other hand, when monitoring the imaging result of the image data recorded on the recording medium 21 in this way, the image data recorded on the recording medium 21 is decompressed by the codec 33 and temporarily stored in the memory 27. The image data is read out by the display control circuit 36 and used for driving the monitor 20, so that it can be confirmed by the monitor 20.

  Thus, in the DSP 19, the memory 27 is accessed by a plurality of processing circuits including the camera signal processing circuit 30, the resolution conversion circuit 32, the codec 33, and the display control circuit 36, and the bus BUS provided for this access is connected to these processing circuits. The BIU 29 and the media control circuit 35 are used in common. As a result, the DSP 19 arbitrates bus access requests from these units by an arbitration circuit provided in the memory control circuit 31.

  However, the arbitration circuit provided in the memory control circuit 31 has the same configuration as that of the arbitration circuit described above with respect to the first embodiment except that the access request related to arbitration relates to an access request for occupying the bus. Thus, the access right of the bus BUS is set appropriately and efficiently by setting the priority order, setting the reference circuit, and setting the bandwidth limit value.

  Further, in the electronic still camera 11, the first and second priorities are selectively set in the arbitration circuit under the control of the central processing unit 18. Here, the first priority order is set to the order of the display control circuit 36, the camera signal processing circuit 30, the BIU 29, the resolution conversion circuit 32, the codec 33, and the media control circuit 35, while the second priority order is set. As for the priority order, the order of the camera signal processing circuit 30 and the BIU 29 in the first priority order is interchanged, and the display control circuit 36, the BIU 29, the camera signal processing circuit 30, the resolution conversion circuit 32, the codec 33, and the media control circuit 35. The priority order is set to the order.

  The central processing unit 18 sets the first priority in the arbitration circuit at the time of capture, thereby giving priority to the display control circuit 36 and the camera signal processing circuit 30 which are real-time processing systems at the time of capture. Set. Thus, the BIU 29 is an interface related to control from the central processing unit 18, and the resolution conversion circuit 32, codec 33, and media control circuit 35 do not require real-time processing. Thereby, the central processing unit 18 gives priority to the processing of the display control circuit 36 and the camera signal processing circuit 30 in preference to the occupation of the bus BUS related to the command from the central processing unit 18.

  On the other hand, when the capture process is completed, the central processing unit 18 sets the second priority in the arbitration circuit. Thereby, the central processing unit 18 improves the user interface by giving priority to the control from the central processing unit 18. However, when the priority order of the central processing unit 18 is set high in this way and the access frequency from the central processing unit 18 is too high by the central processing unit 18 to be used, the resolution conversion circuit 32, the codec 33, the media The processing in the control circuit 35 takes time. However, in this case, if the BIU 29 is set as a reference circuit and a bandwidth limit value is set, even if the access frequency of the central processing unit is too high, the bus right monopoly by the central processing unit 18 can be prevented. Thus, the image data can be appropriately processed in the resolution conversion circuit 32, the codec 33, and the media control circuit 35.

  The central processing unit 18 sets the second priority in the arbitration circuit when displaying the imaging result recorded on the recording medium 21 on the monitor 20. As a result, in this case as well, the bus right is efficiently and appropriately assigned to each circuit block. Thus, when displaying the imaging result recorded on the recording medium 21 on the monitor 20, since the real-time access is only the display control circuit 36, the display control circuit 36 is thus given high priority. The imaging result can be displayed without a sense of incongruity.

  In the electronic still camera 11, when monitoring the imaging result recorded on the recording medium 21, the image data output from the resolution conversion circuit 32 is generated after the codec 33 generates image data for black padding and records it in the memory 27. Data is recorded in the memory 27 by overwriting, whereby one or a plurality of imaging results are displayed on the monitor 20 with a black background. Even in this case, the electronic still camera 11 temporarily sets the priority of the codec 33 to a high level so that the image data related to the black padding process is continuously recorded in the memory 27, and then the priority of the BIU 29. Is set to a high value so that the bus rights are acquired from each other and the imaging results are efficiently displayed on the monitor, thereby preventing the so-called monopolization of the bus rights.

  In the electronic still camera 11, the camera signal processing circuit 30 constitutes an image data processing circuit that processes image data based on the imaging result and outputs the processed image data to the bus. The codec 33 and the media control circuit 35 are connected to the bus. Thus, the image data is compressed and recorded on a recording medium, and the recording / reproducing circuit is configured to decompress the image data recorded on the recording medium and output the data to a bus. The display control circuit 36 is connected to a bus to form a display circuit that acquires image data and displays it on a monitor. The central processing unit 18 and the BIU 29 are connected to the bus to connect the image data processing circuit, recording / reproduction. A control circuit that outputs a command for controlling the operation of the circuit and the display circuit to the bus is configured, and the memory 27 is connected to the bus via the memory control circuit 31 to configure a storage circuit that temporarily holds image data. Has been made.

  According to the configuration of FIG. 10, on the assumption that the access right is set according to the priority order with respect to the bus access request, the access request from the reference circuit and the access request from the processing circuit having a lower priority than the reference circuit If there is a conflict, the access right should be set so that the number of times the access right is set to the processing circuit with a lower priority with respect to the number of times the access right is set to the reference circuit becomes a value corresponding to the bandwidth limit value in advance. Thus, the access right to the bus can be set appropriately and efficiently in a plurality of processing circuits.

  In addition, by switching the priority by switching the operation mode other than capture, capture, image data can be processed without breaking the bus in real-time access, and by setting bandwidth control even in non-real-time access, The buses can be used efficiently with each other.

  In the second embodiment, the case where the reference circuit is set to the BIU and only the priority is switched has been described. However, the present invention is not limited to this, and the reference circuit and the priority circuit are switched in addition to the priority by switching the operation mode. Alternatively, the setting of the band limit value may be switched. If a practically sufficient characteristic can be secured, only the setting of the reference circuit and / or the band limit value may be switched.

  In the first embodiment described above, the case where the priority order, the reference circuit, and the band limit value are switched by the host controller according to the overall processing has been described. However, the present invention is not limited to this, and the processing circuit is an arithmetic processing means. In this case, the setting of the priority order, the reference circuit and / or the band limit value may be switched according to the processing program related to the execution of each arithmetic processing means.

  In the above-described embodiments, the case where one reference circuit and one band limit value are set has been described. However, the present invention is not limited to this, and a single reference circuit and one or more band limit values are set. The band allocated by the band limit value may be further allocated by the remaining band limit value.

  In the above-described embodiments, the case where the present invention is applied to arbitration of memory access requests and bus access requests has been described. However, the present invention is not limited to this. For example, the present invention is not limited to data transfer means. The present invention can be widely applied when various access requests are arbitrated, such as when arbitrating access requests.

  The present invention can be applied to, for example, an electronic still camera.

It is a flowchart which shows the process sequence of the arbitration circuit which concerns on Example 1 of this invention. It is a block diagram which shows the arbitration system which concerns on Example 1 of this invention. It is a chart which shows the priority in the arbitration system of FIG. FIG. 3 is a transition diagram showing transition of a count value in an access right setting counter in the arbitration system of FIG. 2. It is a flowchart which shows the continuation of FIG. 6 is a time chart for explaining arbitration of access requests between a reference circuit and a lower processing circuit. It is a time chart with which it uses for description when holding the count value in an access right setting counter. It is a time chart with which explanation of access request concerning cash back is explained. It is a time chart with which it uses for description when the access request from a high-order processing circuit competes. 6 is a block diagram illustrating an electronic still camera according to Embodiment 2. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Arbitration system, 2, 27 ... Memory, 3 ... Control circuit, 5 ... Arbitration circuit, 11 ... Electronic still camera, 12 ... Image sensor, 18 ... Central processing unit, 19 ... DSP, DESCRIPTION OF SYMBOLS 20 ... Monitor, 20 ... Camera signal processing circuit, 31 ... Memory control circuit, 32 ... Resolution conversion circuit, 33 ... Codec, 35 ... Media control circuit, 36 ... Display control circuit, c1-cn + 2 ... ... MPU

Claims (15)

In an arbitration device that selectively sets access rights for access requests from a plurality of processing circuits and arbitrates access requests from the plurality of processing circuits,
A priority indicating a processing order for an access request from the plurality of processing circuits;
A reference circuit that identifies one of the plurality of processing circuits;
With respect to the number of times of setting the access right to the reference circuit, a band limit value indicating the number of times of setting the access right to the processing circuit having a lower priority than the reference circuit is set,
A counter that is set to an initial value by setting an access right to the reference circuit and counts an access right to the processing circuit having a lower priority than the reference circuit;
If the access request does not conflict, set an access right to the processing circuit related to the access request,
When the access request competes, an access right is set for the access request from the plurality of processing circuits according to the priority order.
When the access request of the reference circuit and the access request of the processing circuit having a lower priority than the reference circuit compete, the comparison between the count value of the counter and the band limit value causes the reference circuit and the reference circuit to An access right is selectively set to the processing circuit having a low priority,
When the access request of the reference circuit and the access request of the processing circuit having a lower priority than the reference circuit compete with each other, the processing having a lower priority than the reference circuit with respect to the set number of access rights to the reference circuit The arbitration device, wherein the number of times of setting the access right to the circuit is set to a value according to the bandwidth limit value. The arbitration device according to claim 1, wherein the access right to the processing circuit having a lower priority than the reference circuit is set according to the priority. The access right is set to the processing circuit having a higher priority than the reference circuit according to the priority when there is an access request from the processing circuit having a higher priority than the reference circuit. The arbitration device described in 1. In the counter, the count of the setting of the access right to the processing circuit having a lower priority than the reference circuit,
In the reference circuit, the processing circuit having a lower priority than the reference circuit, the number of times of setting the access right to the processing circuit having a lower priority than the reference circuit when access requests compete.
If the access request from the reference circuit or the processing circuit having a lower priority than the reference circuit does not compete, the access right is set to the reference circuit related to the access request or the processing circuit having a lower priority than the reference circuit. The arbitrating device according to claim 1, wherein The access request is an access request to a memory;
The reference circuit is
In the case of a write-back cache system, an access right is set for an access request related to a write-back to the memory, and an access request related to a subsequent read request from the memory is prioritized over the reference circuit. If there is a conflict with an access request from the processing circuit having a low
The arbitration device according to claim 1, wherein an access right is preferentially set for a read request of the reference circuit. When an access request related to a read request from the memory following an access request related to a write back to the memory conflicts with an access request from the processing circuit having a higher priority than the reference circuit,
The arbitration device according to claim 5, wherein an access right is preferentially set for an access request from the processing circuit having a high priority. The arbitration device according to claim 1, wherein the access request is an access request to a bus. The arbitration device according to claim 1, wherein the priority order, the reference circuit, and / or the setting of the band limit value are updated at a predetermined timing. The arbitration device according to claim 1, wherein the priority order, the reference circuit, and / or the band limit value are switched by switching an operation mode. Each of the plurality of processing circuits is an arithmetic processing circuit that executes a predetermined processing program,
2. The arbitration device according to claim 1, wherein the priority order, the reference circuit, and / or the band limit value are switched by switching the processing program in any of the plurality of processing circuits. In an arbitration method for selectively setting access rights for access requests from a plurality of processing circuits and arbitrating access requests from the plurality of processing circuits,
A priority indicating a processing order for an access request from the plurality of processing circuits;
A reference circuit that identifies one of the plurality of processing circuits;
With respect to the number of times of setting access rights to the reference circuit, a band limit value indicating the number of times of setting access rights to the processing circuit having a lower priority than the reference circuit is set,
A step of counting to set an initial value by setting an access right to the reference circuit and to count an access right to the processing circuit having a lower priority than the reference circuit;
When the access request does not conflict, an access right is set for the processing circuit related to the access request. When the access request conflicts, an access right for the access request from the plurality of processing circuits according to the priority order. And an access right setting step for setting
The access right setting step includes:
When the access request of the reference circuit and the access request of the processing circuit having a lower priority than the reference circuit compete, the reference circuit and the reference are compared by comparing the count value in the counting step with the band limit value. Selectively setting an access right to the processing circuit having a lower priority than the circuit;
When the access request of the reference circuit and the access request of the processing circuit having a lower priority than the reference circuit compete with each other, the processing having a lower priority than the reference circuit with respect to the set number of access rights to the reference circuit An arbitration method, wherein the number of times of setting access rights to the circuit is set to a value corresponding to the bandwidth limit value. In an arbitration method program for arbitrating access requests from a plurality of processing circuits by selectively setting an access right for access requests from a plurality of processing circuits by execution by an arithmetic processing unit,
The reference for the priority indicating the order of processing for the access requests from the plurality of processing circuits, the reference circuit for specifying one of the plurality of processing circuits, and the number of times of setting the access right to the reference circuit and setting the band limiting value indicating the set number of access to the lower priority the processing circuit from the circuit,
A step of counting to set an initial value by setting an access right to the reference circuit and to count an access right to the processing circuit having a lower priority than the reference circuit;
When the access request does not conflict, an access right is set for the processing circuit related to the access request. When the access request conflicts, an access right for the access request from the plurality of processing circuits according to the priority order. A program for causing a computer to execute an access right setting step for setting
The access right setting step includes:
When the access request of the reference circuit and the access request of the processing circuit having a lower priority than the reference circuit compete, the reference circuit and the reference are compared by comparing the count value in the counting step with the band limit value. Selectively setting an access right to the processing circuit having a lower priority than the circuit;
When the access request of the reference circuit and the access request of the processing circuit having a lower priority than the reference circuit compete with each other, the processing having a lower priority than the reference circuit with respect to the set number of access rights to the reference circuit A program for an arbitration method, wherein the number of times of setting access right to a circuit is set to a value corresponding to the bandwidth limit value. In a recording medium recording a program of an arbitration method for selectively arbitrating access requests from a plurality of processing circuits by selectively setting access rights with respect to access requests from the plurality of processing circuits by execution by an arithmetic processing means ,
The mediation method program is:
The reference for the priority indicating the order of processing for the access requests from the plurality of processing circuits, the reference circuit for specifying one of the plurality of processing circuits, and the number of times of setting the access right to the reference circuit and setting the band limiting value indicating the set number of access to the lower priority the processing circuit from the circuit,
A step of counting to set an initial value by setting an access right to the reference circuit and to count an access right to the processing circuit having a lower priority than the reference circuit;
When the access request does not conflict, an access right is set for the processing circuit related to the access request. When the access request conflicts, an access right for the access request from the plurality of processing circuits according to the priority order. A computer-readable recording medium storing a program for causing a computer to execute an access right setting step for setting
The access right setting step includes:
When the access request of the reference circuit and the access request of the processing circuit having a lower priority than the reference circuit compete, the reference circuit and the reference are compared by comparing the count value in the counting step with the band limit value. Selectively setting an access right to the processing circuit having a lower priority than the circuit;
When the access request of the reference circuit and the access request of the processing circuit having a lower priority than the reference circuit compete with each other, the processing having a lower priority than the reference circuit with respect to the set number of access rights to the reference circuit A recording medium on which a program of an arbitration method is recorded, wherein the number of times of setting access right to a circuit is set to a value corresponding to the band limit value. In an electronic still camera that displays an imaging result on a monitor and records it on a recording medium, and displays the imaging result recorded on the recording medium on the monitor.
An image data processing circuit that processes image data based on the imaging result and outputs the processed image data to a bus;
A recording / reproducing circuit connected to the bus for compressing and recording the image data on the recording medium, decompressing the image data recorded on the recording medium and outputting the data to the bus;
A display circuit connected to the bus for acquiring the image data and displaying it on the monitor;
A control circuit which is connected to the bus and outputs a command for controlling the operation of the image data processing circuit, the recording / reproducing circuit, and the display circuit to the bus;
A storage circuit connected to the bus and temporarily holding the image data;
The image data processing circuit, the recording / reproducing circuit, the display circuit, and an arbitration circuit that arbitrates the bus access request by the control circuit,
The arbitration circuit is:
A priority indicating the order of processing for access requests from a plurality of circuits by the image data processing circuit, the recording / reproducing circuit, the display circuit, and the control circuit;
A reference circuit for identifying one of the plurality of circuits;
With respect to the number of times of setting access rights to the reference circuit, a band limit value indicating the number of times of setting access rights to a circuit having a lower priority than the reference circuit is set,
A counter that is set to an initial value by setting an access right to the reference circuit and counts an access right setting to a circuit having a lower priority than the reference circuit;
When the access request does not conflict, an access right is set for the circuit related to the access request. When the access request conflicts, an access right is set for the access request from the plurality of circuits according to the priority order. And
When the access request of the reference circuit and the access request of a circuit having a lower priority than the reference circuit compete, the priority order of the reference circuit and the reference circuit is compared by comparing the count value of the counter with the bandwidth limit value. Selectively set access rights to low-
Access to a circuit having a lower priority than the reference circuit with respect to the set number of access rights to the reference circuit when an access request of the reference circuit and an access request of a circuit having a lower priority than the reference circuit compete An electronic still camera, wherein the number of times of right setting is set to a value corresponding to the bandwidth limit value. 15. The electronic still camera according to claim 14, wherein the priority, the reference circuit, and / or the band limit value are switched by switching between an operation mode other than capture at the time of capture by the image data processing circuit. .

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