JP4633445B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which wiring is formed so as to overlap a semiconductor element.

The H bridge circuit is generally constituted by four output transistors. When such an H bridge circuit is integrated in a semiconductor integrated circuit, four output transistors are formed in the semiconductor substrate. Further, an insulating layer is provided on the output transistor, and an aluminum wiring layer is provided on the insulating layer. The pad electrode provided in the output transistor is connected to a predetermined signal such as a power supply potential or a ground potential. (For example, refer to Patent Document 1).
JP-A-5-235086

  An H bridge circuit including a set of four output transistors controls a single motor or detects a signal of a single frequency, and thus can be said to be a 1ch (channel) H bridge circuit. Further, when detecting signals having a plurality of frequencies, such as an in-vehicle smart keyless antenna, an H bridge circuit corresponding to a plurality of channels is required. In such a case, if an H bridge circuit corresponding to a plurality of channels is formed in one semiconductor integrated circuit, it is easy to mount the vehicle, which is preferable. However, simply providing an aluminum wiring layer for the output transistor formed on the semiconductor substrate increases the impedance, so that the specified specifications cannot be satisfied. As a result, the operation of the semiconductor integrated circuit is unstable. There is a possibility. Further, when the H bridge circuit is formed in one semiconductor integrated circuit, heat generated by the circuit is concentrated on a predetermined portion of the semiconductor integrated circuit, and the operation of the semiconductor integrated circuit becomes unstable. there is a possibility.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor integrated circuit that operates stably even when a plurality of output transistors are provided.

  In order to solve the above-described problems, a semiconductor integrated circuit according to an aspect of the present invention includes a plurality of output circuits that output a predetermined signal while being formed on a surface of a semiconductor substrate, and that are a plurality of power or driver circuits. Output circuit and a control circuit for controlling the output of signals from the plurality of output circuits. The plurality of output circuits are formed in the vicinity of two opposing sides of the sides constituting the semiconductor substrate and are formed in a substantially symmetrical arrangement, and the control circuit is opposed to the surface of the semiconductor substrate. It is formed so as to be positioned between a plurality of output circuits formed apart in the vicinity of the two sides.

“Substantially symmetric” includes line symmetry and point symmetry, and does not need to be strictly symmetric, but may be symmetric so that the corresponding portion can be understood.
According to this aspect, since the plurality of output circuits are arranged apart from each other in the vicinity of two opposite sides of the semiconductor substrate, heat is dispersed throughout the semiconductor substrate, and as a result, heat concentration in a part of the semiconductor substrate is reduced. Therefore, a semiconductor integrated circuit with stable operation can be provided.

  Each of the plurality of output circuits includes a plurality of transistors, and the semiconductor integrated circuit further includes a terminal common to the plurality of transistors among a plurality of types of terminals provided in each of the plurality of transistors. A first wiring layer to be connected; and a second wiring layer formed above the wiring for connecting at least one common terminal of the first wiring layers and connected to the first wiring layer. May be. In this case, since the first wiring layer and the second wiring layer are overlapped, the impedance can be reduced.

  You may further provide the pad connected with a 1st wiring layer and a 2nd wiring layer through a through hole. You may connect a wire so that a pad may go to the outer side of 2 sides which oppose. In this case, the difference in distance from the position where the wire is connected to each transistor is reduced, so that variation in impedance can be reduced.

  The plurality of output circuits may include a plurality of bridge circuits configured as a set of four transistors, and the plurality of bridge circuits may be arranged along two opposing sides. In this case, it can be applied to a bridge circuit. The second wiring layer may be a gold wiring.

  According to the present invention, it is possible to provide a semiconductor integrated circuit that operates stably even when a plurality of output transistors are provided.

  Before describing the present invention in detail, an outline will be described. The embodiments of the present invention relate to a semiconductor integrated circuit in which a plurality of H bridge circuits are mounted. When a plurality of H bridge circuits are integrated in a semiconductor integrated circuit, the operation of the semiconductor integrated circuit may become unstable due to heat concentration if the plurality of H bridges are locally concentrated. Further, when a plurality of H bridge circuits are integrated, only an aluminum wiring (hereinafter referred to as “aluminum wiring”) has a large impedance and cannot satisfy a condition defined in a predetermined specification. Further, when the length of the bonding wire is limited, the power supply voltage and the ground potential cannot be directly applied to the transistor. Therefore, it is necessary to provide wiring for applying in the semiconductor integrated circuit. At that time, if the number of H-bridge circuits is increased, there are short-wiring transistors and long-wiring transistors, and impedance variation occurs between them. Further, in the H-bridge circuit, the impedance of the entire circuit is affected by a transistor having a large impedance, so that the impedance of the entire circuit also increases in the above-described case. Furthermore, if the number of H bridge circuits increases, the layout of the semiconductor integrated circuit becomes complicated.

  Here, a control circuit for controlling the H-bridge circuit is arranged in the central portion of the semiconductor substrate, and both sides of the semiconductor substrate sandwiching the control circuit (hereinafter, one is referred to as a “first region” and the other is Are referred to as “second region”), and two H bridge circuits are provided to provide four H bridge circuits. That is, if the semiconductor substrate has a rectangular shape, an H bridge circuit is provided in each of the first region and the second region located at both ends of the long side of the rectangle. As a result, the four H bridge circuits are distributed and arranged over the entire semiconductor substrate, so that heat concentration can be reduced. Further, since the number of H bridge circuits per region is reduced, the difference in the length of the wiring with respect to the transistor is reduced, and the variation in impedance is reduced. In addition, the layout is simplified. Furthermore, in the semiconductor integrated circuit according to the present embodiment, the gold wiring is provided in another layer so as to at least partially overlap the aluminum wiring. Since the impedance of gold is smaller than that of aluminum, the overall impedance can be reduced while suppressing an increase in the wiring layer. In addition, since the layout of the gold wiring can be designed to be different from the layout of the aluminum wiring, here, the layout of the gold wiring is designed so as to shorten the length of the bonding wire.

  FIGS. 1A to 1C are plan views in the course of the manufacturing process of the semiconductor integrated circuit 200 according to the embodiment of the present invention. Specifically, the semiconductor integrated circuit 200 has a plurality of wiring layers, and FIGS. 1A to 1C show plan views of the respective wiring layers. These are arranged so as to be upward in the order of FIG. 1A to FIG. 1C, but such a vertical relationship is for convenience, for example, even if the vertical relationship is reversed. Good. FIG. 1A shows a plan view of the first aluminum wiring layer. The semiconductor integrated circuit 200 includes transistors Tr1 to Tr16, a control circuit 10, and pads 20 to 102. In each drawing, fine wiring for forming the transistors Tr1 to Tr16 is omitted, and only the region is shown.

  The transistors Tr1 to Tr4, the transistors Tr5 to Tr8, the transistors Tr9 to Tr12, and the transistors Tr13 to Tr16 constitute a set of four transistors to form an H-bridge circuit. That is, the semiconductor integrated circuit 200 includes four H bridge circuits, which are referred to as a first H bridge circuit, a second H bridge circuit, a third H bridge circuit, and a fourth H bridge circuit in order from the front. The transistors Tr1 to Tr16 are formed on the surface of a semiconductor substrate (not shown). The transistors Tr1 to Tr16 output a predetermined signal. Further, the control circuit 10 controls output of signals from the transistors Tr1 to Tr16.

  Here, the semiconductor integrated circuit 200 has a rectangular shape as shown in the figure, but two short sides orthogonal to both ends of the long side, that is, the ends of the first H bridge circuit and the second H bridge circuit are in contact with each other. The side along which the side along the edge of the third H bridge circuit and the end of the fourth H bridge circuit are in contact with each other is defined as a first side and a second side, respectively. Thus, the first side and the second side are in a positional relationship facing each other. Further, the region where the first H bridge circuit and the second H bridge circuit are installed on the first side is the first region, and the third H bridge circuit and the fourth H bridge circuit are installed on the second side. The region is the second region. Also, the H bridge circuits or transistors installed in the first region and the second region may be the first group or the second group, respectively. Further, pads 20 to 102 are provided in the transistors Tr1 to Tr16. The pads 20 to 102 are assigned to predetermined signals, details of which will be described later. In this way, the first group and the second group are formed apart from each other in the vicinity of two opposing sides of the sides that should constitute the semiconductor substrate, and are formed in a substantially symmetrical arrangement with the control circuit 10 as the center. Has been. Here, the “substantially target” corresponds to a configuration in which the transistors Tr1 to Tr16 are arranged as targets but the pads 20 to 102 are not arranged as targets.

  FIG. 2 is an equivalent circuit diagram of the semiconductor integrated circuit 200. The figure corresponds to one H-bridge circuit, and here, the first H-bridge circuit will be described. As described above, the first H bridge circuit includes the transistors Tr1 to Tr4. These correspond to PMOS (Positive Metal Oxide Semiconductor) or NMOS (Negative Metal Oxide Semiconductor) transistors. The pad 52 is connected to the power supply voltage, the pad 20 is connected to the ground potential, and the pad 52 and the pad 20 are connected to the source terminal or the drain terminal of the transistor Tr1 to the transistor Tr4. Further, the gate terminals of the transistors Tr1 to Tr4 are connected to the control circuit 10. The control circuit 10 controls the operation of the transistors Tr1 to Tr4.

  Of the source terminals or drain terminals of the transistors Tr1 to Tr4, the terminals not connected to the pad 52 and the pad 20 are connected to the pad 32 or the pad 34. The pad 32 and the pad 34 are connected to the motor M as shown in FIG. The first H bridge circuit functions as a motor driver for the motor M. Therefore, it can be said that the transistors Tr1 to Tr4 are driver transistors. In such a configuration, the impedance of the signal line including the motor M between the pad 32 and the pad 34 is affected by a second aluminum wiring layer and a gold wiring layer described later.

  Returning to FIG. As described with reference to FIG. 2, the control circuit 10 applies a predetermined voltage to the gate terminals of the transistors Tr1 to Tr16. The control circuit 10 is formed so as to be located in the central portion of the semiconductor integrated circuit 200, that is, between the first region and the second region. This is equivalent to being provided between the first group and the second group.

  FIG. 1B is a plan view of the second aluminum wiring layer formed above the first aluminum wiring layer. The aluminum wiring 110 to the aluminum wiring 132 are formed so as to overlap the transistors Tr1 to Tr16. In the first region, the aluminum wiring 110 is overlaid on the transistors Tr1, Tr3, Tr5, Tr7, and the terminal of each transistor is connected to GND or VDD. The aluminum wiring 112 is overlaid on the transistors Tr1 and Tr2, the aluminum wiring 114 is overlaid on the transistors Tr3 and Tr4, the aluminum wiring 116 is overlaid on the transistors Tr5 and Tr6, and the aluminum wiring 118 is Overlaid on the transistors Tr7 and Tr8, the output terminal of each transistor is connected. The aluminum wiring 120 is overlaid on the transistors Tr2, Tr4, Tr6, Tr8 and connected to the VDD or GND of each transistor. Further, each of the transistors Tr1 to Tr8 is provided with a plurality of types of terminals, and the aluminum wiring 110 to the aluminum wiring 120 are mutually connected among the plurality of types of terminals provided to the transistors Tr1 to Tr8. Connect the common terminals. Here, the plural types indicate, for example, a drain, a gate, and a source. At that time, the second aluminum wiring layer is connected to the first aluminum wiring layer through a through hole (not shown). The aluminum wiring 110 to the aluminum wiring 120 are also connected to the pads. As a result, the pad corresponds to one of a plurality of types of terminals provided in the transistor. The through hole is also called a via hole (through hole). Here, for clarity of explanation, the power supply pad in FIG. 1A is projected onto the second aluminum wiring layer and displayed, and the corresponding reference numerals are given. This also applies to FIG. 1C described later.

  In the second region, the aluminum wiring 122 is overlaid on the transistors Tr9, Tr11, Tr13, Tr15, and is connected to the VDD or GND of each transistor. The aluminum wiring 124 is overlaid on the transistors Tr9 and Tr10, the aluminum wiring 126 is overlaid on the transistors Tr11 and Tr12, the aluminum wiring 128 is overlaid on the transistors Tr13 and Tr14, and the aluminum wiring 130 is Overlaid on the transistors Tr15 and Tr16, the output terminal of each transistor is connected. The aluminum wiring 132 is overlaid on the transistors Tr10, Tr12, Tr14, Tr16, and the terminal of each transistor is connected to GND or VDD. Further, each of the transistors Tr9 to Tr16 is provided with a plurality of types of terminals, and the aluminum wiring 122 to the aluminum wiring 132 are mutually connected among the plurality of types of terminals provided to the transistors Tr9 to Tr16. Connect the common terminals. The aluminum wiring 122 to the aluminum wiring 132 are also connected to the pads. As a result, the pad corresponds to one of a plurality of types of terminals provided in the transistor.

  In the first region, the aluminum wiring 110 connects the pads 20, 22, 24, 26, 28, and 30, the aluminum wiring 112 connects the pads 32 and 34, and the aluminum wiring 114 connects the pads 36 and 38. The aluminum wiring 116 connects the pads 44 and 46, the aluminum wiring 118 connects the pads 48 and 50, and the aluminum wiring 120 connects the pads 52, 54, 56, 58 and 60. Here, each pad connected to the aluminum wiring 110 is assigned to the ground potential, and each power supply pad connected from the aluminum wiring 112 to the aluminum wiring 118 is assigned to the input / output signal. Each power supply pad connected to the aluminum wiring 120 is assigned to a power supply voltage. The input / output signal corresponds to a signal input / output to / from the motor M in FIG.

  In the second region, the aluminum wiring 122 connects the pads 62, 64, 66, 68, 70, the aluminum wiring 124 connects the pads 72, 74, the aluminum wiring 126 connects the pads 76, 78, The aluminum wiring 128 connects the pads 84 and 86, the aluminum wiring 130 connects the pads 88 and 90, and the aluminum wiring 132 connects the pads 92, 94, 96, 98, 100, and 102. Here, each pad connected to the aluminum wiring 122 is assigned to a power supply voltage, and each power supply pad connected from the aluminum wiring 124 to the aluminum wiring 130 is assigned to an input / output signal. Each power supply pad connected to the aluminum wiring 132 is assigned to the ground potential. Note that aluminum wiring is not provided on the pads 40, 42, 80, 82.

  FIG. 1C shows a plan view of the gold wiring layer provided above the insulating layer on the second aluminum wiring layer after the semiconductor integrated circuit 200 is formed. The gold wiring layer has a characteristic that the impedance is lower than that of the second aluminum wiring layer. Here, FIG. 1C shows a power supply pad connected to the bonding wire on the upper surface of the gold wiring layer among the power supply pads shown in FIGS. 1A and 1B. The gold wiring layer and the second aluminum wiring layer are connected by a through hole (not shown). In the first region, the gold wiring 140 is configured to perform a bonding wire with the pad 24 and the pad 26. The gold wiring 142 is configured to perform a bonding wire by the pad 40 and the pad 42.

  In the second region, the gold wiring 144 is configured to perform a bonding wire by the pad 80 and the pad 82. The gold wiring 146 is configured to perform a bonding wire with the pad 94 and the pad 96. As described above, the pads 20 to 102 provided in the transistors Tr1 to Tr16 in FIG. 1A are formed of the second aluminum wiring layer and the gold as shown in FIGS. 1B and 1C, respectively. A bonding wire is formed through the wiring layer. In addition, since the transistors Tr1 to Tr16 are arranged separately in the first region and the second region, the position where the wire is bonded in each region, for example, the distance from the predetermined pad to the transistor is the first region and the second region. It becomes smaller than the distance when it is not divided into regions. That is, when the first region and the second region are not divided, the second region is disposed so as to be in contact with the first region, so that the distance from the predetermined pad to the transistor becomes long as described above. As a result, according to the present embodiment, the variation becomes small with respect to the impedance as described in FIG.

  Note that the pad 24, the pad 26, and the pad 32 to the pad 50 provided in the transistors Tr1 to Tr8 belonging to the first region are bonded by wires wired from the outside on the first side side, and belong to the second region. Pad 72 to pad 90, pad 94, and pad 96 provided in transistors Tr9 to Tr16 are bonded by wires wired from the outside on the second side. That is, the pads connect the wires so as to go to the outside of the two opposing sides. Here, the gold wiring 140 and the gold wiring 146 are assigned to the ground potential, and the gold wiring 142 and the gold wiring 144 are assigned to the power supply potential. Further, the pads 32 and the like assigned to the input / output signals are not connected by the gold wiring.

  Of the plurality of wirings provided in the first region of the first aluminum wiring layer, the aluminum wiring 120 formed at a position far from the first side is connected to the corresponding gold wiring 142 in the gold wiring layer. However, at least a part of the gold wiring 142 is formed closer to the first side than the aluminum wiring 120. That is, as shown in FIG. 1C, the gold wiring 142 has a shape such that portions corresponding to the pad 38 and the pad 40 approach the first side. In FIG. 1A, the distance from the pad 52 to the pad 60 (hereinafter referred to as “first pad group”) having the same distance from the first side is different from that of the first pad group. The gold wiring 142 is formed so that the pads 40 and 42 (hereinafter referred to as “second pad group”) having the same distance from the first side are connected to each other in the gold wiring layer. As described above, in the first region, the bonding wire is wired from the first side, but the length of the bonding wire can be shortened by the gold wiring 142 approaching the first side.

  Of the plurality of wirings provided in the second region of the first aluminum wiring layer, the aluminum wiring 122 formed at a position far from the second side is connected to the corresponding gold wiring 144 in the gold wiring layer. However, at least a part of the gold wiring 144 is formed closer to the second side than the aluminum wiring 122. That is, as shown in FIG. 1C, the gold wiring 144 has a shape such that the portions corresponding to the pads 80 and 82 approach the second side. The pads 62 to 70 correspond to the first pad group described above, and the pads 80 and 82 correspond to the second pad group described above.

  FIG. 3 is a schematic cross-sectional view of the semiconductor integrated circuit 200. FIG. 3 is a cross-sectional view taken along line A-A ′ in FIGS. A drain D and a source S are formed on the semiconductor substrate 170. The drain D is connected to the first aluminum wiring layer 172 through the through hole 174. In FIG. 1A, the first aluminum wiring layer 172 is shown as a transistor Tr13. A gate G is formed between the semiconductor substrate 170 and the first aluminum wiring layer 172. An insulating layer 160 is formed above the first aluminum wiring layer 172. The aluminum wiring 128 is formed above the first aluminum wiring layer 172 and connected to the source S. Further thereon, a gold wiring 144 is formed, and the gold wiring 144 is connected to the first aluminum wiring layer 172 via the pad 80 and the through hole 174. A pad 80 is provided on the first aluminum wiring layer 172, and a wire is bonded to the pad 80. Note that the through hole 174 may be omitted.

  FIG. 4 is a plan view of a part of the output transistor of the semiconductor integrated circuit 200. FIG. 4 is a plan view of the periphery of the portion indicated by A-A ′ in FIGS. 1A to 1C, and shows the gate G, drain D, and source S of FIG. 3 on one plane. From the top to the bottom of the figure, drains D and sources S are alternately formed. A gate G is disposed between the drain D and the source S. Although only a part is shown here, the illustrated configuration is repeated. Each source S is connected to the second aluminum wiring layer through a through hole.

  FIGS. 5A and 5B are diagrams showing wire bonding in the semiconductor integrated circuit 200. FIG. FIG. 5A shows a semiconductor integrated circuit 200 in the present embodiment. Here, for the sake of clarity, the transistors in the first region are collectively referred to as a transistor Tr20, and the transistors in the second region are collectively referred to as a transistor Tr22. A pad 50 is disposed on the transistor Tr20, and a pad 52 is disposed on the transistor Tr22. Here, FIG. 5 (a) shows the first aluminum wiring layer among the first aluminum wiring layer to the gold wiring layer shown in FIGS. 1 (a) to 1 (c), and further, wire bonding. A pad is also shown to explain the effect of the above. In FIG. 5A, among the sides constituting the semiconductor integrated circuit 200, wires 154 and the like bonded in the direction of the first side and the second side facing each other are wired. That is, for the transistor Tr20, a wire 154 is wired in the direction of the first side, and for the transistor Tr22, a wire is wired in the direction of the second side.

  FIG. 5B shows a case where a plurality of transistors are continuously arranged unlike the present embodiment. In FIG. 5B, the same reference numerals as those in FIG. 5A are used for the components corresponding to those in FIG. As illustrated, the transistor Tr20 and the transistor Tr22 are arranged in contact with each other. Therefore, both the transistor Tr20 and the transistor Tr22 are wired in the direction of the first side. As described above, according to FIG. 5A, the wiring of the wire is simplified as compared with FIG. 5B. Moreover, the length of the wire can be made uniform. Further, since the transistor Tr20 and the transistor Tr22 are separated, heat concentration can be reduced.

  The correspondence between the configuration of the present invention and the example is illustrated. The “plurality of output circuits” corresponds to an H bridge circuit. This corresponds to, for example, the transistors Tr1 to Tr4. The “control circuit” corresponds to the control circuit 10. The “plurality of transistors” corresponds to the transistors Tr1 to Tr16. The “first wiring layer” corresponds to the aluminum wiring 110 to the aluminum wiring 132. The “second wiring layer” corresponds to the gold wiring 140 to the gold wiring 146. The “pad” corresponds to the pad 20 to the pad 102.

According to the embodiment of the present invention, since the plurality of H bridge circuits are arranged apart from each other in the vicinity of the first side and the second side, heat is dispersed throughout the semiconductor substrate. Further, as a result of the heat being dispersed, heat concentration in a part of the semiconductor substrate can be reduced, so that a semiconductor integrated circuit with stable operation can be provided.
Further, since the second aluminum wiring layer and the gold wiring layer are overlapped, the impedance can be reduced. In addition, since the difference in distance from the position where the wire is connected to each transistor is reduced, variation in impedance can be reduced. In addition, since the plurality of transistors are arranged separately in the first region and the second region, the number of transistors arranged in one region is reduced, and the plurality of transistors can be easily laid out on the semiconductor substrate. Further, in the configuration of the H-bridge circuit, the overall impedance is affected by a portion having a large impedance. Therefore, the overall impedance can be reduced by reducing the impedance variation.

  In addition, the amount of current can be increased. Further, since the position where the wire is bonded is formed such that the distance from the first side or the second side of the gold wiring layer is reduced, the length of the bonding wire can be shortened. This also facilitates layout. Further, it can be applied to an H bridge circuit. In addition, since a semiconductor integrated circuit including a plurality of H bridge circuits can be realized, for example, it is possible to reduce the number of steps when mounting the semiconductor integrated circuit. Further, since the number of steps is reduced, the cost can be reduced.

  In the above, this invention was demonstrated based on the Example. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to the combination of each component and each processing process, and such modifications are also within the scope of the present invention. .

  In the embodiment of the present invention, the transistors Tr1 to Tr16 have been described as including a plurality of H-bridge circuits configured by combining four transistors. However, the present invention is not limited to this. For example, the transistors Tr1 to Tr16 may not form an H-bridge circuit. According to this modification, the present invention can be applied to various circuit configurations. That is, it is only necessary to install a plurality of high current output transistors.

  In the embodiment of the present invention, the number of transistors is 16. However, the present invention is not limited thereto, and may be the number of other transistors such as 16 or more. In the embodiment of the present invention, the second aluminum wiring layer and the gold wiring layer are provided on the first aluminum wiring layer. However, the present invention is not limited to this. For example, copper or the like may be used. According to this modification, the present invention can be applied to various circuit configurations. That is, it is only necessary to install a plurality of high current output transistors.

  In the embodiment of the present invention, the motor M is connected to the H bridge circuit. However, the present invention is not limited to this. For example, the inductance L and the capacitor C may be connected to the H bridge circuit. In this case, the H bridge circuit has a function of forming a resonance circuit by the inductance L and the capacitor C and extracting a signal having a resonance frequency specified by the inductance L and the capacitor C. Further, by changing the values of the inductance L and the capacitor C respectively connected from the first H bridge circuit to the fourth H bridge circuit, the resonance frequencies of the first H bridge circuit to the fourth H bridge circuit can be set to different values. According to this modification, the present invention can be applied to various circuits. In other words, it is sufficient that a plurality of H bridges are formed in the semiconductor integrated circuit 200.

The features of the invention described in the embodiments may be defined by the following items.
(Item 1)
A plurality of semiconductor elements;
A semiconductor substrate on which a plurality of semiconductor elements are installed, and
When a plurality of semiconductor elements are divided into two groups, the semiconductor elements belonging to the first group are placed on the first side forming the semiconductor substrate, while the semiconductor elements belonging to the second group Are installed on the second side facing the first side,
The semiconductor element belonging to the first group is provided with a pad to which a wire wired from the outside on the first side can be connected, and the semiconductor element belonging to the second group has an external on the second side. A semiconductor integrated circuit, characterized in that a pad is provided to which a wire wired from can be connected.

(Item 2)
A first wiring layer overlaid on a plurality of semiconductor elements;
A second wiring layer having an impedance smaller than that of the first wiring layer and superimposed on the first wiring layer;
Item 2. The item according to Item 1, wherein the pads provided in each of the plurality of semiconductor elements are configured such that wires wired from the outside can be connected via the first wiring layer and the second wiring layer. Semiconductor integrated circuit.

(Item 3)
Pads provided on each of the plurality of semiconductor elements are assigned to predetermined signals,
In the first wiring layer, a plurality of wirings are formed so as to connect pads assigned to the same signal among pads provided in a plurality of semiconductor elements,
Among the plurality of wirings, the first group first wiring arranged for the first group and formed at a position far from the first side corresponds to the second wiring layer. Connected to the second far wiring for the first group, and at least a part of the second far wiring for the first group is formed closer to the first side than the first far wiring for the first group,
Among the plurality of wirings, the second group first far-away wiring that is provided for the second group and is formed at a position far from the second side corresponds to the second wiring layer. Connected to the second far wiring for the second group, and at least a part of the second far wiring for the second group is formed to be closer to the second side than the first far wiring for the second group. Item 3. The semiconductor integrated circuit according to Item 2.

(Item 4)
A semiconductor substrate;
A plurality of semiconductor elements installed on the surface of the semiconductor substrate;
A first wiring layer overlaid on a plurality of semiconductor elements;
A second wiring layer having a smaller impedance than the first wiring layer and overlaid on the first wiring layer;
A semiconductor integrated circuit characterized in that a plurality of semiconductor elements are provided with pads to which wires wired from the outside can be connected via a first wiring layer and a second wiring layer.

According to item 1, since a plurality of semiconductor elements are divided into the first group and the second group, the number of semiconductor elements per group is reduced, and the semiconductor elements can be easily laid out. In addition, since the difference in distance from the position where the wire is connected to each semiconductor element is reduced, variation in impedance can be reduced.
According to item 2, since the first wiring layer and the second wiring layer having a smaller impedance than the first wiring layer are overlapped, the impedance can be reduced. “Overlapped” includes not only the case where the wiring layers are completely overlapped but also the case where a part thereof is overlapped.

According to item 3, since the distance from the first side or the second side can be reduced, the length of the wire can be reduced.
According to item 4, since the first wiring layer and the second wiring layer having a smaller impedance than the first wiring layer are overlapped, the impedance can be reduced.

  The correspondence between the configuration of the present invention and the example is illustrated. The “plurality of semiconductor elements” corresponds to the transistors Tr1 to Tr16. “Semiconductor substrate” corresponds to the semiconductor substrate 170. The “first wiring layer” corresponds to the aluminum wiring 110 to the aluminum wiring 132. The “second wiring layer” corresponds to the gold wiring 140 to the gold wiring 146. The “pad” corresponds to the pad 20 to the pad 102. Further, the pad 32 to the pad 38, the pad 44 to the pad 50, the pad 72 to the pad 78, and the pad 84 to the pad 90 may be included. The “first group” corresponds to the first region and the transistors disposed in the first region, the “first far wiring for the first group” corresponds to the aluminum wiring 120, and the “second for the first group” The “distant wiring” corresponds to the gold wiring 142, the “second group” is the transistor disposed in the second region and the second region, and the “first remote wiring for the second group” is the aluminum wiring 122. Correspondingly, the “second distant wiring for the second group” corresponds to the gold wiring 144.

1A to 1C are plan views of a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of the semiconductor integrated circuit of FIGS. FIG. 2 is a cross-sectional view of the semiconductor integrated circuit of FIGS. FIG. 2 is a plan view of a part of the semiconductor integrated circuit of FIGS. FIGS. 5A to 5B are diagrams showing wire bonding in the semiconductor integrated circuit of FIGS. 1A to 1C.

Explanation of symbols

  Tr1-16 transistor, 10 control circuit, 20-102 pad, 110-132 aluminum wiring, 140-146 gold wiring, 160 insulating layer, 170 semiconductor substrate, 200 semiconductor integrated circuit.

Claims (4)

A plurality of output circuits for outputting predetermined signals while being formed on the surface of the semiconductor substrate, and a plurality of output circuits for power or driver;
A control circuit for controlling the output of signals by the plurality of output circuits,
The plurality of output circuits are formed apart from each other in the vicinity of two opposing sides of the sides constituting the semiconductor substrate, and are formed in a substantially symmetrical arrangement.
The control circuit is formed on the surface of the semiconductor substrate so as to be positioned between a plurality of output circuits formed in the vicinity of two opposing sides.
Each of the plurality of output circuits includes a plurality of transistors,
The semiconductor integrated circuit further includes: a first wiring layer that connects terminals common to each other among the plurality of types of terminals provided in each of the plurality of transistors;
A semiconductor integrated circuit comprising: a second wiring layer formed above a wiring connecting at least one common terminal of the first wiring layers and connected to the first wiring layer. circuit. A pad connected to the first wiring layer and the second wiring layer via a through hole;
The semiconductor integrated circuit according to claim 1 , wherein the pad connects a wire so as to go to the outside of the two opposing sides. 2. The plurality of output circuits include a plurality of bridge circuits configured by a set of four transistors, and the plurality of bridge circuits are arranged along the two opposing sides. Or the semiconductor integrated circuit according to 2; The second wiring layer, a semiconductor integrated circuit according to claim 1 or 2, characterized in that a gold wire.

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