JP4625030B2 - Communications system - Google Patents

Description

  The present invention relates to a mobile communication system. In particular, the present invention relates to a system for generating a reference frequency signal in a mobile communication system.

  In a GSM type mobile communication system, transmission and reception are required in four common frequency bands such as 850 MHz, 900 MHz, 1800 MHz, and 1900 MHz. That is, frequency generation sources in the 900 MHz band and the 1800 MHz band are required.

  Typically, current frequency sources use three different voltage controlled oscillators (VCOs) that operate at approximately 1 GHz, 2 GHz, and 4 GHz, respectively. Each VCO used for transmission operates at the same frequency required as a transmission channel. Also, the VCO used for reception operates at twice the received frequency, which uses a well-known digital divider circuit to provide in-phase and quadrature local oscillator (LO) signals. This is so that it can be used.

  However, when implemented on an application specific integrated circuit (ASIC), the silicon area of the IC used by the 1 GHz and 2 GHz VCOs greatly increases the cost of the ASIC. Further, the feedback to these VCOs is also a big problem. This is because the VCO operates at the same frequency as the transmitter signal.

  One well-known prior art generates all the required frequencies by using a single VCO coupled to a frequency divider circuit. For example, the VCO operates in the 4 GHz band and provides a lower frequency, so the frequency is divided by 2 or 4 as necessary. However, this is merely an extension of the required VCO adjustment range and is not a direct technique for enabling use within an ASIC.

  The present invention can be implemented, for example, as a phase locked loop circuit in a radio frequency transmitter and receiver. The phase-locked loop circuit includes a first voltage controlled oscillator that operates to output a first reference frequency signal and a second voltage controlled oscillator that operates to output a second reference frequency signal. The phase-locked loop circuit is connected to receive the first and second reference frequency signals, the first subset of the set of output reference frequency signals generated from the first reference frequency signal, and the second A set of switchable frequency dividers operable to output a set of output reference frequency signals having a second subset of output reference frequency signals generated from the reference frequency signals. In addition, the phase locked loop circuit is connected to receive the external reference frequency signal and the feedback reference frequency signal and receives the received external frequency signal to maintain the desired first and second reference frequency signals. VCO control means operative to provide a control voltage to the first and second voltage controlled oscillators in accordance with the reference frequency signal and the feedback reference frequency signal. The first and second reference frequency signals are not equal to the frequency of the output reference frequency signal in the set of output reference frequency signals. A set of dividers selectively receives the first and second reference frequency signals and outputs a high-band output reference frequency signal for the transmitter; And a second divider for receiving a second reference frequency signal and outputting a low-band output reference frequency signal for the transmitter. And a set of frequency dividers for selectively receiving the first and second reference frequency signals and supplying the output reference frequency signal of the local oscillator for the receiver and the VCO control means. A third frequency divider for outputting the feedback signal.

  FIG. 1 is a diagram showing a first embodiment of the present invention. Here, provision of signals to a transmitter and a receiver suitable for use in a mobile station used in a mobile communication network will be described. The embodiment shown in FIG. 1 includes a phase locked loop (PLL) circuit. The PLL circuit includes a first voltage controlled oscillator (VCO A) 2 and a second voltage controlled oscillator (VCO B) 4. The VCOs 2 and 4 output output signals to the adder 6. The adder 6 supplies a signal to the switchable frequency divider 8. As described in detail below, VCO2 and VCO4 are used independently. The output of the adder 6 is equivalent to the output from the selected VCO during operation. The switchable frequency divider 8 is operable to divide the signal from the adder 6 by 1 or 2. The output of the switchable frequency divider 8 is further supplied to the frequency divider 10. Divider 10 is operable to divide the signal by two. The output of the frequency divider 10 is supplied to the programmable frequency divider 12. Programmable divider 12 provides an output to phase detector 14 for comparison with reference frequency 20. The output of the phase detector 14 is supplied to the loop filter 16. The loop filter 16 supplies filter control signals to the first and second VCOs 2 and 4 in order. The PLL operates to stabilize the outputs of the VCOs 2 and 4 in a well-known manner. According to embodiments of the present invention, the VCO is operated at a frequency that is twice or four times the desired frequency. In addition, these frequencies are always divided into two or four divided by the frequency dividers 10 and 8. This means that the frequency provided to the input of the programmable divider 12 is operated at the frequency required for the VCO and is the same as the frequency when the dividers 8, 10 are not present. To do.

  Programmable divider 12 operates to fix the operating VCO at 2 or 4 times the required output frequency by Npd * Fref. Here, Npd indicates a coefficient of the programmatic frequency divider 12, and Fref indicates a reference frequency.

  A fixed and programmable divider provides a set of dividers. These dividers are used to adjust the output of the VCO. The coefficient (size) of the frequency divider can be fixed or variable (for example, 1/2 or 1/4). With appropriate changes, the VCO is frequency modulated. The variable coefficient is given by a variable signal or an appropriate combination of variable and fixed signals. For example, the coefficient may change around a fixed decimal point 0.1.

  The output of the second VCO 4 is also supplied to the frequency divider 26. Divider 26 is operated to divide the output of the VCO by four. The output of the frequency divider is supplied via a buffer 28 to a power amplifier (not shown) of the mobile station. This provides the signal frequency of the low band transmitter. Similarly, the output of the adder 6 is supplied to the frequency divider 22. The frequency divider 22 operates to divide the added signal by two. The frequency-divided signal is supplied to the power amplifier of the mobile station via the buffer 24. This provides the signal frequency of the high band transmitter.

  According to the embodiment shown in FIG. 1, the VCOs 2, 4 are both adjusted to output an output signal of about 4 GHz. Thereby, the signal frequency to the high band transmitter is 2 GHz, and the signal frequency to the low band transmitter is 1 GHz.

  The circuit also operates to provide a signal from a local oscillator (LO) to a mobile station receiver (not shown). This is achieved by supplying the output of the switchable divider 8 to a quadrature splitter and divider 30. The quadrature splitter and divider 30 is operated to generate a signal that is half the frequency of the input signal. This signal also includes in-phase and quadrature signals for supply to the receiver.

  Illustratively, divider 30 includes a unidirectional output connection. This output connection carries an LO signal of either about 1 GHz or about 2 GHz. This is feasible if the receiver mixer has sufficient bandwidth to handle both of these bands. If the receiver is not as described above, each receiver corresponding to each band is used. In this case, the LO signal is divided and transmitted to each receiver as necessary.

  It is a feature of the present invention that the characteristics of the frequency modulation measured at the input to the programmable divider and at the outputs of the circuits 24, 28 are determined by Npd. This is done in exactly the same way as when the VCO is operating at the required final frequency and the fixed dividers 10, 8, 22, 26 are omitted. It will be clear that the frequency modulation measured at the output of the VCO is not accurate. This is because the FM modulation peak deviation is twice or four times the required value. An advantage with embodiments of the present invention is that the modulation signal at the input of the programmatic divider is defined by various values of Npd. Npd accurately outputs similar results to be equal to the final frequency in the VCO prior art.

  The allocation of the operating band between VCO A and VCO B can be arranged to minimize the range adjustment required for each VCO. FIG. 4 is a diagram showing VCO A2 used for the reference frequency in a 3600 Mhz to 4000 Mhz system and VCO B used for a reference frequency in a 3300 Mhz to 3650 Mhz system.

  The loop operation of the PLL will be affected by a fixed divider to reduce the open loop gain by divide by 2 or divide by 4. This is usually not important, but the tuning sensitivity of a 4 GHz VCO is typically about twice for a 2 GHz VCO or about 4 times for a 1 GHz VCO, respectively. Thus, the total loop gain according to embodiments of the present invention does not vary significantly.

  Thus, embodiments of the present invention implement two VCOs 2, 4 that cover the entire adjustment range required. The programmable frequency divider of the phase-locked loop circuit will show a signal with the same frequency as that required (ie, this frequency is related to the nominal center frequency of the GSM channel). This allows the circuit to operate as if it were operating at the required frequency, instead of operating at a frequency twice or four times the VCO.

  FIG. 2 shows an alternative circuit arrangement. In this circuit arrangement, a frequency divider 7 that performs frequency division by 2 and a frequency divider 8 that can be switched by the gates 9 and 21 are realized. Each gate operates to select an input signal to be transferred to another circuit. The signal transmission path from the VCOs 2 and 4 is determined by switching the gates 6, 9 and 21. This is because an accurate VCO is used for the transmission frequency or reception frequency when in use.

  The circuit arrangement shown in FIG. 2 is effective with respect to arrangement and size.

  FIG. 3 is a diagram illustrating a third embodiment. Here, the PLL operates at a frequency substantially output from the VCO, that is, 4 GHz. In the case of a fractional-N PLL, this can increase the resolution of the signal after frequency division by setting the coefficients to 2 and 4.

  By using the present invention, the adjustment range of the VCO becomes relatively small and can be easily implemented. Thereby, the cost can be sufficiently reduced by using a small-sized 4 GHz circuit as compared with a 1 GHz VCO. Furthermore, the frequency of the VCO is different from the final output frequency. This is effective in reducing the coupling effect that occurs between the output signal and the VCO. The present invention is also effective in maintaining control compatibility between different configurations.

It is a figure which shows the 1st Embodiment of this invention. It is a figure which shows the 2nd Embodiment of this invention. It is a figure which shows the 3rd Embodiment of this invention. FIG. 6 is a diagram illustrating a range of reference frequencies provided by a VCO used in an embodiment of the present invention.

Claims (7)

A phase locked loop circuit in a radio frequency transmitter and receiver comprising:
A first voltage controlled oscillator that operates to output a first reference frequency signal;
A second voltage controlled oscillator that operates to output a second reference frequency signal;
A first subset of output reference frequency signals connected to receive the first and second reference frequency signals and generated from the first reference frequency signals, and generated from the second reference frequency signals A set of dividers operable to output a set of output reference frequency signals having a second subset of output reference frequency signals;
The external reference frequency signal and the feedback reference frequency signal received and connected to receive the external reference frequency signal and the feedback reference frequency signal and to maintain the desired first and second reference frequency signals. VCO control means operative to supply a control voltage to the first and second voltage controlled oscillators according to
The first and second reference frequency signals are:
Unlike the frequency of the output reference frequency signal in the set of output reference frequency signals,
The set of dividers is:
Receiving the criteria frequency signal, and a first frequency divider for outputting the output reference frequency signal for high band transmitter,
A second divider for receiving the second reference frequency signal and outputting a low-band output reference frequency signal for the transmitter;
It includes a switchable divider for selectively receiving the first and second reference frequency signals, and a third frequency divider for outputting the output reference frequency signal at a local oscillator for receiver ,
A phase-locked loop including the switchable frequency divider and a fourth frequency divider for outputting a feedback signal to be supplied to the VCO control means circuit. The set of output reference frequency signals is:
The phase-locked loop circuit according to claim 1, comprising a frequency corresponding to a frequency required by a standard in mobile communication of GSM850, GSM900, DCS1800, and PCS1900. The phase-locked loop circuit according to claim 1 or 2, wherein the first and second voltage controlled oscillators are selectively controlled by a phase-locked loop. 4. The phase according to claim 1, wherein the first frequency divider is connected to receive one of the first and second reference frequency signals. 5. Synchronous loop circuit. 4. The phase-locked loop circuit according to claim 1, wherein the first frequency divider is connected to receive the second reference frequency signal. 5. The set of dividers is:
By operating to change the coefficient values of the frequency dividing circuit, a phase synchronization according to any one of claims 1 to 5, characterized in that causing frequency modulation to the first and second voltage controlled oscillator Loop circuit. The phase locked loop circuit according to claim 6 , wherein the coefficient value includes a fixed portion and a portion that changes with time.

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