JP2001332971A - Pll frequency synthesizer - Google Patents

Pll frequency synthesizer

Info

Publication number
JP2001332971A
JP2001332971A JP2000147697A JP2000147697A JP2001332971A JP 2001332971 A JP2001332971 A JP 2001332971A JP 2000147697 A JP2000147697 A JP 2000147697A JP 2000147697 A JP2000147697 A JP 2000147697A JP 2001332971 A JP2001332971 A JP 2001332971A
Authority
JP
Japan
Prior art keywords
voltage
pll
charge pump
controlled oscillator
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000147697A
Other languages
Japanese (ja)
Inventor
Tsukasa Fukui
司 福井
Noriji Ezaki
則治 江崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000147697A priority Critical patent/JP2001332971A/en
Publication of JP2001332971A publication Critical patent/JP2001332971A/en
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a miniaturized and inexpensive switching PLL frequency synthesizer by reducing the number of parts to have a single low-pass filter(LPF) shared among plural voltage controlled oscillators (VCO). SOLUTION: The LPF 3 is connected to a charge pump output terminal 2 of a PLL-IC 1 and a control voltage terminal 5a of a VCO 4a, having an operation control terminal 6a and a control voltage terminal 5b of a VCO 4b having an operation control terminal 6b are connected in parallel to the LPF 3. By selectively switching the output current of a charge pump circuit 7 built in the PLL-IC 1 and the operation control terminals 6a and 6b of the VCO 4a and 4b, the PLL frequency synthesizer having different frequency bands can be provided.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、自動車電話や携帯
電話等の移動通信装置に使用されるPLL周波数シンセ
サイザに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL frequency synthesizer used for a mobile communication device such as a mobile phone or a mobile phone.

【0002】[0002]

【従来の技術】以下、従来の切り換え式PLL周波数シ
ンセサイザについて説明する。従来の切り換え式PLL
周波数シンセサイザは図2に示すようになっていた。即
ち、チャージポンプ電流が制御できないPLL−IC
(このIC内には分周器と比較回路とチャージポンプが
集積されている)11のチャージポンプ出力端子12に
切り替えスイッチ14を設け、この切り替えスイッチ1
4の出力は低域通過フィルタ13aと13bに接続さ
れ、低域通過フィルタ13aと13bの出力は、それぞ
れ動作制御端子6aを有する電圧制御発振器4aの制御
電圧端子5aと、動作制御端子6bを有する電圧制御発
振器4bの制御電圧端子5bに並列接続された構成とな
っていた。そして、切り替えスイッチ14の切り替えと
動作制御端子6a,6bへの動作電圧の切り替えにより
各々異なる発振周波数を出力していた。
2. Description of the Related Art A conventional switched PLL frequency synthesizer will be described below. Conventional switchable PLL
The frequency synthesizer was as shown in FIG. That is, a PLL-IC whose charge pump current cannot be controlled.
(A frequency divider, a comparison circuit, and a charge pump are integrated in this IC.) 11 A charge pump output terminal 12 is provided with a switch 14, and this switch 1
The output of 4 is connected to low-pass filters 13a and 13b, and the outputs of low-pass filters 13a and 13b have a control voltage terminal 5a of a voltage controlled oscillator 4a having an operation control terminal 6a and an operation control terminal 6b, respectively. The configuration is such that the voltage control oscillator 4b is connected in parallel to the control voltage terminal 5b. Then, different oscillation frequencies are output by switching the changeover switch 14 and switching the operation voltage to the operation control terminals 6a and 6b.

【0003】[0003]

【発明が解決しようとする課題】しかしながらこのよう
な従来の構成では、PLLループを切り替える切り替え
スイッチ14と、通過特性の異なる低域通過フィルタ1
3a,13bが2組必要となり、部品点数が多くなるこ
とによって形状が大きくなるという課題があった。
However, in such a conventional configuration, the switch 14 for switching the PLL loop and the low-pass filter 1 having different pass characteristics are used.
There is a problem in that two sets of 3a and 13b are required, and the shape becomes large as the number of parts increases.

【0004】本発明は、このような問題点を解決するも
ので、部品点数が少なく、小型のPLL周波数シンセサ
イザを提供することを目的としたものである。
An object of the present invention is to solve such a problem and to provide a small PLL frequency synthesizer with a small number of components.

【0005】[0005]

【課題を解決するための手段】この目的を達成するため
に本発明は、複数個が並列に接続されるとともに動作制
御端子に選択的に電圧が供給される電圧供給手段を備え
た電圧制御発振器と、これら複数個の電圧制御発振器の
出力が一方の入力に供給されるとともに他方の入力には
基準発振器の出力が接続された比較回路と、この比較回
路の出力に接続されるとともに出力電流の制御手段を有
するチャージポンプ回路と、このチャージポンプ回路の
出力と前記電圧制御発振器の制御電圧端子との間に接続
された低域通過フィルタとで形成され、選択された前記
電圧制御発振器によるPLLループの特性値を前記チャ
ージポンプ回路の出力電流で制御している。
SUMMARY OF THE INVENTION In order to achieve this object, the present invention provides a voltage controlled oscillator comprising a plurality of voltage supply means connected in parallel and selectively supplying a voltage to an operation control terminal. And a comparison circuit in which the outputs of the plurality of voltage controlled oscillators are supplied to one input and the output of the reference oscillator is connected to the other input, and the output current of the comparison circuit is connected to the output of the comparison circuit. A PLL loop formed by a selected voltage controlled oscillator formed by a charge pump circuit having control means and a low pass filter connected between an output of the charge pump circuit and a control voltage terminal of the voltage controlled oscillator. Are controlled by the output current of the charge pump circuit.

【0006】これにより、PLL周波数シンセサイザの
小型化を図ることができる。
Thus, the size of the PLL frequency synthesizer can be reduced.

【0007】[0007]

【発明の実施の形態】本発明の請求項1に記載の発明
は、複数個が並列に接続されるとともに動作制御端子に
選択的に電圧が供給される電圧供給手段を備えた電圧制
御発振器と、これら複数個の電圧制御発振器の出力が一
方の入力に供給されるとともに他方の入力には基準発振
器の出力が接続された比較回路と、この比較回路の出力
に接続されるとともに出力電流の制御手段を有するチャ
ージポンプ回路と、このチャージポンプ回路の出力と前
記電圧制御発振器の制御電圧端子との間に接続された低
域通過フィルタとで形成され、選択された前記電圧制御
発振器によるPLLループの特性値を前記チャージポン
プ回路の出力電流で制御するPLL周波数シンセサイザ
であり、チャージポンプ回路の出力電流でPLLループ
の特性値を制御することにより、低域通過フィルタは共
用が可能となり小型化を実現することができる。また、
フィルタを共用化することにより部品点数が少なくなり
製造コストが安くなる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a voltage controlled oscillator provided with voltage supply means connected in parallel and having a voltage selectively supplied to an operation control terminal. A comparison circuit in which the outputs of the plurality of voltage controlled oscillators are supplied to one input and the output of the reference oscillator is connected to the other input, and the output of the comparison circuit is connected to the output of the comparison circuit to control the output current. And a low-pass filter connected between the output of the charge pump circuit and the control voltage terminal of the voltage controlled oscillator, the PLL loop being formed by the selected voltage controlled oscillator. A PLL frequency synthesizer for controlling a characteristic value by an output current of the charge pump circuit, wherein a characteristic value of a PLL loop is controlled by an output current of the charge pump circuit. And, the low-pass filter can be miniaturized enables shared. Also,
By sharing the filter, the number of parts is reduced and the manufacturing cost is reduced.

【0008】本発明の請求項2に記載の発明は比較回路
の入力に挿入される分周器の分周数と、チャージポンプ
電流と、電圧制御発振器の制御電圧感度を[数2]の関
係にすることで複数組のPLLループにおけるカットオ
フ周波数とノイズ除去特性を略等しくした請求項1に記
載のPLL周波数シンセサイザであり、電圧制御発振器
を切り替えたときの特性が略等しくなるので、このPL
L周波数シンセサイザを組み込んで機器の切り替えによ
る性能の均一化が図れる。
According to a second aspect of the present invention, the relationship between the number of divisions of the frequency divider inserted into the input of the comparison circuit, the charge pump current, and the control voltage sensitivity of the voltage controlled oscillator is expressed by the following equation. 2. The PLL frequency synthesizer according to claim 1, wherein the cutoff frequency and the noise removal characteristic in a plurality of sets of PLL loops are made substantially equal, and the characteristics when the voltage controlled oscillator is switched become substantially equal.
By incorporating an L frequency synthesizer, performance can be made uniform by switching devices.

【0009】[0009]

【数2】 (Equation 2)

【0010】(実施の形態)以下、図面に従って本発明
を説明する。図1は本発明の一実施の形態におけるPL
L周波数シンセサイザのブロック構成を示すものであ
る。本実施の形態では、PLL−IC1に内蔵されたチ
ャージポンプ回路7の出力端子2に低域通過フィルタ3
が接続され、前記低域通過フィルタ3の出力が動作制御
端子6aを有する電圧制御発振器4aの制御電圧端子5
aに接続されるとともに、動作制御端子6bを有する電
圧制御発振器4bの制御電圧端子5bとに並列接続され
た構成となっている。PLL−IC1に内蔵されたチャ
ージポンプ回路7の出力電流と電圧制御発振器4aと電
圧制御発振器4bの動作制御端子6a,6bを選択的に
切り替えることで異なる周波数帯域を有したPLL周波
数シンセサイザを構成する。
(Embodiments) The present invention will be described below with reference to the drawings. FIG. 1 shows a PL according to an embodiment of the present invention.
2 shows a block configuration of an L frequency synthesizer. In the present embodiment, the low-pass filter 3 is connected to the output terminal 2 of the charge pump circuit 7 built in the PLL-IC 1.
And the output of the low-pass filter 3 is connected to a control voltage terminal 5 of a voltage controlled oscillator 4a having an operation control terminal 6a.
a and connected in parallel to the control voltage terminal 5b of the voltage controlled oscillator 4b having the operation control terminal 6b. By selectively switching the output current of the charge pump circuit 7 incorporated in the PLL-IC 1 and the operation control terminals 6a and 6b of the voltage controlled oscillator 4a and the voltage controlled oscillator 4b, a PLL frequency synthesizer having different frequency bands is configured. .

【0011】以上のような実施の形態によれば、異なる
周波数帯域や制御感度を持つ電圧制御発振器4a,4b
を使用した場合でも、チャージポンプ回路7のチャージ
ポンプ制御端子8による電流の制御によりPLLループ
におけるカットオフ周波数、ノイズ除去特性の切り替え
が可能なので、従来のように切り替えスイッチ14を用
いず、低域通過フィルタ3を共用したPLL周波数シン
セサイザが構成できる。
According to the above-described embodiment, the voltage controlled oscillators 4a and 4b having different frequency bands and control sensitivities.
Is used, the cutoff frequency and the noise removal characteristic in the PLL loop can be switched by controlling the current by the charge pump control terminal 8 of the charge pump circuit 7. A PLL frequency synthesizer sharing the pass filter 3 can be configured.

【0012】さらに、チャージポンプ電流と、電圧制御
発振器4a,4bの制御電圧感度と、PLL−IC1の
分周数を[数3]の関係にすることで2組のPLLルー
プにおけるカットオフ周波数、ノイズ除去特性を同等に
することが可能であり、周波数帯域や電圧制御感度の異
なる電圧制御発振器を用いた場合でも同等のロックアッ
プ時間とC/N特性が得られる。
Further, by setting the charge pump current, the control voltage sensitivity of the voltage controlled oscillators 4a and 4b, and the frequency division number of the PLL-IC1 to [Equation 3], the cutoff frequency in the two sets of PLL loops is reduced. The noise removal characteristics can be made equal, and the same lock-up time and C / N characteristics can be obtained even when voltage controlled oscillators having different frequency bands and voltage control sensitivities are used.

【0013】[0013]

【数3】 (Equation 3)

【0014】[0014]

【発明の効果】以上のように本発明によれば、PLL−
ICのチャージポンプ回路により電流を制御することで
カットオフ周波数、ノイズ除去特性が可変であることに
より、性能を劣化させることなく使用部品点数を削減す
ることができ、小型で製造コストの安いPLL周波数シ
ンセサイザを実現することができる。
As described above, according to the present invention, PLL-
The cut-off frequency and noise elimination characteristics are variable by controlling the current by the charge pump circuit of the IC, so the number of parts used can be reduced without deteriorating the performance. A synthesizer can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態によるPLL周波数シン
セサイザのブロック図
FIG. 1 is a block diagram of a PLL frequency synthesizer according to an embodiment of the present invention.

【図2】従来のPLL周波数シンセサイザのブロック図FIG. 2 is a block diagram of a conventional PLL frequency synthesizer.

【符号の説明】[Explanation of symbols]

1 PLL−IC 2 チャージポンプ出力端子 3 低域通過フィルタ 4a 電圧制御発振器 4b 電圧制御発振器 5a 制御電圧端子 5b 制御電圧端子 6a 動作制御端子 6b 動作制御端子 7 チャージポンプ回路 8 チャージポンプ制御端子 Reference Signs List 1 PLL-IC 2 Charge pump output terminal 3 Low pass filter 4a Voltage controlled oscillator 4b Voltage controlled oscillator 5a Control voltage terminal 5b Control voltage terminal 6a Operation control terminal 6b Operation control terminal 7 Charge pump circuit 8 Charge pump control terminal

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5J106 AA04 BB01 CC20 CC24 CC38 CC41 CC52 DD32 GG15 HH03 KK38 KK39 PP03 PP05 QQ12 RR17  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 BB01 CC20 CC24 CC38 CC41 CC52 DD32 GG15 HH03 KK38 KK39 PP03 PP05 QQ12 RR17

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 複数個が並列に接続されるとともに動作
制御端子に選択的に電圧が供給される電圧供給手段を備
えた電圧制御発振器と、これら複数個の電圧制御発振器
の出力が一方の入力に供給されるとともに他方の入力に
は基準発振器の出力が接続された比較回路と、この比較
回路の出力に接続されるとともに出力電流の制御手段を
有するチャージポンプ回路と、このチャージポンプ回路
の出力と前記電圧制御発振器の制御電圧端子との間に接
続された低域通過フィルタとで形成され、選択された前
記電圧制御発振器によるPLLループの特性値を前記チ
ャージポンプ回路の出力電流で制御するPLL周波数シ
ンセサイザ。
1. A voltage-controlled oscillator comprising a plurality of voltage-controlled oscillators connected in parallel and selectively supplied with a voltage to an operation control terminal; A comparison circuit connected to the output of the reference oscillator at the other input, a charge pump circuit connected to the output of the comparison circuit and having output current control means, and an output of the charge pump circuit. And a low-pass filter connected between the voltage-controlled oscillator and a control voltage terminal of the voltage-controlled oscillator, wherein the PLL controls the characteristic value of the PLL loop by the selected voltage-controlled oscillator with the output current of the charge pump circuit. Frequency synthesizer.
【請求項2】 比較回路の入力に挿入される分周器の分
周数と、チャージポンプ電流と、電圧制御発振器の制御
電圧感度を[数1]の関係にすることで複数組のPLL
ループにおけるカットオフ周波数と、ノイズ除去特性を
略等しくした請求項1に記載のPLL周波数シンセサイ
ザ。 【数1】
2. A plurality of sets of PLLs by setting the division number of a frequency divider inserted into the input of the comparison circuit, the charge pump current, and the control voltage sensitivity of the voltage controlled oscillator to [Equation 1].
2. The PLL frequency synthesizer according to claim 1, wherein a cutoff frequency in the loop is substantially equal to a noise removal characteristic. (Equation 1)
JP2000147697A 2000-05-19 2000-05-19 Pll frequency synthesizer Pending JP2001332971A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000147697A JP2001332971A (en) 2000-05-19 2000-05-19 Pll frequency synthesizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000147697A JP2001332971A (en) 2000-05-19 2000-05-19 Pll frequency synthesizer

Publications (1)

Publication Number Publication Date
JP2001332971A true JP2001332971A (en) 2001-11-30

Family

ID=18653845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000147697A Pending JP2001332971A (en) 2000-05-19 2000-05-19 Pll frequency synthesizer

Country Status (1)

Country Link
JP (1) JP2001332971A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006295399A (en) * 2005-04-07 2006-10-26 Kyocera Corp Wireless device
JP2007538418A (en) * 2004-01-21 2007-12-27 テレフオンアクチーボラゲット エル エム エリクソン(パブル) Communications system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007538418A (en) * 2004-01-21 2007-12-27 テレフオンアクチーボラゲット エル エム エリクソン(パブル) Communications system
JP2006295399A (en) * 2005-04-07 2006-10-26 Kyocera Corp Wireless device

Similar Documents

Publication Publication Date Title
US6538521B2 (en) Voltage controlled oscillator
JP2875472B2 (en) PLL synthesizer and control method thereof
JPH10303747A (en) Pll frequency synthesizer for plural frequency bands
JPS61157028A (en) Frequency synthesizer
AU2002257363A1 (en) Tunable voltage controlled oscillator circuit having aided acquisition and methods for operating the same
JP2001332971A (en) Pll frequency synthesizer
EP1227592A2 (en) Frequency synthesizer and method of generating frequency-divided signal
JP2005109608A (en) Pll frequency synthesizer
TW200401512A (en) Receiver
KR100248505B1 (en) Fast synchronizing phase locked loop circuit
JPH0758637A (en) Frequency synthesizer
JP2003500969A (en) Multi-frequency low power oscillator for telecommunications IC
JP3556917B2 (en) Frequency synthesizer
JP2639289B2 (en) Injection-locked doubler
JP2004312588A (en) Crystal oscillator switching type pll oscillation circuit
JP2003509942A (en) Integrated VCO switch
KR20020084776A (en) Voltage controlled oscillator for multi-band
JPH0818448A (en) Control circuit for phase locked loop system frequency synthesizer
JPH0555911A (en) Pll oscillator
KR100387068B1 (en) Phase loked loop of mobile communication station
JP2000174555A (en) Voltage controlled oscillator of frequency band switching type
JPH02246423A (en) Phase locked loop frequency synthesizer
JPH0897712A (en) Pll circuit
JP2004364105A (en) Frequency divider and pll circuit
JP2000013225A (en) Oscillator