JP4617363B2 - Integrated circuit design equipment - Google Patents

Description

  The present invention relates to an integrated circuit design apparatus, and more particularly to an integrated circuit design apparatus for designing an integrated circuit.

  In recent years, with the diversification of products, integrated circuits are required to reduce design time. For this reason, in order to shorten the design time of the integrated circuit, it is necessary to greatly reduce the design process. Currently, integrated circuit design is performed by an integrated circuit design apparatus.

  Conventional integrated circuit design apparatuses mainly have a floor plan display function and a timing analysis function.

  The floor plan display function is a function for displaying mounting blocks as processing units and display units. The timing analysis function is a function that simply calculates the path delay based on the distance between the mounting blocks.

  In the conventional integrated circuit design apparatus, the above-described floor plan display function is used to design each mounting block, the delay between the arranged mounting blocks is analyzed using the timing analysis function, and the delay becomes a desired delay. The design for each mounting block was repeated.

  In the design by the hardware description language, the delay information used at the time of circuit synthesis, for example, the number of cell stages and the gate delay are used for timing analysis in the floor plan.

  However, in the conventional integrated circuit design, the mounting block is a processing unit. The scale of the logic circuit of the mounting block is several hundred thousand gates. For this reason, if the design is performed in units of mounting blocks, the accuracy of the analysis results by the timing analysis function is poor, and the error between the actual and timing analysis results is large, so the design must be reworked to achieve the target circuit speed. It occurred frequently. This hinders the reduction in the number of design steps for the integrated circuit.

  The present invention has been made in view of the above points, and an object thereof is to provide an integrated circuit design apparatus capable of efficiently designing an integrated circuit.

In the present invention, for each of a plurality of mounting blocks, which are areas obtained by dividing a chip area, a coat, which is a virtual arrangement area obtained by dividing a mounting block, is set by a designer using an input unit, and the integrated circuit is designed. In an integrated circuit design device, a block arrangement processing unit that arranges a coat set for each of a plurality of mounting blocks in a predetermined mounting block, and a functional block of a mounting block different from the predetermined mounting block is placed on the predetermined mounting block An area allocation processing unit to be arranged on the set court, a predetermined mounting block, and a block evaluation processing unit that evaluates the arrangement state of the lower layer court to be arranged lower than the predetermined mounting block. , block evaluation processing unit, with the arrangement of the coating of the functional blocks by the area allocation processing section, the area of the functional block of the lower layer Calculating the percentage of the area of the arranged coated to a constant mounting block, the ratio of the area between the calculated functional blocks and coating is for displaying a graphic for each coat.

The present invention also provides a design of an integrated circuit by setting a coat, which is a virtual placement area obtained by dividing a mounting block, from a designer for each of a plurality of mounting blocks, which are areas obtained by dividing a chip area. an integrated circuit design apparatus for performing a block arrangement processing unit to place the constant mounting block where the co-chromatography bets, a region assignment unit for place the function block copolymers over preparative predetermined mounting block and, A block evaluation processing unit that evaluates the arrangement state of the lower layer coats that are lower layers than the predetermined mounting block, and the area of the functional blocks in the lower layer is the predetermined mounting block An area ratio calculation unit that calculates the ratio of the area of the coat placed in the area, and whether or not the calculated area ratio of the functional block and the coat is within the reference range. And a delay calculation processing unit for calculating the delay in the path between the coats arranged lower layer if it is determined that.

Furthermore, the present invention provides a design of an integrated circuit by setting and arranging a coat, which is a virtual placement area obtained by dividing a mounting block, by a designer for each of a plurality of mounting blocks, which are areas obtained by dividing a chip area. an integrated circuit design apparatus for performing, in a mounting block of the integrated circuit, a block arrangement processing unit for setting a coating, a region assignment unit for place the function blocks on the court, function by area assignment processing unit Along with the arrangement of blocks on the court, there is a delay calculation processing section for calculating a delay in a path between functional blocks arranged on the court.

  As described above, according to the present invention, the ratio of the area of the block in the lower hierarchy to the area of the block in the predetermined hierarchy is calculated, and the area of the block in the lower hierarchy calculated as the area of the block arranged in the predetermined hierarchy is calculated. By displaying the proportions in the form of graphics, it is possible to intuitively understand the proportion of the calculated lower layer block area to the area of the blocks arranged in the predetermined layer, so that different layers can be designed efficiently. .

  FIG. 1 shows a block diagram of an embodiment of the present invention.

  The information processing apparatus 1 according to the present embodiment includes a data processing apparatus 11, an input apparatus 12, and an output apparatus 13. The data processing device 11 is composed of a computer system. The input device 12 includes a keyboard and a mouse, and inputs commands and data to the data processing device 11. The output device 13 is composed of a display or the like, and displays data contents processed by the data processing device 11.

  The data processing device 11 includes a hard disk drive 21, a RAM 22, a CPU 23, a replaceable storage device 24, and a communication device 25.

  An OS and an integrated circuit design program are installed in the hard disk drive 21. The OS and integrated circuit design program installed in the hard disk drive 21 are read into the RAM 22 and executed by the CPU 23. The RAM 22 is used as a working storage area for the CPU 23. The replaceable storage device 24 is a floppy (registered trademark) disk drive, a CD-ROM drive, a DVD-ROM drive, an MO drive, or the like. The integrated circuit design program may be provided by, for example, a floppy disk, a CD-ROM disk, a DVD-ROM disk, an MO disk, etc., and installed in the hard disk drive 21. The communication device 25 performs communication via a LAN, a telephone line, and the Internet. The integrated circuit design program may be provided via a LAN, a telephone line, or the Internet, and installed in the hard disk drive 21.

  FIG. 2 shows a functional block diagram of the integrated circuit design program. The integrated circuit design program 31 mainly includes a floor plan creation / display processing unit 41, a function block allocation processing unit 42, an area ratio calculation processing unit 43, a path delay calculation processing unit 44, a path list display processing unit 45, and a path route display. The processing unit 46 is configured.

  The integrated circuit design program 31 includes a floor plan creation / display processing unit 41, a function block allocation processing unit 42, an area ratio calculation processing unit 43, a path delay calculation processing unit 44, a path list display processing unit 45, and a path route display processing unit. 46 functions are used for mounting blocks, virtual placement areas (coats), functional blocks (cells), path placement, display, and editing.

  Here, the functional block, the mounting block, the virtual arrangement area, and the path are defined.

  FIG. 3 is a diagram for explaining a functional block (cell), a mounting block, a virtual arrangement area (coat), and a path. 3A is a diagram for defining functional blocks, FIG. 3B is a diagram for defining mounting blocks, FIG. 3C is a diagram for defining virtual placement areas, and FIG. ) Shows a diagram for defining a path.

  As shown in FIG. 3A, the cells B1 and B2 are defined as a group of logic circuit cells L for each function.

  Further, as shown in FIG. 3B, the mounting blocks P1 to P4 are defined as areas obtained by dividing the LSI chip T when mounting design is performed.

  As shown in FIG. 3C, the virtual arrangement areas (hereinafter referred to as coats) C1 to C3 are defined as areas obtained by further dividing the mounting block P2, for example.

  As shown in FIG. 3D, the paths M1 and M2 are defined as paths from the start point cell SS to the end point cell SE. FIG. 3D shows a path M1 passing through the start cell SS → cell S1 → cell S2 → cell S3 → end cell SE and a path passing through the start cell SS → cell S4 → cell S5 → cell S3 → end cell SE. M2 is present.

  Next, each function constituting the integrated circuit design program 31 will be described.

  The floor plan creation / display processing unit 41 performs processing for arranging the mounting blocks P1 to P4, and performs processing for displaying the arranged mounting blocks P1 to P4 and coats C1 to C3 on the output device 13. It is a function. The functional block allocation processing unit 22 performs processing for allocating the cells B1 and B2 to the mounting blocks P1 and P2 and the coats C1 to C3 arranged in the floor plan creation / display processing unit 21, and displays the processing on the output device 13. It is a function to perform.

  The area ratio calculation processing unit 23 has a function of performing processing for calculating the area ratio and processing for displaying the area ratio on the output device 13. The area ratio is a ratio of the area of the coats C1 to C3 or the cells B1 and B2 to the area of the mounting block P2 to which the coat or functional block belongs.

  The path delay calculation processing unit 24 calculates a path delay between functional blocks. The path list display processing unit 25 displays a path whose delay is equal to or greater than a reference value as a list. The path route display processing unit 46 is a function for performing processing for displaying on the screen the paths of the paths listed by the path list display processing unit 25.

  Next, a design method using the integrated circuit design program 31 will be described.

  FIG. 4 shows a flowchart of a design method according to an embodiment of the present invention.

  First, in step S1, floor plan data is created using the function of the floor plan creation / display processing unit 41 of the integrated circuit design program 31.

  FIG. 5 is a diagram for explaining the creation of the mounting block and the coat. 5A shows an example of definition of a coat in the LSI chip T, FIG. 5B shows an example of definition of a coat in a mounting block, and FIG. 5C shows an example of creation of a coat.

  In creating the floor plan in step S1, coats Ca, Cb, Cc1 to c3, Cd1, and Cd2 are set in the LSI chip T as shown in FIG. 5A, or the LSI is shown in FIG. 5B. By setting mounting blocks Pa to Pd in the chip T and further setting coats Ca, Cb, Cc1 to c3, Cd1 and Cd2 in the set mounting blocks Pa to Pd, a floor plan is created. .

  At this time, as shown in FIGS. 5A and 5B, a plurality of coats Ca1 to Ca25 having the same size can be set at the same time, or can be set at an arbitrary size such as coats Cc1 to Cc3. In addition, the shape of the coat is not limited to a rectangle, but a coat having an arbitrary shape such as coats Cd1 and Cd2 can be created.

  It is also possible to overlap a plurality of coats such as the coat Cc1 and the coat Cc2, or to overlap a part of the coats such as the coat Cc1 and the coat Cc3.

  In order to define a coat on the mounting blocks Pa to Pd or the LSI chip T as shown in FIG.

  The first coat creating method is a method of dividing the LSI chip T or the mounting block P into a plurality of coats by a specified numerical value.

  When creating a coat by the first coat creation method, the designer selects the mounting block Pa or LSI chip T to be divided. Next, a division number designation window is displayed by selecting the first coat creation method. For example, when the mounting block Pa is selected, a division number designation window w1 is displayed near the mounting block Pa as shown in FIG. The designer designates the number of divisions in the x and y directions in the division number designation window w1. In the floor plan creation / display processing function 41, the coats Ca1 to Ca25 are evenly set by the number of divisions designated for the selected LSI chip T or mounting block.

  The second method is a method of dividing the LSI chip T or the mounting block with a specified size.

  When creating a coat by the second method, the designer selects a mounting block Pa or LSI chip T to be divided. Next, the division size designation window is displayed by selecting the second coat creation method. For example, when the mounting block Pb is selected, as shown in FIG. 5C, a division size designation window w2 is displayed near the mounting block Pb. The designer designates the size Sx in the x direction and the size Sy in the y direction of one coat in the division size designation window w2. The floor plan creation / display processing function 41 sets the court of the selected size [(Sx) × (Sy)]. At this time, the size [(Sx) × (Sy)] coat Pb4, Pb5, Pb7, Pb8 is arranged from the lower left end, and the smaller part of the size [(Sx) × (Sy)] is applied to the remaining portion of the mounting block Pb. Pb1 to Pb3, Pb6, and Pb9 are set.

  The third coat setting method is to create an arbitrary rectangular coat using an input means such as a mouse. For example, as shown in the mounting block Pd in FIG. 5C, by dragging the pointer from the point e to the point f with the mouse, the coat Cd is set so that the point e and the point f become diagonal points.

  The fourth coat creation method is to create a coat having an arbitrary shape and size using an input means such as a mouse. For example, as shown in the mounting block Pc in FIG. 5C, the pointer is moved with the mouse, and the point g, the point h, the point i, the point j, the point k, and the point l are designated by clicking. A figure connecting the designated points g, h, i, j, k, and l with straight lines is set as a coat.

  As described above, the coat C is created in the LSI chip T or the mounting block P.

  Returning to FIG. 4, the description will be continued.

  When the mounting block P and / or coat is created on the LSI chip in step S1, the cell B is allocated to the mounting block P or coat C created in step S2. In the cell B, for example, by setting a function to each coat C, a function block for realizing a function corresponding to the set function is automatically set to the coat C.

  When a functional block or cell is assigned to the court C, the cell occupancy rate for each court C is calculated by the following formula in step S3, and a graph is displayed in the court for each court in step S4.

  Occupancy rate = (total functional block or cell area / coat area) × 100 (%) FIG. 6 shows a display example of the cell occupancy rate of the coat.

  In FIG. 6, the cell occupancy rates of the coats Ca, Cb, and Cc are displayed as pie charts Ga, Gb, and Gc for the coats Ca, Cb, and Cc. The coat Ca shows a case where the cell occupation ratio is 100% or less. In the pie chart Ga indicating the cell occupancy of the coat Ca, the cell occupancy is displayed in blue (satin), and the other portions are displayed in white.

  Further, the coat Cb shows a case where the cell occupation rate exceeds 100%. In the pie chart Gb indicating the cell occupancy rate of the coat Cb, the amount of the cell occupancy rate exceeding 100% is displayed in a color different from the blue color indicating the cell occupancy rate, for example, red (checkered).

  Furthermore, the coat Cc shows a case where the cell occupation rate exceeds 200%. The pie chart Gc indicating the cell occupancy of the coat Cc is all displayed in red (checkered). In addition, when it exceeds 200%, you may make it display with colors other than blue and red.

  By referring to the cell occupancy graphs Ga, Gb, Gc, the cell occupancy of each coat Ca, Cb, Cc can be recognized. Based on the displayed cell occupancy graphs Ga, Gb, Gc, in step S5, the designer determines whether the cell occupancy of each code Ca, Cb, Cc is within the standard, and the cell occupancy is within the standard. If not, the process returns to step S1 or step S2, and the arrangement and size of the mounting block P, the coat C, and the cell B are adjusted so as to become the reference cell occupation rate.

  Next, a method for adjusting the arrangement and size of the mounting block P, the coat C, and the cell B will be described.

  First, in order to perform adjustment accurately, the cell occupancy calculated by reflecting an area where cells cannot be arranged may be displayed in a graph on the court. At this time, a display indicating a region where cells cannot be arranged may be displayed in the coat C or may be hidden.

  FIG. 7 is a diagram showing a graph display reflecting an area in which cells cannot be arranged.

  FIG. 7A is a graph display of the cell occupancy calculated by reflecting the power supply wiring / placement prohibition area, and shows the display and the placement prohibition area showing the power supply wiring in a strip shape in the coats Ca, Cb, and Cc. Display is performed. Further, for example, when a switching button on the screen is clicked, as shown in FIG. 7B, the display indicating the power supply wiring / placement prohibited areas in the coats Ca, Cb, Cc is hidden.

  Note that display or non-display may be switched for each coat, and the display method is not limited to a belt shape.

  Further, the cell occupancy graph may be switched and displayed for each arbitrary hierarchical block.

  FIG. 8 is a diagram showing a switching display for each hierarchical block. FIG. 8A is a graph Ga, Gb, Gc showing the cell occupancy rates of courts Ca, Cb, Cc, which are lower-level blocks, and FIG. 8B is an LSI chip T, which is a higher-level block, or The example of a display containing the graph GT or GP which shows the cell occupation rate of the mounting block P is shown.

  Hierarchical block display switching is performed by clicking a hierarchy switching button or the like displayed on the screen. For example, when the cell occupancy graphs Ga, Gb, and Gc are displayed for each of the coats Ca, Cb, and Cc in the LSI chip T or the mounting block P as shown in FIG. Then, as shown in FIG. 8B, a cell occupancy graph GT or GP in the entire LSI chip T or mounting block P is displayed.

  In addition, editing that creates a mounting block P by combining a plurality of coats C is also possible.

  FIG. 9 is a diagram for explaining an operation when a mounting block P is created by collecting a plurality of coats. FIG. 9A shows a state before grouping, and FIG. 9B shows a state after grouping.

  As shown in FIG. 9A, a plurality of coats including coats Ca, Cb, and Cc are set in the LSI chip T. The designer first selects the coats Ca, Cb, and Cc that are to be combined into one mounting block. When the coats Ca, Cb, and Cc to be combined are selected, the floor plan creation / display processing unit 41 creates a mounting coat P that combines the coats Ca, Cb, and Cc as shown in FIG. 9B. To do.

  Further, in order to facilitate editing work, information regarding each court may be displayed.

  FIG. 10 is a diagram showing a screen display example of court information. FIG. 10A shows a display screen of the mounting block P and the coats Ca, Cb, and Cc, and FIGS. 10B and 10C show screens that display information on the coat Ca.

  When the pointer is moved to the court Ca on the screen displaying the three courts Ca, Cb, Cc defined in the mounting block P shown in FIG. 10A, information on the court Ca shown in FIG. Is displayed.

  The information on the court Ca is composed of higher-level mounting block name information D1, court area information D2, cell occupancy information D3, and functional block and cell name information D4 allocated to the court. The details of the coat Ca can be known by viewing this screen.

  Note that the screen shown in FIG. 10B is a case where the pointer is positioned on the court Ca in the screen shown in FIG. 10A. If the pointer is moved as it is, the screen is erased. When various edits and evaluations of the court are performed, the information D1 to D4 in the information screen can be used to recognize the court situation, so that the display may be retained. At this time, by pressing a key on the keyboard that has been registered in advance, for example, the “Z” key, the information of the coat Ca is continuously displayed on the information screen even if the pointer moves. At this time, the information screen is displayed as shown in FIG. A LOCK display DSP1 is displayed on the information screen shown in FIG. The designer is notified that the data on the screen is held by the LOCK display DSP1. In order to delete the information screen, a key on the keyboard registered in advance, for example, the “ESC” key is pressed.

  Designers can perform design work by referring to the information screen on which detailed information of each court is displayed, so the design work can be advanced while grasping the state of the court and the surrounding situation, Therefore, the efficiency of design work can be improved. In addition, since there is no inconvenience at the time of designing other layers, rework of the design process can be eliminated.

  Furthermore, in order to improve the workability of the design, a coat may be automatically generated by setting parameters, or the cell occupancy of the coat may be adjusted.

For example, the coat area S _C is calculated using parameters that determine the area such as the functional block or cell gate area S _L , the target occupancy O _T of the cell area with respect to the coat area, and the margin R. The parameter is specified externally. The default value is used unless otherwise specified. However, priorities are set between parameters. For example, when the target occupancy and the margin are specified, the target occupancy is prioritized.

  The following shows the formula for calculating the coat area using the specified parameters.

When applying the target cell occupancy: When applying the _{S C = S L * 100 /} O T Formula 1 margin: S _C = S _L * R Formula 2 above formula (1), the area calculated in (2) A coat is automatically created based on the aspect ratio of the designated coat (one-to-one unless otherwise specified).

  FIG. 11 is a diagram for explaining automatic adjustment of the cell occupancy rate by parameter setting. FIG. 11A shows a display example of a coat before adjustment, FIG. 11B shows a parameter setting screen example, and FIG. 11C shows a coat display example after adjustment.

  FIG. 11A shows a coat whose length and width are L and the cell occupancy is 50%. In order to make the cell occupation ratio 40% without changing the functional blocks and cells assigned to the court, it is necessary to change the size of the court. When the designer selects a mode for selecting the cell occupancy rate, a parameter setting screen as shown in FIG. 11B is displayed. When “40” is input to the box for designating the occupancy ratio of the parameter setting screen by the designer, the area of the court is calculated by the above equation (1). A rectangle corresponding to the aspect ratio set from the calculated coat area is formed. Here, since the aspect ratio of the coat is 1: 1, as shown in FIG. 11C, the length and width are each multiplied by 5/4, and the coat is automatically changed to a cell occupation ratio of 40%.

  As described above, the cell occupancy of the coat can be changed or a coat having the desired cell occupancy can be generated simply by setting the cell occupancy to a desired value, thereby enabling efficient design.

  In addition, in order to efficiently perform the design work, the logic cell may be moved between the courts.

  FIG. 12 is a diagram for explaining the movement of the logic cell between the courts. 12A shows the state of the mounting block before movement, FIG. 12B shows the state of the mounting block when all the logic of the court Ca is moved to the court Cb, and FIG. 12C shows the logical assignment of the court Ca. FIG. 12D shows the state of the mounting block when a part of the logic of the court Ca is moved to the court Cb.

  In the coat Ca, functional blocks and cells are allocated with cell occupancy as shown in the graph Ga in FIG. No logic is assigned to the coat Cb. The size of the coat Cb is set to be larger than the coat Ca.

  In order to move all functional blocks and cells assigned to the court Ca to the court Cb, the designer first selects a movement command. Next, the source coat Ca and the destination coat Cb are selected in this order. By the above operation, all the functional blocks and cells of the coat Ca are moved to the coat Cb. Since all the functional blocks and cells of the coat Ca move to the coat Cb, the size of the coat Cb is larger than the size of the coat Ca, so that the occupation ratio of the functional blocks and cells in the coat Cb can be reduced.

  When moving some of the functional blocks or cells assigned to the court Ca to the court Cb, the logical assignment list shown in FIG. 12C is used. In the state shown in FIG. 12A, when the designer selects the movement command and selects the movement source court Ca, the logical assignment list of the functional blocks and cells set in the court Ca shown in FIG. Is displayed.

  The designer selects a functional block and a cell to be moved from the logical assignment list shown in FIG. The selected functional block and cell are displayed in reverse video as shown in FIG. Next, when the destination court Cb is selected, the functional blocks and cells specified in the logical assignment list are moved to the court Cb. When the functional blocks and cells specified in the logical assignment list are moved from the court Ca to the court Cb, the cell occupation ratio of the court Ca is lowered and the cell occupation ratio of the court Cb is increased as shown in FIG.

  As described above, logic can be exchanged between courts as necessary, so that the cell occupancy can be easily adjusted and the efficiency of design work can be improved.

  It is also possible to cancel the assignment of functional blocks and cells to the court.

  FIG. 13 is a diagram for explaining the operation of canceling the assignment of functional blocks and cells to the court. 13A is a state before the logic is released, FIG. 13B is a state after all the logic is released from the court Ca, FIG. 13C is a display example of the logical assignment list of the court Ca, and FIG. D) shows a state after a part of logic is released from the coat Ca.

  In order to release all logics assigned to the court Ca, the designer first selects a release command. Next, by double-clicking the coat Ca, all the functional blocks and cells of the coat Ca are released as shown in FIG.

  In addition, a logical assignment list is used to release some functional blocks and cells allocated to the court Ca. When a cancel command is selected in the state shown in FIG. 13A and coat Ca is selected, a logical assignment list as shown in FIG. 13C is displayed. The designer selects a functional block and a cell to be canceled from the logical assignment list. The selected functional block and cell are displayed in reverse video as shown in FIG. Next, when the court Ca is clicked, the functional blocks and cells specified in the logical assignment list are released from the court Ca, and the cell occupancy is reduced and displayed as shown in FIG.

  In this way, the functional blocks and cells can be released from the coat Ca as necessary, so that the design work can be performed efficiently.

  Coats may be combined as needed during editing.

  FIG. 14 is a diagram for explaining the operation of combining a plurality of coats. FIG. 14A shows the state of the mounting block P before joining, and FIG. 14B shows the state of the mounting block P after joining.

  The mounting block P has a plurality of coats including coats Ca, Cb, and Cc to which functional blocks and cells are assigned.

  When three coats Ca, Cb, and Cc in the mounting block P are combined into one coat, first, a combination command is selected, and then the coats Ca, Cb, and Cc to be combined are selected. At this time, the maximum coordinates (x1, y1) and the minimum coordinates (x2, y2) are obtained from the vertex coordinates of each selected court, and a rectangular area having these two points as vertices is set as a new coat Cd after combination. Note that the functional blocks and cells assigned to the three coats Ca, Cb, and Cc before the combination are assigned to a new coat Cd.

  In addition, editing can be performed by subdividing a single coat into a plurality of coats.

  FIG. 15 is a diagram for explaining an operation of dividing and editing a single court into a plurality of courts. 15A shows the state before the division of the coat to which logic is assigned, FIG. 15B shows the coat image when the coat is divided into 3 × 3, and FIG. 15C shows the single coat 3 × 3 The state after dividing into three is shown.

  When the single coat Ca shown in FIG. 15A is subdivided into a plurality of coats Ca1 to Ca9, the designer first selects a division command. Next, the number of vertical and horizontal divisions or the vertical and horizontal length of the coat is designated.

  When the number of coat divisions in the vertical direction and the number of divisions in the horizontal direction are designated, the coat Ca is subdivided into nine coats Ca1 to Ca9 as shown in FIG. At this time, if a functional block is assigned to the division source court, an algorithm such as pass level sorting is used in the pre-division court to arrange it in the court Ca as shown in FIG. The virtual placement positions of the cells B1 to B9 are obtained, and the cells B1 to B9 are assigned to the divided court closest to the virtual placement position. As a result, the cells B1 to B9 are allocated to the divided coats Ca1 to Ca9. The cell occupancy rates of the divided coats Ca1 to Ca9 are calculated from the allocated functional blocks, and graphs Ga2, Ga3, Ga5, Ga7 indicating the cell occupancy rates are displayed as shown in FIG.

  Further, in this embodiment, the configuration is such that overlap between coats and protrusion from the mounting block can be easily corrected.

  FIG. 16 is a diagram for explaining the operation for correcting the overlap of the coat and the protrusion from the mounting block. 16A shows a state where the coats Ca and Cb overlap, FIG. 16B shows a state where the coats Ca and Cb protrude from the mounting block P, and FIG. 16C shows an overlap between the coats Ca and Cb and the mounting block P. This shows a state in which the protrusion from the head is corrected.

  As shown in FIG. 16A, the coats Ca and Cb overlap each other. In order to eliminate the overlap between the coats Ca and Cb, the designer manually moves the coats Ca and Cb, so that the coats Ca and Cb partially overlap the mounting block P as shown in FIG. Suppose that the physical legitimacy is impaired. In such a case, when the designer selects the check command, the overlap between the mounting block P and the coats Ca and Cb is checked, the positions of the coats Ca and Cb are automatically corrected, and the mounting is performed as shown in FIG. The overlap between the block P and the coats Ca and Cb is eliminated.

  Note that the floor plan creation / display processing unit 41 of the present embodiment can easily arrange cells on the path.

  17 and 18 are diagrams for explaining a cell arrangement method on a path. 17A is a path between cells Ba to Be, FIG. 17B is an arrangement of cells Ba to Be, FIG. 18A is a state where passage points a and b are selected, and FIG. It is a figure for demonstrating the arrangement | positioning method of cell Bb, Bc, Bd.

  As shown in FIG. 17A, the cells Ba to Be are connected in the order of cells Ba → Bb → Bc → Bd → Be. In the cells Ba to Be, as shown in FIG. 17B, the cell Ba is assigned to the coat C3, the cell Be is assigned to the coat C7, and the cells Bb to Bd are assigned to the coat C5.

  The vertex a of the court C3 and the vertex b of the court C7 that have the shortest path connecting the court C3 to which the path start functional block Ca is allocated and the court C7 to which the path end functional block Ce is allocated are Selected as a passing coordinate point. As shown in FIG. 18A, the cell Ba that is the starting point of the path is virtually arranged in the center of the coat C3, and the cell Be that is the end point of the path is virtually arranged in the center of the coat C7.

  Further, the cells Bb, Bc, Bd provided on the coat C5 through which the path passes are, for example, from the start point side to the end point side on the line segment connecting the passing point a and the passing point b as shown in FIG. Virtually placed at intervals.

  Next, a virtual block placement method for functional blocks when a path having branches is set will be described.

  19 to 21 are diagrams for explaining a cell arrangement method on a branching path.

  19A is a path between cells Ba to Bg, FIG. 19B is an arrangement of cells Ba to Bg, FIG. 20A is a state in which cells Ba to Be are virtually arranged according to the path, FIG. (B) is a diagram for explaining a method of virtually arranging cells Bb to Bf and Bg, and FIG. 21 shows a state in which all cells Ba to Bg are virtually arranged.

  As shown in FIG. 19A, the cells Ba to Be are connected in the order of cells Ba → Bb → Bc → Bd → Be through the main path. As shown in FIG. 19A, the cells Bb, Bf, and Bg are connected in the order of the cells Bb → Bf → Bg through the branched path.

  As shown in FIG. 19B, cells Ba to Bg are assigned to coat C3, cell Be is assigned to coat C7, cells Bb to Bd are assigned to coat C5, and cells Bf and Bg are assigned to coat C6. ing.

  The cells Ba to Be are virtually arranged by the virtual arrangement method described with reference to FIGS. At this time, a path with a long distance is given priority in the priority of virtual placement.

  When the cells Bf and Bg are virtually arranged, first, the pass point coordinates of the court C6 to which the cells Bf and Bg are assigned are obtained. Here, since the temporary arrangement position of the branch source cell Bb has already been determined, the passing point coordinate c is determined by the positional relationship between the temporary arrangement position of the cell Bb and the court C6 to which the cells Bf and Bg are allocated. The passing point coordinates c are set, for example, at the intersection of a line segment connecting the apex of the cell Bb close to the coat C6 and the center position of the coat C6 and the outer periphery of the coat C6. Next, the cells Bf and Bg are evenly arranged on a line segment connecting the passing point coordinates c and the center coordinates of the court C6. As described above, the cells Ba to Bg are virtually arranged as shown in FIG.

  As described above, the size and arrangement of the mounting block P, the coat C, and the cell B are set.

  Here, returning to FIG. 4 again, the description will be continued.

  When the cell occupancy falls within the standard in step S5 by the adjustment as described above, the delay is calculated in step S6. Based on the delay calculated in step S6, the path delay list is displayed on the output device 13 in step S7, and the path route is displayed on the output device 13 in step S8.

  FIG. 22 is a diagram for explaining a delay calculation and display method. FIG. 22A shows a path route, and FIG. 22B shows a delay list.

  FIG. 22 illustrates an example in which the delay between the cells Ba to Be is calculated and displayed.

  Use the pin coordinates of the functional blocks that are connected to each other in terms of the net line length between the functional blocks of cell Ba and cell Bb, cell Bb and cell Bc, cell Bc and cell Bd, and cell Bd and cell Be. Using the Manhattan length. The net delay and gate delay are calculated by applying the calculated Manhattan length to the formulas specific to the existing technology. For example, the path route is displayed as shown in FIG. Display the detailed delay list as shown.

  In FIG. 22B, Tline represents a net delay, Tcell represents a gate delay, and Total represents an accumulated delay.

  Based on the delay list shown in FIG. 22B, the designer determines whether or not the delay exceeds the reference value in step S9. If the reference value is not exceeded in step S9, the desired circuit speed is obtained, and the process is terminated. Also, if the reference value is exceeded in step S9, the delay does not exceed the reference value by moving the function block including the cells Ba, Bb, Bc, Bd, Be and the cell to another court in step S10. To do.

  23 and 24 are diagrams for explaining the operation for moving the cell Bc. FIG. 23A shows an example of the connection relation of a plurality of paths and the allocation of cells Ba to Be on the path.

  In FIG. 23A, there are two paths: a path where cells Ba → Bb → Bd → Be are connected and a path where cells Ba → Bb → Bc are connected. Cell Ba is assigned to coat C9, cell Bb is assigned to coat C5, cell Bc is assigned to coat C4, and cells Bd and Be are assigned to coat C3.

  When the cell Bc is moved from the court C4 to the court C8 and re-temporary placement is performed by the provisional placement method shown in FIGS. 17 to 21, since the path having a larger length is preferentially placed, the cell Ba → The temporary arrangement of Bb → Bd → Be is performed first. As a result, as shown in FIG. 23B, the cell Bb moves to the right in the coat C5. Accordingly, the net line length between the cells Ba → Bb and between the cells Bb → Bd changes. As a result, the delay of the cells Ba → Bb → Bd → Be changes. In this case, as a result of moving the functional block in order to obtain a desired delay, the delay of another path may change, and the desired delay may not be obtained, which complicates the design.

  Therefore, even if the cell Bc moves, it is necessary to prevent the delay of the cells Ba → Bb → Bd → Be from changing. For this purpose, it is necessary to prevent the movement of the cell Bb due to the movement of the cell Bc.

  In order to prevent the movement of the cell Bb by the movement of the cell Bc, as shown in FIG. 24, a very narrow coat C10 is set at a position where the cell Bb in the coat C5 exists, and the cell Bb is set in the coat C10. Is assigned. By assigning the cell Bb to the coat C10, the cell Bb can move only within the very narrow coat C10, that is, does not move. As a result, there is no change in the line length between the cells Ba → Bb and between the cells Bb−Bd due to the movement of the cell Bc, so the delay of the cells Ba → Bb → Bd → Be is unchanged from that before the movement, and the cell Bc− Only the delay of Bb can be adjusted.

  The cell Bc is moved as described above, and the delay is adjusted so as not to exceed the reference value.

  After the adjustment, the process returns to step S3 to check the cell occupancy and then check the delay again.

  Conventionally, mounting blocks of hundreds of thousands of gates have been processing units in the floor plan. However, in this embodiment, a virtual layout area, that is, a coat is placed in the LSI chip T or the mounting block P according to the circuit scale. As a result, the processing unit becomes tens of thousands of gates or less, and timing analysis such as cell occupancy and delay in the floor plan can be performed with high accuracy.

As a result, the layout image intended by the designer can be realized at the floor plan stage, and the cause of the timing problem that occurs after mounting design can be investigated at the initial stage of design. Therefore, rework during design can be suppressed to a minimum. For this reason, design efficiency can be improved. In addition, since the delay is sufficiently considered, it greatly contributes to the improvement of the quality of the LSI circuit.
(Appendix 1)
An integrated circuit design apparatus for designing an integrated circuit by setting and arranging blocks for each predetermined hierarchy, wherein a block arrangement processing unit for setting and arranging blocks in the predetermined hierarchy is different from the predetermined hierarchy An integrated circuit design apparatus comprising: an area allocation processing unit that virtually arranges a block of a hierarchy on the predetermined hierarchy; and a block evaluation processing part that evaluates an arrangement state of the block of the predetermined hierarchy and a lower hierarchy.
(Appendix 2)
2. The integrated circuit design apparatus according to claim 1, wherein the block evaluation processing unit includes an area ratio calculation unit that calculates a ratio of the area of the lower layer block to the area of the upper layer block.
(Appendix 3)
The integrated circuit design apparatus according to appendix 2, wherein the area ratio calculation unit reflects at least a wiring and a wiring prohibited area.
(Appendix 4)
4. The integrated circuit design apparatus according to appendix 2 or 3, wherein the block evaluation processing unit displays the area ratio calculated by the area ratio calculation unit as a graphic.
(Appendix 5)
3. The integrated circuit design apparatus according to appendix 1 or 2, wherein the block evaluation processing unit includes a delay calculation processing unit that calculates a delay of a path between the blocks.
(Appendix 6)
6. The integrated circuit design apparatus according to claim 5, wherein the block evaluation processing unit displays a path exceeding a reference value among delays calculated by the delay calculation processing unit.
(Appendix 7)
7. The integrated circuit design apparatus according to appendix 6, wherein the block evaluation processing unit includes a path list display processing unit that displays a list of paths in which the delay calculated by the delay calculation processing unit exceeds the reference value.
(Appendix 8)
The integrated circuit according to claim 6 or 7, wherein the block evaluation processing unit includes a path route display processing unit that displays a path of a path whose delay calculated by the delay calculation processing unit exceeds the reference value. Design equipment.
(Appendix 9)
9. The integrated circuit design device according to any one of appendices 1 to 8, wherein the block can be re-edited.
(Appendix 10)
The integrated circuit according to any one of appendices 1 to 9, further comprising a correction unit that determines the correctness of the position of the block and corrects the position of the block so that the block is in a valid position. Design equipment.
(Appendix 11)
An integrated circuit design method for designing an integrated circuit by setting and arranging blocks for each predetermined hierarchy, the block arrangement processing procedure for setting and arranging the blocks of the predetermined hierarchy, and the predetermined hierarchy Has a block allocation processing procedure for virtually arranging blocks of different hierarchies on the predetermined hierarchy, and a block evaluation processing procedure for evaluating the arrangement status of the blocks of the predetermined hierarchy and lower hierarchy. .
(Appendix 12)
12. The integrated circuit design method according to claim 11, wherein the block evaluation processing procedure calculates a ratio of the area of the block of the lower hierarchy to the area of the block of the upper hierarchy.
(Appendix 13)
13. The integrated circuit design method according to appendix 12, wherein the calculation of the area ratio reflects at least a wiring and a wiring prohibited area.
(Appendix 14)
14. The integrated circuit design method according to appendix 12 or 13, wherein the block evaluation processing procedure displays the calculated area ratio as a graphic.
(Appendix 15)
15. The integrated circuit design method according to claim 11, wherein the block evaluation processing procedure calculates a delay of a path between the blocks.
(Appendix 16)
16. The integrated circuit design method according to claim 15, wherein the block evaluation processing procedure displays a path exceeding a reference value among the calculated delays.
(Appendix 17)
The integrated circuit design method according to claim 16, wherein the block evaluation processing procedure displays a list of paths in which the calculated delay exceeds the reference value.
(Appendix 18)
18. The integrated circuit design method according to appendix 16 or 17, wherein the block evaluation processing procedure displays a path of a path whose calculated delay exceeds the reference value.
(Appendix 19)
The integrated circuit design method according to any one of appendices 11 to 18, wherein the block can be re-edited.
(Appendix 20)
The integrated circuit design method according to any one of appendices 11 to 19, wherein the correctness of the position of the block is determined, and the position of the block is corrected so that the block becomes a valid position.
(Appendix 21)
An integrated circuit design program for designing an integrated circuit by setting and arranging blocks for each predetermined hierarchy, the block arrangement processing procedure for setting and arranging blocks in the predetermined hierarchy, and the predetermined hierarchy Can be executed by a computer comprising: a block allocation processing procedure for virtually arranging blocks of different hierarchies on the predetermined hierarchy; and a block evaluation processing procedure for evaluating the arrangement status of the blocks of the predetermined hierarchy and lower hierarchy Program.
(Appendix 22)
The program according to claim 21, wherein the block evaluation processing procedure calculates a ratio of an area of the block in the lower hierarchy to an area of the block in the upper hierarchy.
(Appendix 23)
The program according to appendix 22, wherein the calculation of the area ratio reflects at least wiring and a wiring prohibited area.
(Appendix 24)
24. The program according to appendix 22 or 23, wherein the block evaluation processing procedure displays the calculated area ratio as a graphic.
(Appendix 25)
The program according to any one of appendices 21 to 24, wherein the block evaluation processing procedure calculates a delay of a path between the blocks.
(Appendix 26)
The program according to claim 25, wherein the block evaluation processing procedure displays a path exceeding a reference value in the calculated delay.
(Appendix 27)
27. The program according to claim 26, wherein the block evaluation processing procedure displays a list of paths for which the calculated delay exceeds the reference value.
(Appendix 28)
28. The program according to appendix 26 or 27, wherein the block evaluation processing procedure displays a path of a path whose calculated delay exceeds the reference value.
(Appendix 29)
29. The program according to any one of appendices 21 to 28, wherein the block is editable.
(Appendix 30)
30. The program according to any one of appendices 21 to 29, wherein the validity of the position of the block is determined, and the position of the block is corrected so that the first to third blocks are valid positions. .

  In addition, this invention is not limited to the said Example, It cannot be overemphasized that a various modified example can be considered in the range which does not deviate from the summary of this invention.

It is a block block diagram of one Example of this invention. It is a functional block diagram of an integrated circuit design program. It is a figure for demonstrating a functional block, a mounting block, a virtual arrangement | positioning area | region (coat), and a path | pass. It is a flowchart of the design method of one Example of this invention. It is a figure for demonstrating creation of a mounting block and a coat | court. It is a figure which shows the example of a display of the cell occupation rate of a coat. It is a figure which shows the graph display reflecting the area | region where arrangement | positioning of a cell is impossible. It is a figure which shows the switching display for every hierarchy block. It is a figure for demonstrating the operation | movement in the case of putting together a some court. It is a figure which shows the example of a screen display of court information. It is a figure for demonstrating the automatic adjustment of the cell occupation rate by parameter setting. It is a figure for demonstrating the movement of the logic cell between coat | courts. It is a figure for demonstrating the operation | movement which cancels | releases allocation to the block of a functional block and a cell. It is a figure for demonstrating the operation | movement which couple | bonds several coats. It is a figure for demonstrating the operation | movement which divides and edits a single court into a some court. It is a figure for demonstrating the operation | movement which correct | amends the overlap of a coat and the protrusion from a mounting block. It is a figure for demonstrating the arrangement | positioning method of the cell on a path | pass. It is a figure for demonstrating the arrangement | positioning method of the cell on a path | pass. It is a figure for demonstrating the arrangement | positioning method of the cell on the path | route which branches. It is a figure for demonstrating the arrangement | positioning method of the cell on the path | route which branches. It is a figure for demonstrating the arrangement | positioning method of the cell on the path | route which branches. It is a figure for demonstrating the calculation and display method of a delay. Operation | movement explanatory drawing for moving a cell to another court is shown. Operation | movement explanatory drawing for moving a cell to another court is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Integrated circuit design apparatus 11 Data processing apparatus 12 Input apparatus 13 Output apparatus 21 Hard disk drive 22 RAM
23 CPU
24 exchangeable storage device 25 communication device 31 integrated circuit design program 41 floor plan creation / display processing unit 42 functional block allocation processing unit 43 area ratio calculation processing unit 44 path delay calculation processing unit 45 path list display processing unit 46 path route display Processing part

Claims (8)

An integrated circuit design apparatus for designing an integrated circuit by setting and arranging a coat, which is a virtual layout area obtained by dividing a mounting block, from a designer for each of a plurality of mounting blocks which are areas obtained by dividing a chip area. Because
A block arrangement unit for arranging before constant mounting blocks where the logger over bets,
An area allocation processing section for placement of the functional blocks in the copolymers over preparative,
The predetermined mounting block, and a block evaluation processing unit that evaluates an arrangement state of a lower layer coat that is lower than the predetermined mounting block,
The block evaluation processing unit calculates a ratio of the area of the functional block in the lower layer to the area of the court arranged in the predetermined mounting block in accordance with the placement of the functional block on the court by the area allocation processing unit. An integrated circuit design apparatus that displays the calculated area ratio between the functional block and the coat as a graphic for each coat. The integrated circuit design device according to claim 1, wherein the block evaluation processing unit switches the mounting block displaying the area ratio or the layer of the coat in accordance with a switching input. The said block evaluation process part displays the figure which shows the area ratio of the said functional block and the said coat visually distinguishing according to the calculated area ratio of the said functional block and the said court. Integrated circuit design equipment. An integrated circuit design apparatus for designing an integrated circuit by setting and arranging a coat, which is a virtual layout area obtained by dividing a mounting block, from a designer for each of a plurality of mounting blocks which are areas obtained by dividing a chip area. Because
A block arrangement unit for arranging a predetermined mounting block before Kiko over preparative,
The functional blocks, before Kiko over preparative, an area allocation processing unit to place,
The predetermined mounting block, and a block evaluation processing unit that evaluates an arrangement state of a coat of a lower hierarchy that is a lower hierarchy with respect to the predetermined mounting block,
The block evaluation processing unit determines a ratio of the area of the functional block in the lower hierarchy to the area of the court arranged in the predetermined mounting block in accordance with the arrangement of the functional block on the court by the area allocation processing unit. An area ratio calculation unit to calculate,
It is determined whether or not the calculated area ratio between the functional block and the court is within a reference, and when it is determined that the area ratio is within the reference, a delay in a path between lower-layer courts arranged is calculated. An integrated circuit design apparatus having a delay calculation processing unit. 5. The integrated circuit design apparatus according to claim 4, wherein the block evaluation processing unit displays a path in which the delay calculated by the delay calculation processing unit exceeds the reference value. 6. The integrated circuit design apparatus according to claim 5, wherein the block evaluation processing unit includes a path list display processing unit that displays a list of paths in which the delay calculated by the delay calculation processing unit exceeds the reference value. 7. The integrated circuit design apparatus according to claim 5, wherein the block evaluation processing unit includes a path route display processing unit that displays a path of a path whose delay calculated by the delay calculation processing unit exceeds the reference value. An integrated circuit design apparatus for designing an integrated circuit by setting and arranging a coat, which is a virtual layout area obtained by dividing a mounting block, from a designer for each of a plurality of mounting blocks which are areas obtained by dividing a chip area. Because
A block arrangement processing unit for setting a coat in a mounting block of the integrated circuit;
An area allocation processing section for placement on the front Symbol coated functional blocks,
An integrated circuit design apparatus comprising: a delay calculation processing unit that calculates a delay in a path between the functional blocks arranged on the court in accordance with the arrangement of the functional blocks on the court by the area allocation processing unit .

Images