JP4615898B2 - Operation stable pixel bias circuit - Google Patents

Description

  The present invention generally relates to semiconductor imaging devices (imagers). More particularly, the present invention relates to a method and apparatus for improving bias current stability in an imaging device.

  FIG. 1 shows a conventional imaging apparatus (imager) 100 in a block diagram form. As illustrated, the imaging apparatus 100 includes a power source 110, a pixel array 120 including a plurality of pixels 121, a plurality of load circuits 130, a plurality of sample-hold circuits 140, and a plurality of amplifiers 150. Usually, a very large number of pixels 121 are arranged in a plurality of rows and columns. However, for simplicity, the pixel array 120 shown in FIG. 1 includes only two rows and two columns of the pixel array 121. The power supply 110 generates a bias current IBIAS with an array pixel voltage of VAAPIX. The load circuit 130 generates a bias current IBIAS, and this bias current IBIAS is supplied to each pixel 121 of the imaging device 100. The imaging apparatus 100 includes a control circuit 160 that generates control signals (for example, ROW, TX, RESET, SHR, SHS, and OUT) shown in the figure, and additional image processing for further processing the signals output from the pixels 121. A circuit 170 is also provided.

  Here, the operation of the imaging apparatus 100 will be described with reference to FIGS. FIG. 2 shows a conventional four-transistor pixel 121. The pixel 121 includes a photodiode 122, a transfer transistor 123, a reset transistor 124, a source follower transistor 125, and a row selection transistor 126. Pixel 121 receives a ROW control signal at node (node) F1 (coupled to the gate of row select transistor 126), a TX control signal at node (node) D1 (coupled to the gate of transfer transistor 123), and A RESET control signal is received at node C1 (coupled to the gate of reset transistor 124). The pixel 121 receives power from an output node (for example, the node B01 or B02) of the power supply 110 at the node A1, and generates a reset signal “Vrst” and an optical signal “Vsig” as outputs of the node B1. As will be described in detail below, the pixel 121 also includes a charge detection node E1.

  Here, it demonstrates with reference to the timing diagram of FIG. As can be seen, initially, the control signals ROW, RESET, TX, SHR, and SHS are not rising (ie, are at a logic low level) (ie, at time t0).

  At time t1, the ROW control signal rises and is supplied to the node F1 to operate the row selection transistor 126.

  At time t2, the RESET control signal rises so that the voltage VAAPIX supplied from the power supply 110 to the node A1 is supplied to the charge detection node E1. Since node E1 is coupled to the gate of transistor 125 and node F1 is coupled to the gate of transistor 126, transistors 125 and 126 are both conducting. As a result, the reset signal Vrst is output to the node B1.

  At time t3, the control signal falls and the charge detection node E1 enters a floating state (floating). The photodiode 122 has already accumulated electric charge at the node P1 while being exposed from the last initialization. This exposure period is also known as the integration period.

  At time t5, the control signal TX rises, and charge transfer from the node P1 to the electrification detection node E1 is performed. As a result, charge is sent to the node E1. This charge reduces the voltage at node E1 and affects the conduction of the source follower transistor 125. Since the row selection transistor 126 is still conductive, the optical signal Vsig based on the charge transferred to the node E1 is output to the node B1. FIG. 5 shows the variability of the optical signal Vsig at the node B1 by three traces (lines) 511, 512, and 513. The upper trace 511 shows the output when there is light during the integration period and the photodiode 122 is only slightly exposed. Intermediate trace 512 corresponds to a moderate exposure during the integration period. The lower trace 513 corresponds to a strong exposure during the integration period.

  At time t8, the ROW control signal decreases, and the row selection transistor 126 is turned off. As a result, the output of the node B1 is cut off.

  Accordingly, the pixel 121 generates two output signals, namely a reset signal Vrst and an optical signal Vsig. The two signals Vrst and Vsig are generated at different times, but both signals are output to the node B1. The output of the pixel 121 is directed to the load circuit 130, whereby the source follower transistor 125 and the load circuit 130 constitute a voltage follower circuit when the ROW control signal rises.

  FIG. 3 shows a load circuit 130 used in the imaging apparatus 100. The circuit 130 is a current sink for output of the pixel circuit 121. As shown in the figure, the load circuit 130 receives the output signals Vrst and Vsig of the pixel 121 at the node A2, and generates an output corresponding to these signals at the node B2. The outputs of the load circuit 130 are collectively referred to as VPIXOUT, and this output corresponds to a form in which the reset signal between times t3 and t5 is modified, and in a form in which the optical signal between times t5 and t8 is modified. Correspond. Transistor 131 has its gate coupled to node C2, and node C2 receives control signal VLN. The control signal VLN is used to adjust the bias current generated by the transistor 131 and to optimize the performance of the source follower circuit with respect to power consumption and speed. This transistor 131 is often referred to as a bias transistor.

  FIG. 4 is a circuit diagram of the sample-hold circuit 140. The function of the sample-hold circuit 140 is to sample (sample) and hold (hold) the reset signal Vrst and the optical signal Vsig of the pixel 121 and output a corresponding difference signal. The difference signal output by the sample-hold circuit 140 includes a reset signal Vrst (node B31) and an optical signal Vsig (node B32) as its components. The operation of the sample-and-hold circuit 140 will be described below.

  At time t3, the sample-hold circuit 140 receives the reset signal Vrst at the node A3, and the SHR control signal transitions from low to high. Both the OUT control signal and the SHS control signal are low, so that while the transistor 141 is conducting, the transistors 142, 145, and 146 are non-conducting and the transistor 141 is conducting. Accordingly, the reset signal Vrst charges the capacitor 143, whereby the reset signal Vrst is stored in the capacitor 143.

  At time t4, the SHR control signal changes from high to low, and the transistor 141 is turned off.

  At time t5, the SHS control signal transitions from low to high. Both the OUT control signal and the SHR control signal are low, so that the transistors 141, 145, and 146 are nonconductive and the transistor 142 is conductive. Therefore, the optical signal Vsig charges the capacitor 144, whereby the optical signal Vsig is stored in the capacitor 144.

  At time t7, the SHS control signal changes from high to low, and the transistor 142 is turned off.

  At time t8, the OUT control signal transitions from low to high, causing transistors 145 and 146 to conduct. Accordingly, charges from the capacitors 143 and 144 simultaneously flow to the nodes B31 and B321 via the transistors 145 and 146, respectively. For simplicity, the signal resulting from the charge flowing from capacitor 143 to node B31 is labeled Vrst and the signal resulting from the charge flowing from capacitor 144 to node B32 is labeled Vsig.

  Here, returning to FIG. As can be seen, the Vsig and Vrst signals output from nodes B31 and B32, respectively, are provided to differential amplifier 150, which generates a single-ended output VOUT. The VOUT signal represents the output of the pixel 121 and can be supplied to the image processing circuit 170 for digitization, digital processing, and storage.

  At time t9, the OUT control signal transitions from high to low, and the transistors 145 and 146 are turned off.

  FIG. 6 is a block diagram of a conventional power supply 110. As shown, the power supply 110 includes a power supply 111 coupled to a resistor 112. Resistor 112 represents the output resistance of power supply 111 and any parasitic components between power supply 111 and nodes B01 and B02. The circuit 110 outputs the bias current IBIAS to the nodes B01 and B02 with the predetermined voltage VAAPIX.

  One problem associated with the imaging device 100 described above is that when the pixel 121 is exposed to very bright light, the charge transferred from the node P1 to the node E1 resets the voltage at the node E1 (ie, VAAPIX). The source follower transistor 125 can be made non-conductive by reducing the voltage to the ground voltage. This phenomenon is known as saturation. In the imaging apparatus 100, pixel saturation causes a bias current to be cut off. This causes voltage fluctuations in the output signals of the nodes B01 and B02 of the power supply 110. Since the power supply 110 is coupled to multiple pixels 121, saturation of one or more pixels 121 can affect the output of other pixels. In particular, the saturation of one or more pixels appears as unstable horizontal band noise in the image generated by the imaging device 100.

  Another problem associated with the imaging apparatus 100 described above occurs when extremely bright light such as sunlight enters the pixel 121. This saturates the photodiode 122 by generating a very large current in the photodiode 122. This current can overflow through transfer transistor 123 and charge detection node E1. In addition, the source junction of the reset transistor 124 also generates a photocurrent between the node E1 and the substrate, and this photocurrent is applied to the node E1 when the reset transistor 124 is turned off. Reduce the voltage. Actually, under such a strong irradiation condition, after the reset transistor 124 is turned off at the time t3, the voltage of the node E1 decreases, and the level of the reset signal Vrst decreases between the times t3 and t4. As a result, the voltage at the node E1 is stored in the capacitor 143 when the control signal SHR drops at time t4. Under such strong light conditions, the optical signal Vsig is always saturated. That is, the optical signal Vsig is set to the minimum level near the ground potential. Since Vout is equal to Vsig−Vrst, a decrease in the level of the reset signal Vrst causes a decrease in the Vout signal. Thus, very bright light incident on the pixel array causes a drop in the output signal, which eventually appears as a negative photoconversion response. This phenomenon is also known as inverted video noise.

  Therefore, there is a need for a bias current supply circuit for an imaging device that can generate a more stable pixel bias current regardless of the amount of light incident on the pixels of the imaging device. There is also a need for a bias current supply circuit that is resistant to inversion video noise when imaging extremely bright objects.

(Summary of Invention)
A preferred embodiment of the method and apparatus of the present invention provides a power supply that provides a stable pixel bias current supply within an imaging device. This power supply features a current bypass circuit for preventing the bias current cutoff from adversely affecting the output stability of the power supply. This power supply is also characterized by a voltage limiter (limiter) for preventing the pixel from outputting an output voltage outside a predetermined range when very strong light is incident on the pixel.

  These and other advantages and features of the present invention will become more apparent from the detailed description of the embodiments of the present invention with reference to the following drawings.

(Detailed description of examples)
Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same reference number represents the same element. FIG. 7A shows a bias current supply circuit 700 according to a first preferred embodiment of the present invention.

  The bias current supply circuit 700 includes a plurality of taps 740. More specifically, there are n taps 740, where n corresponds to the number of columns that receive power from the bias current supply circuit 700. The bias current supply circuit 700 supplies the current IBIAS to the node 741 of each tap 740, and the node 741 is coupled to the node A1 (FIG. 2) of each pixel 121. The voltage VAAPIX is supplied from the node 711 of the power supply 710. Node 711 is coupled to line 721, which is coupled to each node 741. The power supply 710 must be able to supply NIBIAS output current at a voltage of VAAPIX. The current level of the current NIBIAS must be at least n times the current IBIAS. The power supply 710 generates another output signal VSLICE at the node 712. Node 712 is coupled to line 722, which is coupled to the gate of each transistor 731 in circuit 700. Each transistor 731 has one source / drain coupled to line 721 and the other source / drain coupled to a respective node 742. Each node 742 is an output node coupled to node B1 and its associated pixel 121 (FIG. 2).

  The signal VSLICE is the voltage level of VS, where VS is greater than the threshold voltage VT of the transistor 731. When the imaging apparatus 100 is operated using the power source 700 and dark light or moderate light is incident on the pixel 121, the optical signal voltage Vsig becomes higher than the voltage VS-VT. As a result, the transistor 731 is turned off. Thus, when dark or moderate light is incident on the pixel 121, the imaging device 100 operates as previously described with respect to FIG.

  As previously described, when bright light is incident on the pixel 121, the source follower transistor 125 in the pixel 121 becomes non-conductive, so that the current IBIAS no longer passes through the node 741. It does not flow to the node A1 of the pixel 121. However, at the same time, the voltage Vsig of the optical signal drops below the voltage VS−VT, thereby making the transistor 731 conductive. Since one source / drain of transistor 731 is coupled to line 721 and the other source / drain is coupled to node B 1 of pixel 121, the circuit formed by transistor 731 is connected from node 741 to node 742. Acting as a current bypass, this current bypass allows the current IBIAS to continue to flow through the pixel 121 even when the source follower transistor 125 is non-conductive. As a result, even when bright light enters the pixel 121, the output current from the power source 710 remains constant.

  The embodiment of the present invention of FIG. 7A addresses the problem of unstable horizontal band noise and reduces it, but not the problem of inverted video noise. FIG. 7B shows a second preferred embodiment of the present invention, which provides a method for reducing inverted video noise. The second preferred embodiment of the present invention utilizes a power supply 700 'similar to the bias current supply circuit 700 of the first preferred embodiment. However, circuit 700 'includes a new power supply 710' and is intended for use with a new control circuit 160 '. The power supply 710 'is similar to the power supply 710 of the first embodiment, but further includes a new signal input node 713 for receiving a new control signal SLICE_R. The power supply 710 'is modified to control the output of the VSLICE control signal based on the state of the SLICE_R control signal. SLICE_R is a control signal generated by the modified control circuit 160 ', which is similar to the control circuit 160 (FIG. 1), but also generates a SLICE_R signal. The characteristics of the SLICE_R signal will be described below.

  The SLICE_R control signal is supplied from the control circuit 160 'to the power source 710'. When the SLICE_R control signal rises, the power supply 710 'outputs VR as a VSLICE signal. When the SLICE_R control signal falls, the power supply 710 'does not output the VSLICE signal, i.e. keeps VSLICE at ground potential.

  As shown in the supplemental timing diagram of FIG. 8, the SLICE_R control signal is controlled to rise simultaneously with the rise of the SHR control signal at time t3. The SLICE_R control signal falls at an arbitrary time between the fall of the SHR control signal at t4 and the rise of the SHS control signal at time t5. Therefore, the SLICE_R control signal rises only during the reset phase of pixel operation. That is, the power source 710 'is controlled to output the VSLICE signal exclusively during the sampling and holding (holding) stage of the reset signal Vrst. When dark or normal level light is incident on a pixel, the presence of the VSLICE signal does not change the operation of the imaging device 100. However, when very bright light is incident on the pixel, the presence of the VSLICE signal prevents the voltage level of the reset signal Vrst from dropping below VSLICE_VT, which makes the level of the reset signal Vrst very bright. Prevent being affected by light. Therefore, the problem of inverted video noise is addressed by preventing the reset signal Vrst from being significantly affected when extremely bright light is incident on the pixel 121.

  The third preferred embodiment of the present invention addresses both the unstable load noise problem and the inverted video noise problem. The third preferred embodiment utilizes the same bias current supply circuit 700 'as the second preferred embodiment (FIG. 7B). Now described with reference to the supplemental timing diagram of FIG. 9, and as can be seen, the VSLICE signal is generally at the voltage level of VS. However, when the SLICE_R control signal rises, the VSLICE signal goes to a higher VR voltage level. As described in connection with the second preferred embodiment above, the inverted video noise can be reduced by setting the VSLICE signal to the voltage level of VR during the reset phase. Similarly, as described with respect to the first preferred embodiment above, by setting the VSLICE signal to the voltage level of VS during the optical signal stage, unstable load noise is reduced. Thus, the third preferred embodiment combines the elements of the first and second preferred embodiments to address both the unstable load noise and inverted video noise problems.

  FIG. 10 shows a bias power supply circuit 1000 according to a fourth preferred embodiment of the present invention. The power supply circuit 1000 can respond to the problem of inverted video noise. The fourth preferred embodiment operates in the same manner as the second preferred embodiment. However, the fourth preferred embodiment utilizes a different mechanism for generating an output signal at node 742. The second preferred embodiment requires power supply 710 to be able to keep the VSLICE signal continuous between voltage VR and ground voltage, and using the VSLICE signal to control transistor 731 to produce the output of node 742. In contrast, the power supply 1010 of the bias power supply circuit 1000 is configured to output the VSLICE signal at a single voltage level VR. An additional transistor 1032 is coupled in series between the source / drain of transistor 731 and node 742 using its source and drain terminals. Transistor 1032 has its gate coupled to signal line 1023, which is coupled to node 1050. The control circuit 160 (FIG. 1) is changed so as to also output a SLICE_EN control signal. The SLICE_EN control signal is used to control the conduction of the transistor 1032. Since the transistor 1032 is coupled in series between the source / drain terminal of the transistor 731 and the node 742 using its source / drain terminal, the transistor 1032 is connected from the power source 1010 (node 711 thereof) to the node 742. It can be used as a control device for the current. More specifically, referring back to FIG. 8, the SLICE_EN control signal is output so that the output of the node 742 in the fourth preferred embodiment is the same as the output of the node 742 in the third preferred embodiment. Therefore, the control circuit 160 is changed.

  FIG. 11 shows a power supply 1100 according to a fifth preferred embodiment of the present invention. The power supply 1100 can address both the unstable load noise problem and the inverted video noise problem (as in the third and fourth preferred embodiments). The fifth preferred embodiment operates in the same manner as the third preferred embodiment. However, the fifth preferred embodiment utilizes a different mechanism for generating an output signal at node 742. The third preferred embodiment controlled the output signal at node 742 by controlling the conduction of transistor 731 by supplying a VSCALE control signal to the gate of transistor 731. This requires that the power supply 710 can continue the VSLICE signal between the voltages VR and VS. In the fourth embodiment, the power supply 1010 supplies the VSLICE control signal at a fixed voltage level VR. In the embodiment shown in FIG. 11, the power supply 1110 of the power supply 1100 outputs the VSCALE1 signal on the additional signal line 1121 at the voltage level VR and outputs the VSCALE2 signal on the additional signal line 1123 at the voltage level VS. Thus, the power supply 1110 is configured.

  The power supply 1100 controls the output of the node 742 by using four transistors 1031a, 1031b, 1032, and 1033. More specifically, each of transistors 1031a and 1031b operates in the same manner as transistor 731 (FIG. 7A). Transistor 1032 is coupled in series between the source / drain of transistor 1031b and node 742 using its source and drain. Similarly, transistor 1033 is coupled in series between the source / drain of transistor 1031a and node 742 using its source and drain. The control signal 160 (FIG. 1) is modified to supply new SLICE_EN1 and SLICE_EN2 control signals to the gates of transistors 1032 and 1033, respectively. The states of the SLICE_EN1 control signal and the SLICE_EN2 control signal are complementary. These states are either a signal flowing from the line 711 via the transistors 1031 and 1033 or a signal flowing from the line 711 via the transistors 1031b and 1032. Is set by the control circuit 160 so as to be supplied to the node 742. In this manner, bias current supply circuit 1000 generates the same output signal at node 742 as that generated by the third preferred embodiment.

  FIG. 12 shows a processor system 1200. The processor system 1200 includes a processor device 1210. The processor unit 1210 can be, for example, a digital camera, a personal computer, or other image processing unit, and includes, for example, a central processing unit 1220, a memory 1230, and an I / O controller 1240. The memory 1230 can be a conventional memory. Alternatively, the memory 1230 may be a removable memory such as a removable flash memory device or may include a removable memory. The I / O controller 1240 is coupled to the interconnect 1260, which interconnects the processor-based device 1210 to the imaging device 100 '. The imaging device 100 'is similar to the imaging device 100 (FIG. 1), but incorporates a bias current supply circuit according to the principle of the present invention. As shown in FIG. 12, this bias current supply circuit is the circuit 700 of the first preferred embodiment, but the circuit 700 may be a bias current supply circuit (eg, circuits 700 ′, 1000, And 1100) can be substituted.

  Thus, the present invention provides numerous embodiments of pixel power supply circuits that address the problem of unstable load noise and / or inverted video noise that can be encountered in any imaging system. The present invention addresses the problem of unstable load noise by improving bias current stability with a current bypass circuit, which operates when the source follower is saturated. The present invention addresses the problem of inverted video noise by using a voltage limiter at the pixel output node to limit the reset voltage output from the pixel.

  Although the invention has been described in detail with reference to preferred embodiments, it is clear that the invention is not limited to the embodiments disclosed above. Rather, the present invention can be modified in a number of variations, alternatives, replacements, or equivalent configurations not described above, and these variations are within the scope of the present invention. Accordingly, the present invention is not limited to the above description or drawings, but is limited only by the scope of the claims.

It is a block diagram of the conventional imaging device (imager). It is a circuit diagram of the conventional pixel. It is a circuit diagram of the conventional load circuit. It is a circuit diagram of a conventional sample-hold circuit. FIG. 2 is a timing chart regarding the operation of the imaging apparatus in FIG. 1. It is a circuit diagram of a conventional bias current supply circuit. 1 is a circuit diagram of a bias current supply circuit according to a first preferred embodiment of the present invention. FIG. FIG. 4 is a circuit diagram of a bias current supply circuit according to second and third preferred embodiments of the present invention. FIG. 6 is a supplementary timing diagram for operating a bias current supply circuit according to a second preferred embodiment of the present invention. FIG. 6 is a supplementary timing diagram for operating a bias current supply circuit according to a third preferred embodiment of the present invention. FIG. 6 is a circuit diagram of a bias current supply circuit according to a fourth preferred embodiment of the present invention. FIG. 10 is a circuit diagram of a bias current supply circuit according to a fifth preferred embodiment of the present invention. 1 is a block diagram of a processor-based system incorporating the principles of the present invention.

Explanation of symbols

100 Imaging device (imager)
110 Power supply 111 Power supply 112 Resistor 120 Pixel array 121 Pixel 122 Photodiode 123 Transfer transistor 124 Reset transistor 125 Source follower transistor 126 Row selection transistor 130 Load circuit 131 Transistor 140 Sample-hold circuit 141 Transistor 142 Transistor 143 Capacitor 144 Capacitor 145 Transistor 146 Transistor 150 Amplifier 160 Control circuit 170 Image processing circuit 700 Bias current supply circuit 710 Power supply 711 Node 712 Node 713 Signal input node 721 Line 722 Line 731 Transistor 740 Tap 741 Node 742 Node 1000 Bias power supply circuit 1010 Power supply 1023 Signal line 1031 Transi Star 1032 Transistor 1033 Transistor 1050 Node 1100 Power supply 1110 Power supply 1121 Signal line 1123 Signal line 1200 Processor system 1210 Processor unit 1220 Central processing unit 1230 Memory 1240 I / O controller 1260 Interconnection

Claims (40)

A power signal for power supply is supplied to a pixel of a solid-state imaging device, the pixel having a power input node that receives power for driving the pixel and a signal output node that outputs a signal related to light incident on the pixel. A power supply having a first node to supply and a second node to supply a first control signal;
A power supply circuit comprising a plurality of taps, wherein the plurality of taps are connected in parallel to the power source, and each of the plurality of taps is
A first output node coupled to the first node;
A first transistor;
In a power supply circuit comprising a second output node,
Coupling the first output node to the power input node of the pixel and coupling the second output node to the signal output node of the pixel;
Using the first source / drain and the second source / drain of the first transistor to couple the first transistor in series between the first node and the second output node;
The first transistor is controllable by the first control signal;
A power supply circuit, wherein the gate of the first transistor is coupled to the second node.   The power supply is configured to selectively switch between a ground potential or a first predetermined voltage and output as the first control signal, and the first predetermined voltage is higher than a threshold voltage of the first transistor. The power supply circuit according to claim 1.   The power source is configured to selectively switch between either a first predetermined voltage or a second predetermined voltage and output as the first control signal, and the first predetermined voltage is higher than a threshold voltage of the first transistor, The power supply circuit according to claim 1, wherein the second predetermined voltage is higher than the first predetermined voltage.   The power supply is configured to selectively switch between a ground potential or a first predetermined voltage and output as the first control signal, and the first predetermined voltage is higher than a threshold voltage of the first transistor. The power supply circuit according to claim 1.   The power source is configured to selectively switch between a ground potential or a second predetermined voltage and output as the first control signal, the second predetermined voltage being higher than the first predetermined voltage, and the first The power supply circuit according to claim 4, wherein a predetermined voltage is higher than a threshold voltage of the first transistor.   The power supply is configured to output the first control signal at the second predetermined voltage when the pixel outputs a reset signal at a predetermined voltage. Power supply circuit.   The power supply circuit according to claim 6, wherein the power supply is configured to output the first control signal at a ground potential when the pixel does not output the reset signal.   The power supply is configured to receive a second control signal, and selectively switch between a ground potential or the second predetermined voltage based on the state of the second control signal, and output the selected signal as the first control signal. The power supply circuit according to claim 5, wherein:   The power supply is configured to selectively switch between either a first predetermined voltage or a second predetermined voltage and output the first control signal, and the first predetermined voltage is higher than a threshold voltage of the first transistor. The power supply circuit according to claim 1, wherein the second predetermined voltage is higher than the first predetermined voltage.   10. The power according to claim 9, wherein the power source is configured to output the first control signal at the second predetermined voltage when the pixel outputs the reset signal. 11. Supply circuit.   11. The power according to claim 10, wherein the power source is configured to output the first control signal at the first predetermined voltage when the pixel does not output the reset signal. 11. Supply circuit.   The power supply receives a second control signal, and selectively switches between the first predetermined voltage and the second predetermined voltage based on the state of the second control signal, and outputs the first control signal as the first control signal. The power supply circuit according to claim 9, wherein the power supply circuit is configured as follows. The power supply circuit further comprises a first external control node for receiving a first external control signal;
Each of the plurality of taps further comprises a second transistor;
Using the first source / drain and the second source / drain of the second transistor to couple the second transistor in series between the source / drain of the first transistor and the second output node;
2. The power supply circuit according to claim 1, wherein a gate of the second transistor is coupled to the first external control node. A first external control node wherein the power supply circuit further receives a first external control signal;
A second external control node for receiving a second external control signal;
Each of the plurality of taps further includes
A second transistor;
A third transistor;
With a fourth transistor,
The power supply further comprises a third node for supplying a second control signal;
Using the first source / drain and the second source / drain of the second transistor to couple the second transistor in series between the source / drain of the first transistor and the second output node;
Coupling the gate of the second transistor to the first external control node;
Using the first source / drain and the second source / drain of the third transistor to couple the third transistor in series between the first node and the first source / drain of the fourth transistor;
Coupling the gate of the third transistor to the third node;
Using the first source / drain and the second source / drain of the fourth transistor to couple the fourth transistor in series between the source / drain of the third transistor and the second output node;
The power supply circuit of claim 1, wherein the gate of the fourth transistor is coupled to the second external control node. In a method of supplying power to a pixel of a solid-state imaging device, the pixel having a power input node that receives power for driving the pixel and a signal output node that outputs a signal related to light incident on the pixel.
Supplying a first bias current to the power input node of the pixel;
Supplying a second bias current to the signal output node of the pixel ;
A method for supplying power to a pixel, comprising the step of setting the level of the second bias current to either a first predetermined level or a second predetermined level . 16. The method according to claim 15, wherein the setting step is based on whether or not the pixel outputs a reset signal having a predetermined voltage to the signal output node. The method of claim 15, wherein the setting is based on a state of an external control signal. In a method of supplying power to a pixel of a solid-state imaging device, the pixel having a power input node that receives power for driving the pixel and a signal output node that outputs a signal related to light incident on the pixel.
Supplying a first bias current to the power input node of the pixel;
Providing a second bias current to the signal output node of the pixel,
The pixel feeding method, wherein the second bias current is supplied to the pixel only when a reset signal of the predetermined voltage of the pixel reaches a level outside a predetermined range. First power for feeding power to a pixel of a solid-state imaging device, the pixel having a power input node that receives power for driving the pixel and a signal output node that outputs a signal related to light incident on the pixel. A power supply having a first node for supplying a signal and a second node for supplying a first control signal;
A power supply circuit comprising a plurality of taps each coupled to the power source,
Each of the taps
A first output node coupled to the first node of the power source and receiving the first power signal from the first node;
A bypass circuit path having a power input node coupled to the first node, a control node coupled to the second node, and a second output node outputting a second power signal;
With
The power supply circuit, wherein the first output node is coupled to the power input node of the pixel, and the second output node is coupled to the signal output node of the pixel. A power source for supplying power to a pixel of a solid-state imaging device, the pixel having a power input node that receives power for driving the pixel and a signal output node that outputs a signal related to light incident on the pixel When;
A power supply circuit comprising a plurality of taps,
Each of the taps is coupled to the power supply and receives a power signal and a control signal from the power supply.
Each of the taps
A first output node for generating a first bias current supplied to the power input node of the pixel;
A second output node for generating a second bias current supplied to the signal output node of the pixel;
A power supply circuit comprising: A pixel array having a plurality of pixels organized in a plurality of rows and a plurality of columns, wherein each of the pixels is associated with a power input node that receives power to drive the pixels and light incident on the pixels A pixel array having a signal output node for outputting a signal to be output;
An imaging device comprising a power supply circuit coupled to each pixel of the pixel array,
The power supply circuit is
A power supply having a first node for supplying a power signal and a second node for supplying a first control signal;
A plurality of taps, wherein the plurality of taps are coupled in parallel to the power source, each of the plurality of taps supplying power to at least one of the plurality of pixels, and each of the plurality of taps ,
A first output node coupled to the first node;
A first transistor controllable by the first control signal;
In an imaging device comprising a second output node,
Coupling the first output node to the power input node of the pixel and coupling the second output node to the signal output node of the pixel;
Using the first source / drain and the second source / drain of the first transistor to couple the first transistor in series between the first node and the second output node;
An imaging device, wherein the gate of the first transistor is coupled to the second node. The power supply is configured to selectively switch between a ground potential or a first predetermined voltage and output as the first control signal, and the first predetermined voltage is higher than a threshold voltage of the first transistor. The imaging apparatus according to claim 21, wherein: The power supply is configured to selectively switch between either a first predetermined voltage or a second predetermined voltage and output the first control signal, and the first predetermined voltage is higher than a threshold voltage of the first transistor. The image pickup apparatus according to claim 21, wherein the second predetermined voltage is higher than the first predetermined voltage. The power supply is configured to selectively switch between a ground potential or a first predetermined voltage and output as the first control signal, and the first predetermined voltage is higher than a threshold voltage of the first transistor. The imaging apparatus according to claim 21, wherein: The power source is configured to selectively switch between a ground potential or a second predetermined voltage and output as the first control signal, the second predetermined voltage being higher than the first predetermined voltage, and the first The imaging apparatus according to claim 24, wherein a predetermined voltage is higher than a threshold voltage of the first transistor. The power supply is configured to output the first control signal at the second predetermined voltage when the pixel outputs a reset signal at a predetermined voltage. Imaging device. 27. The imaging apparatus according to claim 26, wherein the power supply is configured to output the first control signal at a ground potential when the pixel does not output the reset signal. The power supply is configured to receive a second control signal, and selectively switch between a ground potential or the second predetermined voltage based on the state of the second control signal, and output the selected signal as the first control signal. 26. The imaging apparatus according to claim 25, wherein The power supply is configured to selectively switch between either a first predetermined voltage or a second predetermined voltage and output the first control signal, and the first predetermined voltage is higher than a threshold voltage of the first transistor. 24. The imaging apparatus according to claim 23, wherein the second predetermined voltage is higher than the first predetermined voltage. 30. The imaging according to claim 29, wherein the power supply is configured to output the first control signal at the second predetermined voltage when the pixel outputs the reset signal. apparatus. 31. The imaging according to claim 30, wherein the power source is configured to output the first control signal at the first predetermined voltage when the pixel does not output the reset signal. apparatus. The power supply receives a second control signal, and selectively switches between the first predetermined voltage and the second predetermined voltage based on the state of the second control signal, and outputs the first control signal as the first control signal. 30. The imaging apparatus according to claim 29, wherein the imaging apparatus is configured as follows. The imaging device further comprises a first external control node for receiving a first external control signal;
Each of the plurality of taps further comprises a second transistor;
Using the first source / drain and the second source / drain of the second transistor to couple the second transistor in series between the source / drain of the first transistor and the second output node;
The gate of the second transistor is coupled to the first external control node
The imaging apparatus according to claim 21, wherein: The imaging device further includes
A first external control node receiving a first external control signal;
A second external control node for receiving a second external control signal;
Each of the plurality of taps further includes
A second transistor;
A third transistor;
With a fourth transistor,
The power supply further comprises a third node for supplying a second control signal;
Using the first source / drain and the second source / drain of the second transistor to couple the second transistor in series between the source / drain of the first transistor and the second output node;
Coupling the gate of the second transistor to the first external control node;
Using the first source / drain and the second source / drain of the third transistor to couple the third transistor in series between the first node and the first source / drain of the fourth transistor;
Coupling the gate of the third transistor to the third node;
Using the first source / drain and the second source / drain of the fourth transistor to couple the fourth transistor in series between the source / drain of the third transistor and the second output node;
The gate of the fourth transistor is coupled to the second external control node
The imaging apparatus according to claim 21, wherein: A pixel array having a plurality of pixels organized in a plurality of rows and a plurality of columns, wherein each of the pixels is associated with a power input node that receives power to drive the pixels and light incident on the pixels A pixel array having a signal output node for outputting a signal to be output;
An imaging device comprising a power supply circuit coupled to each pixel of the pixel array,
The power supply circuit is
A power supply having a first node for supplying a first power signal and a second node for supplying a first control signal;
A plurality of taps, wherein the plurality of taps are coupled in parallel to the power source, and each of the plurality of taps includes:
A first output node coupled to the power source and receiving the first power signal from the first node;
A bypass circuit path having a power input node coupled to the first node, a control node coupled to the second node, and a second output node outputting a second power signal;
With
The imaging apparatus, wherein the first output node is coupled to the power input node of the pixel, and the second output node is coupled to the signal output node of the pixel. A processing device;
A processor-based system comprising an imaging device,
The processing device is
With a processor;
A memory coupled to the processor;
An I / O controller coupled to the processor;
The imaging device is
A control circuit coupled to the I / O controller;
A pixel array coupled to the control circuit and having a plurality of pixels organized in a plurality of rows and columns, each of the pixels receiving a power for driving the pixels; and A pixel array having a signal output node for outputting a signal related to light incident on the pixel;
A power source coupled to the control circuit and having a first node for supplying a power signal and a second node for supplying a first control signal;
With multiple taps,
The plurality of taps are connected in parallel to the power source, and each of the plurality of taps is
A first output node coupled to the first node;
A first transistor controllable by the first control signal;
In a processor based system comprising a second output node,
Coupling the first output node to the power input node of the pixel and coupling the second output node to the signal output node of the pixel;
Using the first source / drain and the second source / drain of the first transistor to couple the first transistor in series between the first node and the second output node;
The gate of the first transistor is coupled to the second node
A processor-based system characterized by that. A processing device;
A processor-based system comprising an imaging device,
The processing device is
With a processor;
A memory coupled to the processor;
An I / O controller coupled to the processor;
The imaging device is
A control circuit coupled to the I / O controller;
A pixel array coupled to the control circuit and having a plurality of pixels organized in a plurality of rows and columns, each of the pixels receiving a power for driving the pixels; and A pixel array having a signal output node for outputting a signal related to light incident on the pixel;
A power supply circuit coupled to each pixel of the pixel array,
The power supply circuit is
A power supply having a first node for supplying a first power signal and a second node for supplying a first control signal;
A plurality of taps each coupled to the power source;
Each of the taps
A first output node coupled to the power source for receiving the first power signal from the first node;
A bypass circuit path having a power input node coupled to the first node, a control node coupled to the second node, and a second output node outputting a second power signal;
With
A processor-based system, wherein the first output node is coupled to the power input node of the pixel and the second output node is coupled to the signal output node of the pixel. A processing device;
A processor-based system comprising an imaging device,
The processing device is
With a processor;
A memory coupled to the processor;
An I / O controller coupled to the processor;
The imaging device is
A control circuit coupled to the I / O controller;
A pixel array coupled to the control circuit and having a plurality of pixels organized in a plurality of rows and columns, each of the pixels receiving a power for driving the pixels; and A pixel array having a signal output node for outputting a signal related to light incident on the pixel;
A power supply circuit coupled to each pixel of the pixel array,
The power supply circuit is
With power supply;
In a processor-based system, each comprising a plurality of taps coupled to the power source,
Each of the taps provides a first bias current to the power input node of the pixel and a second bias current to the signal output node of the pixel. The power supply circuit according to claim 1, wherein the pixel includes a source follower transistor connected between the power input node and the signal output node. The power supply circuit according to claim 39, wherein the source follower transistor is connected to the signal output node via a row selection transistor.

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