JP4608229B2 - Organic EL drive circuit and organic EL display device using the same - Google Patents

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic EL drive circuit and an organic EL display device using the organic EL drive circuit. The present invention relates to an organic EL display device suitable for high-luminance color display in which white balance adjustment on a display screen by adjustment is easy or luminance unevenness can be reduced.

In an organic EL display panel of an organic EL display device mounted on a mobile phone, a PHS, a DVD player, a PDA (portable terminal device), etc., the number of column pins is 396 (132 × 3) terminal pins and row lines are 162. One having a plurality of terminal pins has been proposed, and column line and row line terminal pins tend to increase further.
The output stage of the current drive circuit of such an organic EL display panel is provided with a drive circuit of a current source corresponding to a terminal pin , for example , an output circuit using a current mirror circuit, regardless of whether it is an active matrix type or a simple matrix type. .

One of the problems with organic EL display devices is that when voltage driving is performed as in a liquid crystal display device, the luminance variation becomes large, and the display sensitivity is difficult because there is a difference in light emission sensitivity between R, G, and B. It is. For this purpose, current driving is performed. Even if current driving is performed, the ratio of the light emission efficiency to the driving currents of R, G, and B is different from, for example, about R: G: B = 6: 11: 10. Such luminous efficiency varies depending on the material of the organic EL element (hereinafter referred to as OEL element) to be used.
Therefore, in the current drive circuit for color display, it is necessary to adjust the luminance according to the material used for R, G, and B and to take white balance on the display screen. For this purpose, an adjustment circuit for adjusting the brightness corresponding to R, G, and B is provided.

By the way, a driving circuit for an OEL element that performs current driving of OEL elements arranged in a matrix and resets the anode and cathode of the OEL element to ground is known (Patent Document 1). Also, a technique for driving an OEL element with low power consumption using a DC-DC converter is known (Patent Document 2).
Japanese Patent Application Laid-Open No. 9-232074 JP 2001-143867 A

In a current drive circuit of an organic EL display device, a reference current is normally amplified to generate a drive current for an OEL element corresponding to each column terminal pin. Therefore, the adjustment of the drive current for achieving the white balance is performed by adjusting the respective reference currents corresponding to R, G, and B.
In order to adjust the reference current, the conventional current driving circuit is provided with a D / A conversion circuit of about 4 bits in the reference current generating circuit and corresponding to R, G, B, for example, in the range of 30 μA to 75 μA in increments of 5 μA. The reference currents of R, G, and B are adjusted by setting predetermined bit data at. However, various organic EL materials have been developed recently, and the range of luminance adjustment for white balance is coarse in the D / A conversion circuit of about 4 bits, and the adjustment dynamic range is in the range of about 4 bits. Is too small to support.

As the number of column lines increases, it is necessary to drive the column line terminal pins by a plurality of driver ICs. In addition, one driver IC drives many terminal pins. As a result, variation occurs in the current output characteristics of the drive circuit of the current source provided for the terminal pin, and the luminance unevenness of the organic EL display panel driven thereby becomes noticeable.
The object of the present invention is to solve such problems of the prior art, and to adjust the white balance accurately even if the adjustment dynamic range of each reference current value of R, G, B used for white balance adjustment is small. An organic EL driving circuit and an organic EL display device that can be used.
Another object of the present invention is to provide an organic EL driving circuit and an organic EL display device which can easily reduce luminance unevenness.

In order to achieve such an object, the organic EL drive circuit of the present invention and the configuration of the organic EL display device using the same are provided with a display period corresponding to a horizontal one-line scanning period and a reset corresponding to a horizontal scanning blanking period. In an organic EL driving circuit that current-drives an organic EL panel through a terminal pin in a display period in accordance with a first timing control signal having a predetermined frequency for dividing the period,
A timing signal generating circuit for generating a plurality of second timing control signals sequentially delayed by a predetermined time with respect to the first timing control signal; a plurality of second timing control signals; a first timing control signal; and predetermined data And selecting one of the plurality of second timing control signals according to the predetermined data and determining the leading edge (rising or falling edge) according to the selected second timing control signal, A reset pulse generation circuit for generating a reset pulse with a trailing edge (falling or rising edge) as a trailing edge of the first timing control signal , and a terminal pin connected to a predetermined bias line upon receiving the reset pulse Reset the charge of the OEL element of the organic EL panel connected to It comprise a switch circuit, the display period in accordance with the predetermined data is adjusted, in which the luminance of the organic EL panel is adjusted.

By the way, since the OEL element is driven to emit light by performing a constant voltage reset that is precharged to a predetermined constant voltage VZR, the drive waveform of the OEL element that is current-driven through each column terminal pin of the organic EL drive circuit is Like the drive current waveform for R shown in FIG. 3G, the peak current waveform (solid line) starts from this predetermined constant voltage VZR. In addition, the dotted line of FIG.3 (g) is a voltage waveform.
The constant voltage reset is performed in a reset period corresponding to a blanking period of horizontal scanning, and the display period at this time corresponds to a horizontal scanning period of one horizontal line. Therefore, the display period and the reset period are separated by a timing control pulse having a period (horizontal scanning frequency) corresponding to the display period + the reset period. FIG. 3 is an explanatory diagram of a drive waveform of a current for driving a terminal pin and various timing signals for generating the drive waveform.

Describing this, FIG. 3A shows a synchronous clock CLK that is the basis of the timing of each control signal, and FIG. 3B shows a count start pulse CSTP of a pixel counter. The count value of the pixel counter is shown in FIG. 3D shows the display start pulse DSTP, FIG. 3J shows the timing control pulse TP, FIG. 3E shows the reset pulse RSR for R, and FIG. The reset pulse RSG and FIG.
In the present invention, as shown in FIGS. 3 (e), 3 (h), and 3 (i), the reset periods of the reset pulses of R, G, and B are made different to display R, G, and B, respectively. Make the end of the period different.

In other words, according to the present invention, the end point of the display period of R, G, B is set to R, G, B by allowing the reset period to be adjusted by setting data from the outside corresponding to R, G, B. It adjusts corresponding to each and adjusts each brightness | luminance. Alternatively, it is possible to adjust the brightness corresponding to each terminal pin by making it possible to adjust the reset period corresponding to each terminal pin.
As a result, the reset period can be adjusted for the entire terminal pins of R, G, and B, and the white balance can be adjusted. Furthermore, the luminance unevenness can be reduced by adjusting the reset period of the selected terminal among the terminal pins corresponding to the luminance unevenness.
As a result, it is possible to easily realize an organic EL driving circuit and an organic EL display device that can adjust white balance or reduce luminance unevenness.

FIG. 1 is a block diagram centering on a reset circuit of a column driver of an organic EL panel of an embodiment to which an organic EL driving circuit of the present invention is applied, FIG. 2 is an explanatory diagram of its timing waveform, and FIG. It is explanatory drawing of the current waveform which current-drives a terminal pin, and the timing signal which generate | occur | produces this.
In FIG. 1, reference numeral 10 denotes a column IC driver (hereinafter referred to as a column driver) as an organic EL drive circuit in the organic EL panel. The column driver 10 includes a control circuit 1, an n-stage (n is an integer of 2 or more) shift register 2, reset pulse generation circuits 3R, 3G, 3B, D / A conversion circuits 4R, 4G, 4B, an output stage. Current sources 5R, 5G, and 5B, a resistor 6 and the like are included.

Each D / A conversion circuit 4R receives the display data DAT from the MPU 7 via the register 6, amplifies the reference drive current for R generated by the reference current generation circuit (not shown) by the display data value, and A drive current according to occasional display brightness is generated. Then, the output stage current source 5R is driven by each of the generated drive currents. Each output stage current source 5R is composed of a current mirror circuit composed of a pair of transistors, and the drive current is supplied to the organic EL through m column side output terminals XR1, XR2,... XRm (not shown) for R. It outputs to the anode of each OEL element 9 about R of a panel.
The output terminals XR1, XR2,... XRm of the R are further connected to switch circuits SWR1, SR2,. Is connected to the ground GND.

Since the D / A conversion circuits 4G and 4B and the output stage current sources 5G and 5B have the same configuration as the D / A conversion circuit 4R and the output stage current source 5R, description of their connection is omitted. Output terminals XG1, XG2,... XGm (not shown) connected to the output stage current sources 5G are connected to the anodes of the OEL elements 9 for G, and the output terminals XG1, XG2,. The switch circuits SWG1, SG2,... SGm (not shown) are connected to the ground GND via a constant voltage Zener diode DZG. Further, output terminals XB1, XB2 (not shown),... XBm (not shown) to which the output stage current sources 5B are connected are connected to the anodes of the respective OEL elements 9 for B, and the output terminals XB1, XB2,... XBm are connected to the ground GND via switch circuits SWB1, SB2 (not shown),... SBm (not shown) and a constant voltage Zener diode DZB, respectively.
Therefore, in the following, the configuration and relationship of the D / A conversion circuit 4R and the output stage current source 5R for R will be mainly described, and each of the D / A conversion circuits 4G and 4B and the output stage current sources 5G and 5B will be described. I will omit the composition and its relationship.

As shown in FIG. 1, the switch circuits SWR1, SWR2,... SWRm are reset switches provided corresponding to the output terminals XR1 to XRm for R, and reset each output terminal to the constant voltage VZR of the Zener diode DZR. Is. As shown in FIG. 1, each switch circuit is composed of, for example, a P-channel MOS transistor, and its gate is connected to a line 11, and a reset pulse RSR for R is sent from the reset pulse generating circuit 3R via this line 11. receive.
The source of each transistor is connected to each output terminal XR1 to XRm, and the drain of each transistor is connected to the ground GND via a Zener diode DZR. As a result, the anode side of the OEL element 9 is precharged to the constant voltage VZR of the Zener diode DZR during the reset period.

Similarly, as shown in FIG. 1, P-channel MOS transistors constituting switch circuits SWG1, SWG2,... For G are provided corresponding to the output terminals XG1, XG2,. The source of each transistor is connected to each output terminal XG1, XG2,..., And the drain of each transistor is connected to the ground GND via a Zener diode DZG. The gate of each transistor is connected to the line 12 and receives the reset pulse RSG from the reset pulse generating circuit 3G via the line 12.
Similarly, as shown in FIG. 1, P channel MOS transistors constituting switch circuits SWB1, SWB2,... SWBm for B are provided corresponding to the output terminals XB1, XB2,. The source of each transistor is connected to each output terminal XB1, XB2,..., And the drain of each transistor is connected to the ground GND via a Zener diode DZB. The gate of each transistor is connected to the line 13 and receives the reset pulse RSB from the reset pulse generating circuit 3B via the line 13.

Since the reset pulse generation circuits 3R, 3G, and 3B provided for R, G, and B respectively have the same configuration, the reset pulse generation circuit 3R will be described with respect to the selector 31 and the 2-input AND gate 32, respectively. It consists of a 3-bit register 33 and an inverter 34.
Shift register 4 receives timing control pulse TP from the control circuit 1, a clock CLK through an inverter 34, a falling timing of the clock CLK, the output waveform as shown in FIG. 2 (a) to each stage Are generated as a second timing control signal .
FIG. 2A illustrates a case where n is 4 to form a four-stage shift register, and the flip-flops at the respective stages are Q1 to Q4. The output signal of each stage of Q1 to Q4 is generated in response to the fall of the clock CLK input to each stage of the shift register 4, and Q2 to Q4 are delayed by one to several clocks CLK from the rise of the first stage Q1. It is output. The rising timing of the first stage Q1 is delayed by a period from the rising of the timing control pulse TP to the falling of the clock CLK synchronized therewith.
The selector 31 receives one of the output signals from the first stage to the last stage of the shift register 4 and the input signal (timing control pulse TP from the control circuit 1) to the first stage, and selects one of the input signals. The selection of the input signal of the selector 31 is performed according to a k-bit data value (k is an integer of 2 or more) set in the register 33. Here, the selected input signal is input to one of the two-input AND gate 32. An input signal (timing control pulse TP) of the shift register 4 is input to the other input of the AND gate 32.

  As a result, the output of the AND gate 32 generates a reset pulse RSR delayed by m clock CLK (m is an integer of 1 or more) from the first stage according to the data value set in the register 32. This reset pulse RSR has the rising edge (leading edge) of the rising edge (leading edge) of the timing control pulse TP or the selected Q1-Q4 output rising edge (leading edge), and the falling edge (rear edge) is timed. The reset pulse RSR is as shown in FIG. 3E, which is the falling edge (rear edge) of the control pulse TP. The reset pulse RSR is sent to the gate of the P-channel MOS transistor via the inverter 35 and applied to the switch circuits SWR1, SWR2,. Note that the AND gate 32 and the inverter 35 may be composed of NAND gates.

Here, when the shift register 4 is n = 4 and has a four-stage configuration, and k = 3, the 3-bit data set in the register 33 is a value from 0 to 4, and the value corresponds to the number of output stages. is doing. Therefore, when the 3-bit data set in the register 33 of the reset pulse generating circuit 3R is “011” and “3”, the output of Q3 of the shift register 4 is selected as shown in FIG. As shown in FIG. 2B , the output of the AND gate 32 is delayed by two clocks from the output of the first stage Q1 (see FIG. 2A) .
As a result, a reset pulse RSR as shown in FIG. 3 (e) is generated from the reset pulse generating circuit 3R. In the case of the reset pulse RSG in FIG. 3H, the 3-bit data set in the register 33 of the reset pulse generating circuit 3G is “010” and “2”, and the output of Q2 of the shift register 4 is Selected. In the case of the reset pulse RSB in FIG. 3I, the 3-bit data set in the register 33 of the reset pulse generation circuit 3B is “001” and “1”, and the output of Q1 of the shift register 4 is Selected. In the case of this figure, the output of each stage of the shift register 4 is assumed to coincide with the falling timing of the clock CLK.

In this way, the reset pulse corresponding to R, G, B is synchronized with the clock CLK according to the data set in the 3-bit register 33 of each of the reset pulse generating circuits 3R, 3G, 3B at the fall timing. Generated as a rising pulse. Moreover, this pulse is a pulse that falls at the fall of the timing control pulse TP. As a result, the end timing of the display period can be adjusted to correspond to R, G, and B. Thereby, the display period can be adjusted corresponding to R, G, and B, and the respective luminance adjustments can be made.
When the value of the register 33 is “0”, each reset pulse generation circuit 3R, 3G, 3B outputs the timing control pulse TP as a reset pulse. Note that the rise of the timing control pulse TP coincides with the rise timing, not the fall of the clock CLK. However, if the pulse in FIG. 3H is a timing control pulse TP, the timing control pulse TP can be generated in accordance with the falling timing of the clock CLK.

  These reset pulses RSR, RSG, RSB are pulses having a period (horizontal scanning frequency) corresponding to a predetermined display period + reset period, and are at a HIGH level (hereinafter, “H”, “H” significant). In response to this, the reset period RT starts as indicated by the reset pulse RSR in FIG. Then, the display period D starts at the rise of the display start pulse DSTP shown in FIG. 3D, and the reset period ends in synchronization with this. Therefore, the timing control pulse TP falls on the basis of the time when the reset period ends. At the falling timing, counting is started by a counter or the like, and the timing control pulse TP becomes the LOW level (hereinafter referred to as “L”) for a predetermined period. The next rising timing of the timing control pulse TP is determined according to the counting up of the counter or the like.

As a result, for R, for example, a current driving waveform (see solid line) for driving the OEL element 9 as shown in FIG. 3G is generated in response to the peak generation pulse Pp shown in FIG. It will be.
By the way, during the reset period in which the reset pulses RSR, RSG, RSB shown in FIGS. 3E, 3H, and 3I are “H”, various data such as display data are set and the organic EL display element is set. A constant voltage reset of the anode voltage of 9 is performed. In particular, when these reset signals are “H”, the data is set in the display data register such as the register 6 provided for each terminal pin, so that there are 132 terminal pins for R, G, B. In this case, according to the value of the pixel counter in FIG. 3C, the “H” period of each reset pulse RSR, RSG, RSB requires a count of 133 clocks or more.

In the current drive waveform of R shown in FIG. 3G, the rising start period when the reset pulse RSR is “H” corresponds to the display end period. The same applies to the G and B current drive waveforms.
Therefore, by setting the rising timing of each reset pulse RSR, RSG, RSG to correspond to R, G, B, the length of the display period can be changed to correspond to R, G, B. Therefore, the rising timing of each reset pulse RSR, RSG, RSB is set by data from the outside, thereby determining the length of each display period corresponding to R, G, B, and adjusting the luminance accordingly. As a result, the white balance can be adjusted.

  Data set in each register 33 of the reset pulse generating circuits 3R, 3G, 3B is set from the MPU 7 corresponding to R, G, B. Therefore, the rising positions of these reset pulses RSR, RSG, RSB can be adjusted by data set from the MPU 7. This data value is stored in, for example, a nonvolatile memory inside the MPU, and is set in each register 33 when the power is turned on. These setting data are stored in a nonvolatile memory or the like according to the input data. In particular, the input to the MPU 7 and the writing of data to the nonvolatile memory may be performed by inputting from the keyboard in correspondence with R, G, and B, respectively, in the test stage of product shipment, and the white balance adjustment is performed.

In this embodiment, reset pulse generating circuits 3R, 3G, 3B are provided for R, G, B, but the reset pulse generating circuits are output terminals XR1, XR2,... XRm, output terminals XG1, XG2,. XGm and output terminals XB1, XB2,... Can be provided corresponding to the respective output terminals. As a result, the brightness can be adjusted for each terminal pin.
As a result, the data from the MPU 7 is set in the register 33 of the reset pulse generating circuit at the position of the terminal pin where the luminance unevenness is reduced according to the luminance unevenness. As a result, the luminance unevenness can be reduced by adjusting the luminance of the vertical line corresponding to the terminal pin.
Note that the data set in the register 33 may be set from the outside of the reset pulse generation circuit, and is not limited to the MPU, but may be a controller or the like.

As described above, in the embodiment, the second timing control signal delayed by a predetermined period selected by the selector 31 with respect to the timing control pulse TP is generated by the delay circuit (shift register). However, a general timing signal generation circuit can be used for the second timing control signal delayed for the predetermined period without using a delay circuit.
Of course, each reset pulse RSR, RSG, RSB in the embodiment may be generated not as “H” but as a period of “L” by reversing the logic level. In the embodiment, G and B are provided with independent reset pulse generation circuits, respectively, and generate reset pulses. However, at present, there is little difference in light emission efficiency between G and B light emitting materials. Therefore, these can be controlled by this one circuit as one identical circuit.
Further, in the embodiment, precharge voltages (constant voltages for performing constant voltage reset) are respectively set for R, G, and B independently by the voltages of the Zener diodes DZR, DZG, and DZB. A voltage may be used, and one Zener diode or a constant voltage circuit may be used. Furthermore, a Zener diode may be provided corresponding to each output terminal. Furthermore, the reset may be performed with respect to the ground GND instead of the constant voltage.

FIG. 1 is a block diagram centering on a reset circuit of a column driver of an organic EL panel of an embodiment to which the organic EL driving circuit of the present invention is applied. FIG. 2 is an explanatory diagram of the timing waveform. FIG. 3 is an explanatory diagram of a current waveform for driving a terminal pin and a timing signal for generating the current waveform.

Explanation of symbols

1 ... Control circuit, 4 ... Shift register,
3R, 3G, 3B ... reset pulse generation circuit,
4R, 4G, 4B ... D / A conversion circuit,
5R, 5G, 5B ... output stage current source, 6 ... register,
7 ... MPU, 9 ... Organic EL element,
SWR1, SWR2 ... switch circuit,
10 ... Column IC driver,
31 ... selector, 32 ... 2-input AND gate,
33: Register, 34, 35: Inverter.

Claims (16)

In response to a first timing control signal having a predetermined frequency for separating a display period corresponding to a scanning period of one horizontal line and a reset period corresponding to a blanking period of horizontal scanning, the terminal pin is connected to the organic EL panel in the display period. A timing signal generation circuit that generates a plurality of second timing control signals that are sequentially delayed by a predetermined time with respect to the first timing control signal;
One of the plurality of second timing control signals is selected according to predetermined data, a leading edge is determined according to the selected second timing control signal, and a trailing edge is defined as the first timing control signal. A reset pulse generation circuit for generating a reset pulse as a trailing edge of
A switch circuit for receiving the reset pulse and connecting the terminal pin to a predetermined bias line to reset the charge of the OEL element of the organic EL panel connected to the terminal pin;
An organic EL driving circuit in which the display period is adjusted according to the predetermined data, and the luminance of the organic EL panel is adjusted.   2. The organic EL drive circuit according to claim 1, wherein the reset pulse generation circuit generates the reset pulse having a leading edge of the selected second timing control signal as a leading edge.   The timing signal generation circuit is a delay circuit that receives the first timing control signal and sequentially delays the predetermined time period to generate a plurality of second timing control signals, and has a register. The organic EL drive circuit according to claim 2, wherein is set in the register. The reset pulse generating circuit includes the register, the organic EL driving circuit according to claim 3, wherein said predetermined data in said register from the outside of the reset pulse generating circuit is set. The organic EL panel includes a plurality of the OEL elements corresponding to display colors of R, G, and B, the reset pulse generation circuit and the switch circuit are provided corresponding to R, G, and B, The organic EL drive circuit according to claim 4, wherein the OEL elements corresponding to G and B are respectively reset.   Each of the switch circuits corresponding to R, G, and B is turned on in response to the corresponding reset pulse, and the terminal pin is connected to the anode side of each of the OEL elements corresponding to R, G, and B. The organic EL drive circuit according to claim 5, wherein the organic EL drive circuit is connected to the predetermined bias line or a bias line corresponding to R, G, and B via a via.   The organic EL drive circuit according to claim 6, wherein the reset pulse generation circuit is provided corresponding to each of the terminal pins, and the predetermined data is set corresponding to the terminal pins.   The leading edge is a rising edge, the trailing edge is a falling edge, the delay circuit is configured by a shift register, and the reset pulse generation circuit includes the register, a selector, and an AND circuit or a NAND circuit. The selector receives the plurality of second timing control signals and the predetermined data from the register and selects one of the plurality of second timing control signals, and the AND circuit or the NAND circuit 8. The organic EL drive circuit according to claim 7, wherein the reset pulse is generated in response to the first timing control signal and the second timing control signal output from the selector. Furthermore, a D / A conversion circuit provided for the terminal pin,
9. The organic EL drive circuit according to claim 8, further comprising: a current source corresponding to the terminal pin that is current driven by a current having a current value converted by the D / A conversion circuit and that drives the terminal pin. In response to a first timing control signal having a predetermined frequency for separating a display period corresponding to a scanning period of one horizontal line and a reset period corresponding to a blanking period of horizontal scanning, the terminal pin is connected to the organic EL panel in the display period. A timing signal generating circuit for generating a plurality of second timing control signals that are sequentially delayed by a predetermined time with respect to the first timing control signal;
A leading edge of the second timing control signal selected by selecting one of the plurality of second timing control signals according to predetermined data is used as a leading edge, and a trailing edge of the second timing control signal is selected. A reset pulse generation circuit for generating a reset pulse as a trailing edge ;
A switch circuit that receives the reset pulse and connects the terminal pin to a predetermined bias line to reset the charge of the OEL element of the organic EL panel connected to the terminal pin;
An organic EL display device in which the display period is determined according to the predetermined data and the luminance of the organic EL panel is adjusted.   The timing signal generation circuit is a delay circuit that receives the first timing control signal and sequentially delays the predetermined time to generate a plurality of second timing control signals, and has a register. 11. The organic EL display device according to claim 10, wherein is set in the register. The reset pulse generating circuit includes the register, the organic EL display device according to claim 11, wherein said predetermined data is set from the outside of the reset pulse generating circuit to said register. The organic EL panel includes a plurality of the OEL elements corresponding to display colors of R, G, and B, and the reset pulse generation circuit and the switch circuit are provided corresponding to R, G, and B, The organic EL display device according to claim 12, wherein the OEL elements corresponding to G and B are reset.   The leading edge is a rising edge, the trailing edge is a falling edge, and each of the switch circuits corresponding to R, G, B is turned on in response to the corresponding reset pulse. 14. The organic EL display device according to claim 13, wherein an anode side of each of the OEL elements corresponding to G and B is connected to the predetermined bias line or a bias line corresponding to R, G, and B via the terminal pin. In response to a timing control signal having a predetermined frequency for separating a display period corresponding to a scanning period of one horizontal line and a reset period corresponding to a blanking period of horizontal scanning, the organic EL panel is connected via the terminal pin in the display period. In an organic EL drive circuit that is current driven,
A timing signal generation circuit for generating a plurality of timing signals sequentially delayed by a predetermined time with respect to a leading edge of the timing control signal;
A reset that selects one of the plurality of timing signals according to predetermined data, determines a leading edge according to the selected timing signal, and generates a reset pulse with a trailing edge as the trailing edge of the timing control signal A pulse generation circuit;
A switch circuit for receiving the reset pulse and connecting the terminal pin to a predetermined bias line to reset the charge of the OEL element of the organic EL panel connected to the terminal pin;
An organic EL driving circuit in which the display period is adjusted according to the predetermined data, and the luminance of the organic EL panel is adjusted.   The organic EL drive circuit according to claim 15, wherein the timing signal is a signal generated with a delay from the timing control signal.

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