JP4603130B2 - Method and display device for automatic phase adjustment of sampling clock - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of automatically adjusting a sampling clock phase of an input video signal to an optimum value, and a display device having an automatic adjustment function of a sampling clock phase.
[0002]
[Prior art]
In a personal computer, WS, etc., the video signal level changes at a constant cycle shorter than the horizontal sync signal (hereinafter referred to as dot cycle), and when displaying video on a matrix display device such as a liquid crystal display device or in memory In order to perform write signal processing, it is necessary to sample the video signal with a clock that coincides with the dot cycle (hereinafter referred to as dot clock), and if the phase of the dot clock deviates from the optimum value, the display image is blurred. Occurs, and the image quality deteriorates. Therefore, it is necessary to keep the dot clock phase at an optimum value.
[0003]
As an example of the prior art for automatically adjusting the phase of the dot clock, the processing contents of the automatic phase adjustment of the dot clock reproducing device disclosed in Japanese Patent Laid-Open No. 11-282399 will be described with reference to FIG. 3 includes block A and block B. In block A, phase data is acquired by sampling while changing the phase of the dot clock, and in block B, an optimum phase is obtained from the acquired phase data by calculation. .
[0004]
In block A, the clock phase is set to p0 (step 1), and r (p0) is stored as the phase data at that time (step 2). Next, returning to step 1, the clock phase is shifted by a minute amount δ, and the phase data r (p1) = r (p0 + δ) at that time is stored (step 2). The above operation is repeated n times. The clock phase pn when it is repeated n times is p0 + n · δ, and the phase data at that time is represented by r (pn).
[0005]
The block B is a part for executing the process of calculating the optimum phase of the clock from the obtained phase data, but the description thereof is omitted because it is not directly related to the present invention.
[0006]
In the above processing, for example, when the clock phase is changed to p0, p1,..., P32, when p16 is the optimum phase, the blur of the display screen increases as the clock phase moves away from p16. In other words, when adjusting the clock phase, if the clock phase is changed from p0 to p32, the display screen is in an optimal state (the clock phase is the optimal value) from the blurred state (the clock phase is shifted from the optimal value). ), And the camera returns to the bleeding state again.
[0007]
[Problems to be solved by the invention]
As described above, in the conventional technique as described above, blurring occurs on the display screen during the sampling clock phase adjustment, and the deterioration of the image quality is recognized by the user. Therefore, the sampling clock phase is adjusted during use of the display device. There is a problem that adjustment is difficult.
[0008]
An object of the present invention is to enable automatic adjustment of the phase of a sampling clock to an optimal value without causing deterioration in image quality such as blurring on the display screen during use of the display device.
[0009]
[Means for Solving the Problems]
The above-described problems are based on an A / D converter that samples an input video signal according to a sampling clock and converts it into a digital image signal, a frame memory in which the digital image signal is written, and a digital image signal read from the frame memory. In a method for automatically adjusting a sampling clock phase in a display device including display means for displaying an image, a current value of the phase of the sampling clock is stored as a first phase value, and then a digital image signal is written to the frame memory The phase of the sampling clock is set to the second phase value, a predetermined number of times the input video signal is sampled with the set sampling clock, and the value of the digital image signal obtained by the sampling The set sampling clock and Obtaining phase data representing a phase difference between the input video signal, a step of sampling the input video signal by returning the phase of the sampling clock to the first phase value, and a step of sampling the digital video signal to the frame memory A process of resuming writing is executed a predetermined number of times while the second phase value is incremented by a predetermined value, and the phase value of the sampling clock is converted into phase data for the predetermined number of times obtained by the process. This is solved by an automatic phase adjustment method for a sampling clock, which is characterized in that the optimum phase value is determined based on the sampling clock.
[0010]
The phase data is a value obtained by accumulating the absolute value of the difference between the values of two adjacent digital image signals for the certain number of digital image signals, and the second value of each of the two phase data for which the accumulated value is minimized. An intermediate value of the phase values can be set as the optimum phase value.
[0011]
The phase data is defined as the number of horizontal scanning lines in which the digital image signals at the corresponding pixel positions all match between two frames preceding and following in time, and the second phase of the phase data having the maximum number. The value can be the optimum phase value.
[0012]
The above-described problems also include an A / D converter that samples an input video signal according to a sampling clock and converts it into a digital image signal, a frame memory in which the digital image signal is written, and a digital image read from the frame memory In a display device including display means for displaying video according to a signal,
After storing the current value of the phase of the sampling clock as the first phase value, stopping writing of the digital image signal to the frame memory, setting the phase of the sampling clock to the second phase value, Sampling a predetermined number of input video signals with a set sampling clock, and phase data representing a phase difference between the set sampling clock and the input video signal from the value of the digital image signal obtained by the sampling. A process comprising the steps of: obtaining a sampling clock by returning the phase of the sampling clock to the first phase value; and resuming writing of the digital image signal to the frame memory. The sample is executed a predetermined number of times while incrementing the phase value of Solved by a display device comprising a sampling clock automatic phase adjusting means for setting a phase value of a clock to an optimum phase value determined based on a predetermined number of phase data obtained by the processing Is done.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a configuration of an embodiment of a display device of the present invention having a sampling clock phase automatic adjustment function. In the figure, 1 is an A / D converter that samples an input video signal and converts it into digital image data, 2 is a frame memory for storing one frame of digital image data, and 3 is an image data to frame memory 2 A frame memory access circuit that performs writing and reading, 4 is a PLL circuit that generates a sampling clock from a synchronization signal supplied from an input video signal source (not shown), and 5 is a controller that controls the frame memory access circuit 3 to write image data. And a controller for controlling the start and stop of reading and adjusting the phase of the sampling clock by controlling the PLL circuit 4, and 6 is a memory for storing the current value of the phase of the sampling clock at the start of the sampling phase adjustment. . The digital image data read from the frame memory 2 is processed by a video processing circuit, and a video is displayed on a display unit (not shown).
[0014]
An automatic adjustment operation of the sampling clock phase in the display device having the above configuration will be described with reference to the flowchart of FIG.
[0015]
First, the current value px of the phase of the sampling clock before adjustment is stored in the memory 7 (step S1), and n is set to 0 (step S2).
[0016]
The frame memory access circuit 3 is controlled to stop writing digital image data to the frame memory 2 (step S3). Thereby, the update of the display screen is stopped.
[0017]
The PLL circuit 4 is controlled, the phase of the sampling clock is set to pn (step S4), and the phase data rn at that time is fetched (step S5). Note that pn is equal to p0 + n · δ as described above.
[0018]
The PLL circuit 4 is controlled again, and the phase of the sampling clock is returned to the pre-adjustment value px stored in the memory 7 (step S6), the frame memory access circuit 3 is controlled, and the digital image data for the frame memory 2 is controlled. Writing is resumed (step S7).
[0019]
The controller 5 waits until two vertical synchronizing signals are counted, and waits for the screen to be rewritten with the data read by the sampling clock of the phase value before adjustment. Thereby, the screen is updated again in the state before the clock adjustment is started (step S8).
[0020]
1 is added to the value of n (step S9), and the process returns to step S3. In step S4, the value of the clock phase is increased by a minute amount δ, and steps S5 to S9 are executed again. The above processing is repeated until n becomes equal to the predetermined value N and the phase data has been captured.
[0021]
When the N pieces of phase data rn are taken in by the above processing, the optimum phase value of the sampling clock is obtained from these values (step S10).
[0022]
The phase data rn is data representing the phase relationship between the sampling clock signal and the input video signal, and can be obtained from the read sample. As the phase data rn, as described in JP-A-11-282399, a value obtained by accumulating the absolute value of the difference between two adjacent samples over a predetermined number of samples, or JP-A-7-219485. As described in the publication, it is possible to use the number of horizontal scanning lines in which samples at corresponding pixel positions all match between two frames that are temporally changed.
[0023]
In the example described in Japanese Patent Application Laid-Open No. 11-282399, when the edge of the input video signal and the edge of the sampling clock coincide with each other (phase difference is 0 degree), sampling is not performed correctly and the accumulated value is minimized. Therefore, an intermediate value between the phase values of the two phase data having a minimum accumulated value can be set as the optimum phase. In the example described in Japanese Patent Laid-Open No. 7-219485, the phase value of the phase data that maximizes the number of horizontal scanning lines in which the samples at the corresponding pixel positions all match can be set as the optimum phase.
[0024]
As described above, in the present embodiment, the update of the screen display is stopped for one frame period, the phase data is captured during that period, and then the update of the screen display is restarted to display one or more frames. Stop updating the screen display again and capture another phase data. By repeating this process, all the phase data necessary for determining the optimum phase can be acquired. While the phase data is being captured, the screen display update is stopped, but since this is a short period of one frame period, almost no deterioration in image quality is recognized. Accordingly, the phase of the sampling clock can be automatically adjusted during use of the display device.
[0025]
【The invention's effect】
According to the first aspect of the present invention, the phase of the sampling clock can be automatically adjusted to an optimum value without causing image quality deterioration such as blurring on the display screen during use of the display device.
[0026]
According to the second aspect of the present invention, the optimum phase can be determined from the accumulated value of the difference between adjacent samples of the input video signal.
[0027]
According to the third aspect of the present invention, the optimum phase can be determined based on the number of horizontal scanning lines in which the digital image signals at the corresponding pixel positions all match between two frames that are temporally changed.
[0028]
According to the fourth aspect of the present invention, there is provided a display device capable of automatically adjusting the phase of the sampling clock to an optimum value without causing deterioration of image quality such as blurring on the display screen during use. .
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an embodiment of a display device of the present invention having a sampling clock phase automatic adjustment function.
FIG. 2 is a flowchart illustrating an operation of automatic sampling clock phase adjustment in the display device of FIG.
FIG. 3 is a flowchart for explaining the operation of conventional sampling clock phase automatic adjustment;
[Explanation of symbols]
1 A / D converter, 2 frame memory, 3 frame memory access circuit, 4 PLL circuit, 5 controller, 6 memory.

Claims (4)

An A / D converter that samples an input video signal according to a sampling clock and converts it to a digital image signal, a frame memory in which the digital image signal is written, and a video that is displayed according to the digital image signal read from the frame memory In an automatic phase adjustment method of a sampling clock in a display device including display means,
Storing the current value of the phase of the sampling clock as a first phase value ;
Stopping writing digital image signals to the frame memory;
Setting the phase of the sampling clock to a second phase value, and sampling a certain number of input video signals with the set sampling clock;
Obtaining phase data representing the phase relationship between the set sampling clock and the input video signal from the value of the digital image signal obtained by the sampling;
Sampling the input video signal by returning the phase of the sampling clock to the first phase value;
Resuming the writing of the digital image signal to the frame memory and updating the display screen, and executing the process a predetermined number of times while incrementing the second phase value by a predetermined value to obtain the phase value of the sampling clock the automatic phase adjusting method of sampling clock and setting the optimum phase value is determined based on the phase data of a predetermined number of times obtained by the process.   The phase data is a value obtained by accumulating the absolute value of the difference between two adjacent digital image signals with respect to the certain number of digital image signals, and the second value of each of the two phase data that minimizes the accumulated value. The method according to claim 1, wherein an intermediate value of the phase values is set as an optimum phase value.   The phase data is the number of horizontal scanning lines in which the digital image signals corresponding to the corresponding pixel positions all match between two frames preceding and following in time, and the second phase data having the maximum number is the second data. The method according to claim 1, wherein the phase value is an optimum phase value. An A / D converter that samples an input video signal according to a sampling clock and converts it to a digital image signal, a frame memory in which the digital image signal is written, and a video that is displayed according to the digital image signal read from the frame memory In a display device including display means,
Storing the current value of the phase of the sampling clock as a first phase value ;
Stopping writing digital image signals to the frame memory;
Setting the phase of the sampling clock to a second phase value, and sampling a certain number of input video signals with the set sampling clock;
Obtaining phase data representing the phase relationship between the set sampling clock and the input video signal from the value of the digital image signal obtained by the sampling;
Sampling the input video signal by returning the phase of the sampling clock to the first phase value;
Resuming the writing of the digital image signal to the frame memory and updating the display screen, and executing the process a predetermined number of times while incrementing the second phase value by a predetermined value to obtain the phase value of the sampling clock and it sets the optimum phase value is determined based on the phase data of a predetermined number of times obtained by the processing, display device characterized by having an automatic phase adjusting means of the sampling clock.

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