JP4589253B2 - Differential output divider - Google Patents

Description

  The present invention relates to a technology of a frequency divider circuit for differential two-phase output using a COMS inverter.

  In recent years, circuits and configurations aiming at low power consumption operation are important technologies in wireless communication terminals and general AV equipment. A configuration employing a circuit using a CMOS inverter is an effective means for reducing power consumption. An inverter that allows current to flow only when a signal transitions can easily reduce current compared to a type that uses a constant current source that constantly flows current (a general differential pair circuit shown in FIG. 4A). On the other hand, the differential pair type can always easily extract a differential output whose phase is inverted by 180 degrees, whereas the inverter type shown in FIG. 4B is based on single-phase operation. Requires the addition of a circuit such as adding one stage of inverter or cross-coupling the output shown in FIG. 5 in order to eliminate the delay (Td) of the inverter. However, as shown in the time chart of the same figure, there is no problem if the current values i1 and i2 flowing through the two inverters change the same, but the output signal is distorted because the current change differs depending on manufacturing variations. Problems also arise.

Next, in Patent Document 1, an exclusive OR circuit is used to generate a division ratio switching signal of a general two-mode frequency dividing circuit.
In Patent Document 2, an exclusive OR circuit can create a clock having a double frequency using two signals having a phase shift of 90 degrees (exclusive to the added flip-flop circuit (FF circuit)). It is characterized by an OR circuit (EXOR circuit). Therefore, it is different from the configuration in which the output between the differential signals of the present invention is input to the exclusive OR circuit. Specifically, the flip-flop circuits 11 and 12 always shift the signal transition time of the output waveform by ¼ period (half period of the original input clock) by using the flip-flop circuit having the reverse trigger polarity. For example, a flip-flop circuit having the same trigger polarity can be used to invert the input clock to one side, but this also changes the trigger polarity of the flip-flop circuit in order to shift the output by a quarter period. There is nothing else.

Further, in Patent Document 3, the output of the exclusive OR circuit is simply for creating a new signal from two inputs.
Japanese Patent Application Laid-Open No. 2005-505979 JP-A-10-28048 Japanese Utility Model Publication No. 7-38943

However, these configurations have problems such as a phase difference corresponding to an inverter delay between differential signals and waveform distortion due to a delay suppression circuit.
In Patent Documents 1 and 2 and Patent Document 3, when output as a differential frequency divider, waveform transition cannot occur at the same timing.

  In addition, when the output of the flip-flop circuit is stochastically indeterminate, the differential output signal is in-phase using an exclusive OR circuit or an AND circuit or a NAND gate circuit to avoid this. This is not a configuration in which an operating state is detected and the outputs of both counters are set to opposite values (1 and 0) and a signal is applied to the reset input.

  The present invention has been made in view of the above circumstances, and uses two flip-flop circuits having the same configuration, divides each by a common clock, and outputs clocks inverted by 180 degrees from each other (one Single-phase output from the flip-flop circuit). Further, the common-phase state is detected by a simple logic circuit using two-phase outputs and is forcibly initialized. An object of the present invention is to provide a differential output frequency dividing circuit that does not generate a delay difference between differential signals.

  A frequency dividing circuit that divides and outputs a clock signal according to one aspect of the present invention is provided with a setting input terminal for forcibly fixing the signal level of the output signal, and the signal level is input to the setting input terminal. Thus, the first divider circuit forcibly fixing the output signal and the input signal having the same signal level as the setting input terminal of the first divider circuit are forcibly different from the output signal. The output signal is input from the second frequency divider circuit fixed to the signal level, the first frequency divider circuit, and the second frequency divider circuit, the signal levels of the output signals are compared, and are the same or different And a common-mode detection circuit that outputs to the setting input terminal.

Preferably, the in-phase detection circuit may be constituted by an exclusive OR circuit.
A frequency dividing circuit that divides and outputs a clock signal according to another aspect of the present invention is provided with a setting input terminal for forcibly fixing the signal level of the output signal, and the signal level is input to the setting input terminal. Thus, the first divider circuit forcibly fixing the output signal and the input signal having the same signal level as the setting input terminal of the first divider circuit are forcibly different from the output signal. The output signal is input from the second frequency divider circuit fixed to the signal level, the first frequency divider circuit, and the second frequency divider circuit, the signal levels of the output signals are compared, and are the same or different The common-mode detection circuit that determines whether or not to output to the setting input terminal is disposed on the COMS circuit board.

Preferably, the in-phase detection circuit may be constituted by an exclusive OR circuit.
With the above configuration, conventionally, after adding an inverter to create a negative-phase signal, a delay adjustment circuit that cancels the delay caused by this inverter is added, and the potential of the node inside the flip-flop circuit at the start of circuit operation (Random value) prevents the occurrence of a malfunction in which the initial value becomes the same value between two flip-flop circuits, resulting in an in-phase operation instead of a differential operation. In the above configuration, two flip-flop circuits with the same configuration are used so that a delay between differential signals does not occur, and a malfunction mode (a state where the two flip-flop circuits are in phase) is detected by a simple detection circuit. Thus, it can be forcibly returned to normal operation.

  According to the present invention, when the clock is divided on the CMOS, it can be forcibly returned to the normal operation even if it is in an indefinite state when the power is turned on.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Principle explanation)
FIG. 1 is a diagram showing the principle of the present invention. The configuration includes a first flip-flop circuit 1, a second flip-flop circuit 2, and an in-phase detection circuit 3. The first flip-flop circuit 1 is a circuit that includes a clock input terminal and divides a clock signal by a configuration in which a feeder back is applied from the Q_B terminal to the D terminal. Further, a CLR terminal is provided as a reset terminal. The second flip-flop circuit 2 includes a clock input terminal and divides the frequency by a configuration in which a feeder back is applied from the Q_B terminal to the D terminal. Further, a SET terminal is provided as a reset terminal. In the example of FIG. 1, when a low level signal enters the CLR terminal, the first flip-flop circuit 1 is subjected to CLR, so that the inverted output Q_B is at a high level.

  In the second flip-flop circuit 2, since the SET terminal receives the same low level signal at the same timing and the SET is applied, the inverted output Q_B is forced to the low level. In both the first flip-flop circuit 1 and the second flip-flop circuit 2, the reset function does not work for a high level signal input, and the flip-flop circuit performs a normal operation (in this case, a frequency dividing operation).

  In other words, the frequency dividing circuit that divides and outputs the clock signal is provided with setting input terminals SET and CLR for forcibly fixing the signal level of the output signal, and the output signal of the in-phase detector 3 is input to the setting input terminal. Thus, a first flip-flop circuit 1 (first frequency divider circuit) is provided in which the output signal is forcibly fixed (CLR).

  Then, by inputting the same signal level as the setting input terminal of the first flip-flop circuit 1, the second flip-flop is forcibly fixed (SET) with the reverse logic to the output signal of the first flip-flop circuit 1. A circuit 2 (second frequency dividing circuit) is provided. An output signal is input from the first frequency divider circuit and the second frequency divider circuit, the signal levels of the output signals are compared, a determination is made as to whether they are the same or different, and an in-phase detection circuit 3 that outputs to each setting input terminal It has.

Example 1
FIG. 2 is a diagram showing Example 1 of the present invention. The configuration includes a first flip-flop circuit 1, a second flip-flop circuit 1, and an exclusive OR circuit 4. The first flip-flop circuit 1 is a circuit that includes a clock input terminal and divides the frequency by a configuration in which a feedback is applied from the Q_B terminal to the D terminal. Furthermore, a CLR terminal is provided. The second flip-flop circuit 2 includes a clock input terminal and divides the frequency by a configuration in which a feeder back is applied from the Q_B terminal to the D terminal. Furthermore, a SET terminal is provided. When a low level signal enters the CLR terminal, the first flip-flop circuit 1 is subjected to CLR, so that the inverted output Q_B is fixed to the high level. In the second flip-flop circuit 2, since the SET terminal receives the same low level signal at the same timing and the SET is applied, the inverted output Q_B is forcibly fixed at the low level. In both the first flip-flop circuit 1 and the second flip-flop circuit 2, the reset function does not work for a high level signal input, and the flip-flop circuit performs a normal operation (in this case, a frequency dividing operation).

  In other words, the frequency dividing circuit that divides and outputs the clock signal is provided with setting input terminals SET and CLR for forcibly fixing the signal level of the output signal, and the output signal of the in-phase detector 3 is input to the setting input terminal. Thus, a first flip-flop circuit 1 (first frequency divider circuit) is provided in which the output signal is forcibly fixed (CLR).

  Then, by inputting the same signal as the setting input terminal of the first flip-flop circuit 1 (first divider circuit), the signal is forcibly fixed (SET) with the reverse logic of the output signal of the first flip-flop circuit 1. A second flip-flop circuit 2 (second frequency divider circuit). The output signal is input from the first divider circuit and the second divider circuit, the signal level of the output signal is compared, it is judged whether they are the same or different, and exclusive as a common-mode detection circuit that outputs to each setting input terminal This is a differential frequency divider circuit using a logical OR circuit (EXOR circuit).

The time chart shown in FIG. 3 will be described. When the state of the circuit is indefinite, the in-phase is detected regardless of the clock CLK within the range indicated by the broken-line circle. As a result, an output signal is output by the logical operation of the exclusive OR circuit shown in the table. As a result, the signals input to the setting input terminals of the first flip-flop circuit 1 and the second flip-flop circuit 2 forcibly reset each flip-flop circuit, and the output signals OUT, OUT_B is output. If there is no forced reset, an output in phase with the OUT signal is output from OUT_B like the output signal OUT_B in parentheses in the figure, and it does not operate as a differential frequency divider.
(Example 2)
In addition to the exclusive OR circuit, an AND circuit, a NAND circuit, or the like may be used as long as the in-phase can be detected. The operations of the first flip-flop circuit 1 and the second flip-flop circuit 2 are the same as those in the first embodiment.

The configurations described in the first and second embodiments are effective circuits when handling high-frequency signals of 10 GHz or higher.
The present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the gist of the present invention.

It is a figure which shows a principle. 1 is a diagram illustrating a circuit of Example 1. FIG. It is a figure which shows the time chart of Example 1, and the logic of an exclusive OR circuit. 4A is a diagram showing a conventional differential circuit, and 4B is a differential circuit using a conventional inverter. It is a differential circuit when performing conventional cross coupling.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st flip-flop circuit 2 2nd flip-flop circuit 3 In-phase detection circuit 4 Exclusive OR circuit

Claims (4)

A frequency dividing circuit that divides and outputs the clock signal is provided with a setting input terminal for forcibly fixing the signal level of the output signal, and the output is forced by inputting the signal level to the setting input terminal. A first divider circuit to which the signal is fixed;
The second frequency divider circuit forcibly fixed at a signal level different from the output signal by inputting the same signal level as the setting input terminal of the first frequency divider circuit;
The output signal is input from the first frequency dividing circuit and the second frequency dividing circuit, the signal levels of the output signals are compared, and it is determined whether they are the same or different, and output to the setting input terminal A detection circuit;
A differential frequency dividing circuit comprising:   The differential frequency dividing circuit according to claim 1, wherein the common-mode detection circuit is an exclusive OR circuit. A frequency dividing circuit that divides and outputs the clock signal is provided with a setting input terminal for forcibly fixing the signal level of the output signal, and the output is forced by inputting the signal level to the setting input terminal. A first divider circuit to which the signal is fixed;
The second frequency divider circuit forcibly fixed at a signal level different from the output signal by inputting the same signal as the setting input terminal of the first frequency divider circuit;
The output signal is input from the first frequency dividing circuit and the second frequency dividing circuit, the signal levels of the output signals are compared, and it is determined whether they are the same or different, and output to the setting input terminal A detection circuit;
Is provided on the COMS circuit board.   The differential frequency dividing circuit according to claim 3, wherein the common-mode detection circuit is an exclusive OR circuit.