JP4572779B2 - Power circuit - Google Patents

Description

  The present invention relates to a power supply circuit including a plurality of constant voltage circuits.

  As a power supply circuit including a plurality of constant voltage circuits, for example, there is one disclosed in Patent Document 1 below. Here, an outline of the configuration of the power supply circuit disclosed in Patent Document 1 will be described with reference to FIGS. Note that the power supply circuit 100 illustrated in FIG. 11 corresponds to an extract of the power supply circuit disclosed in FIG.

  As shown in FIG. 11, the power supply circuit 100 mainly includes a constant voltage supply unit 100 a and a current sink unit 100 b. From a battery voltage VB (for example, 12 V) supplied from the outside, a MOS-IC (hereinafter, “ The driving voltage Vcc (for example, 5V) of the IC 21) can be supplied. Note that the constant voltage supply unit 100a and the current sink unit 100b both function as a constant voltage circuit, as will be described below.

  The constant voltage supply unit 100a is a series regulator type constant voltage power supply circuit capable of stepping down the battery voltage VB to the drive voltage Vcc. Transistors Q21 to Q24, resistors R21 to R27, capacitors C21 to C23, an operational amplifier OP6, a constant voltage source CV29 It is comprised by. The transistors Q23 and Q24, resistors R25 to R27, the operational amplifier OP6, and the constant voltage source CV29 are integrated with the integrated circuit such as a microcomputer (hereinafter referred to as “microcomputer”) MC5 (equipped with a CPU) driven by the drive voltage Vcc. It is configured inside.

  The transistor Q21 is a PNP transistor capable of controlling the voltage supplied to the drive voltage line + Vcc, that is, the drive voltage Vcc. The emitter is connected to the battery voltage line + VB via the resistor R21, and the collector is connected to the terminal T7 of the IC 21. Has been. A smoothing capacitor C21 is connected between the terminal T7 and the ground, and a phase compensation capacitor C22, which will be described later, is connected to the terminal T7. Further, a resistor R23 connected to the battery voltage line + VB and a resistor R24 connected to the collector of the transistor Q22 are connected to the base of the transistor Q21. The transistor Q22 is an NPN transistor for current drive, its emitter is connected to the ground, and its base is connected to a terminal T25 of the IC 21 from which a control voltage is output.

  The operational amplifier OP6 is a differential amplifier capable of monitoring and controlling the drive voltage Vcc supplied from the transistor Q21 via the terminal T7. The operational amplifier OP6 is a resistor (resistors R25 and R26) connected in series between the terminal T7 and the ground. A voltage divided by the resistor R27) is used as a detection voltage Va as a non-inverting input voltage, a reference voltage Vr output from the constant voltage source CV29 is used as an inverting input voltage, and a control voltage Vp obtained by amplifying the difference voltage between the two is output. It is configured to be possible.

  The output of the operational amplifier OP6 is set to be around the threshold voltage Vt (for example, 1 V) of the transistor Q23 so that it can be input to the gate of the transistor Q23, and the transistor Q24 connected in series to the capacitor C22 As will be described later, the operational amplifier OP31 constituting the current sink section 100b can also be input. The transistor Q24 is an N-channel MOS transistor, and functions as a resistor and is connected in series with the capacitor C22 via the terminal T23, thereby connecting the input and output (non-inverting input and output) of the operational amplifier OP6. A compensation circuit is configured.

  The transistor Q23 is an N-channel MOS transistor capable of controlling the transistor Q21 via the transistor Q22 described above, and the drain and source are connected between the terminal T26 of the IC 21 and the ground. The terminal T26 is directly connected to the terminal T25, and includes a resistor R22 interposed between the terminal T26 and the battery voltage line + VB and a capacitor C23 interposed between the terminal T26 and the ground. Each is connected.

  By configuring the constant voltage supply unit 100a in this way, the detection voltage Va, which is the divided voltage of the drive voltage Vcc supplied from the transistor Q21 to the IC 21 via the terminal T7, is input to the operational amplifier OP6. The operational amplifier OP6 outputs a control voltage Vp (around the threshold voltage Vt of the transistor Q23) to the gate of the transistor Q23 as a difference voltage between the detection voltage Va and the reference voltage Vr. Accordingly, since the transistor Q23 is controlled in the saturation region, the drain current, that is, the base current of the transistor Q22 can be controlled in an analog manner, and the base voltage of the transistor Q21 can be controlled via the transistor Q22. Yes.

  For example, when the drive voltage Vcc is higher than the control target 5V, the control voltage Vp output from the operational amplifier OP6 increases, so that the drain current of the transistor Q23, that is, the base current of the transistor Q22 increases due to the increase of the gate voltage. Thus, the base voltage of the transistor Q21 is lowered. For this reason, since the drive voltage Vcc controlled by the transistor Q21 decreases, the drive voltage Vcc supplied to the terminal T7 can be brought close to the control target of 5V.

  On the other hand, when the drive voltage Vcc is lower than the control target 5V, the control voltage Vp from the operational amplifier OP6 drops, and therefore the drain current of the transistor Q23, that is, the base current of the transistor Q22 decreases due to the rise of the gate voltage. The base voltage of transistor Q21 is raised. For this reason, since the drive voltage Vcc controlled by the transistor Q21 increases, the drive voltage Vcc supplied to the terminal T7 can be brought close to the control target of 5V.

  In this way, the constant voltage supply unit 100a is configured and operates, while the current sink unit 100b is configured in the IC 21 by the transistor Q25, resistors R25 to R27, and the operational amplifier OP31. That is, the detection voltage Vb obtained by voltage division between the resistors R25 and R26 and R27 can be input to the inverting input of the operational amplifier OP31, and the output of the operational amplifier OP6 of the constant voltage supply unit 100a can be input to the non-inverting input. Constitute. The output (sink voltage Vs) of the operational amplifier OP31 can be input to the gate of the N-channel MOS transistor Q25, and the terminal T7 and the ground can be connected between the drain and source of the transistor Q25. . Thus, even if a voltage higher than the drive voltage Vcc of the microcomputer MC5 is input from the battery voltage line + VB to the terminal T9, the injected current Io can be released to the ground side by the transistor Q25.

  That is, since the injection current Io (for example, several mA or less) flowing from the terminal T9 is orders of magnitude smaller than the load current (consumption current) Ix (for example, several tens of mA) by the microcomputer MC5, the injection during the operation of the microcomputer MC5 The current Io is not charged in the capacitor C21. However, since the transistor Q21 is also in the off state when the microcomputer MC5 is in the sleep state, that is, in the sleep state, the injection current Io is charged in the capacitor C21 to increase the voltage at the terminal T9. Such a voltage rise at the terminal T7 can reach a battery voltage VB that is higher than the drive voltage Vcc of the microcomputer MC5. If the maximum input voltage allowed by the microcomputer MC5 is exceeded, the microcomputer MC5 may be damaged. Absent.

For this reason, in the current sink portion 100b, regardless of the operation state of the microcomputer MC5, the voltage that can be applied to the terminal T7, that is, the divided voltage of the drive voltage Vcc (here, 5V) is set as the detection voltage Vb (for example, 2V). The operation voltage is monitored by the operational amplifier OP31 so that the output voltage (control voltage Vp) of the operational amplifier OP6 becomes equal to Vb with reference to Vb, and the sink voltage Vs is output to control the transistor Q25. That is, in the sleep state of the microcomputer MC5, the current sink unit 100b monitors the control voltage Vp by the operational amplifier OP6 of the constant voltage supply unit 100a by the operational amplifier OP31, and thereby the voltage at the terminal T7 via the input voltage Va of the operational amplifier OP6. (Drive voltage Vcc) is indirectly monitored, and the drive voltage Vcc is controlled to be equal to or lower than the allowable voltage. As a result, the electric charge charged to the capacitor C21 and the injected current Io are released to the ground side (current sink), so that the voltage rise at the terminal T7 can be suppressed to prevent the microcomputer MC5 from being damaged.
JP-A-2005-71320

  However, in the power supply circuit 100 including the sink current circuit, when the microcomputer MC5 is in the operating state, the injected current Io is orders of magnitude smaller than the load current Ix generated by the microcomputer MC5. Exceeds the injection current Io by far. Therefore, as described above, constant voltage control is performed in the constant voltage supply unit 100a, so that the control voltage Vp of the operational amplifier OP6 is controlled around the threshold voltage Vt. On the other hand, when the microcomputer MC5 is in the sleep state, as described above, the injection current Io flowing from the battery voltage line + VB to the capacitor C21 via the terminal T9, the diode D3, and the terminal T7 becomes a problem. In order to allow the injection current Io to escape to the ground side, the current sink unit 100b is controlled by the operational amplifier OP31 so that the control voltage Vp of the operational amplifier OP6 is substantially equal to the detection voltage Vb. For this reason, the power supply circuit 100 has the following technical problems (1) and (2).

(1) Problems when the microcomputer MC5 transitions from the sleep state to the operation state A phase compensation circuit including a capacitor C22 and a transistor Q24 functioning as a resistor is connected to the output of the operational amplifier OP6. For this reason, even when the microcomputer MC5 transitions from the sleep state to the operating state, even if the control voltage Vp of the operational amplifier OP6 is controlled to drop from the equivalent of the detection voltage Vb to the vicinity of the threshold voltage Vt of the transistor Q23, Since the capacitor C22 constituting the compensation circuit takes time to discharge, the control voltage Vp falls gently during the discharge period.

  Therefore, the control voltage Vp cannot fall steeply like the waveform of the dotted line K shown in FIG. 12 (output response waveform when the phase compensation circuit does not exist). For this reason, as the output response of the operational amplifier OP6 is delayed, the control of the drive voltage Vcc by the operational amplifier OP6 described above is delayed, and the drive voltage Vcc sinks. That is, the drive voltage Vcc continues to drop (sinks) until the control voltage Vp of the operational amplifier OP6 becomes substantially equal to the detection voltage Vb (2V) from the threshold voltage Vt (1V) of the transistor Q23. Thus, there is a problem that a decrease in the drive voltage Vcc prevents a stable supply of the drive voltage Vcc, which can lead to a system reset of the microcomputer MC5.

(2) Problems when the microcomputer MC5 transits from the operating state to the sleep state On the other hand, when the microcomputer MC5 transits from the operating state to the sleep state, the phase compensation circuit acts as a load of the operational amplifier OP6. For this reason, as shown in FIG. 13, even when the control voltage Vp of the operational amplifier OP6 is controlled to be substantially equal to the detection voltage Vb by the operational amplifier OP31, the control voltage Vp is charged to the capacitor C22 via the transistor Q24. The output (control voltage Vp) of the operational amplifier OP6 rises gently.

  Therefore, the control voltage Vp cannot rise steeply like the waveform of the dotted line K ′ shown in FIG. 13 (the output response waveform when the phase compensation circuit does not exist). For this reason, as the output response of the operational amplifier OP6 is delayed, the control of the drive voltage Vcc by the operational amplifier OP31 described above is delayed to cause overshoot. That is, since the drive voltage Vcc continues to rise until the control voltage Vp of the operational amplifier OP6 becomes substantially equal to the detection voltage Vb (2V) from the threshold voltage Vt (1V) of the transistor Q23 (overshoot). There is a problem that this becomes a ripple voltage, which prevents a stable supply of the drive voltage Vcc, and may lead to a failure of the microcomputer MC5.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a power supply circuit that can prevent a system reset or failure of a microcomputer or the like that receives a power supply voltage. is there.

The numbers in [] in the following description can correspond to the reference numerals and the like described in the [Best Mode for Carrying Out the Invention] column.
In order to achieve the above object, in the power supply circuit according to claim 1, the control input [Va] based on the voltage [Vcc] of the power supply line [+ Vcc] and the predetermined first reference input [Vr] The first control means [OP32, OP52] capable of outputting the first control output [Vp] based on the difference between the power supply line [+ Vcc] and the first control means [OP32, OP52] which is higher than the voltage [Vcc] of the power supply line [+ Vcc]. 1st step-down means [Q21] capable of stepping down or shutting off one input voltage [VB] equal to the voltage [Vcc] of the power supply line [+ Vcc] according to the first control output [Vp], The voltage stepped down by the first step-down means [Q21] during the constant voltage control output state [operation state of the microcomputer MC5] in which the control output [Vp] can control the step-down of the first input voltage [VB]. Power line [+ Vcc Output voltage [Vcc] to the power supply line [+ Vcc], and the first control output [Vp] can control the interruption of the first input voltage [VB] [the sleep state of the microcomputer MC5 ] A first constant voltage circuit [30a, 40a, 50a] capable of cutting off the output to the power line [+ Vcc] during the period of
Based on the difference between the first control output [Vp] output from the first control means [OP32, OP52] of the first constant voltage circuit [30a, 40a, 50a] and the predetermined second reference input [Vb]. The second control means [OP31] capable of outputting the second control output [Vs] and the first step-down means [Q21] of the first constant voltage circuit [30a, 40a, 50a] are connected to the first input voltage [VB]. The second input voltage [VB] that is higher than the voltage [Vcc] of the power supply line [+ Vcc] can be stepped down according to the second control output [Vs]. Second voltage step-down means [Q25], and the voltage stepped down by the second voltage step-down means [Q25] is set as the voltage [Vcc] of the power supply line [+ Vcc] during the cutoff control period. + Vcc] can be output to the second constant A voltage circuit [30b, 40b, 50b];
The first control output [Vp] output by the first control means [OP32, OP52] of the first constant voltage circuit [30a, 40a, 50a] is the constant voltage control output state [operation state] and the cutoff control. A delay factor circuit [C22, Q24] capable of delaying transition between the output state [sleep state] and a power supply circuit comprising:
The first control output [Vp] by the first constant voltage circuit [30a, 40a, 50a] transits from the cutoff control output state [sleep state] to the constant voltage control output state [operation state], or the first The delay factor circuit indicates that the first control output [Vp] by the one constant voltage circuit [30a, 40a, 50a] transits from the constant voltage control output state [operation state] to the cutoff control output state [sleep state]. Provided is an assist circuit [30c, 40c, 50c, 50d] that is enabled without being affected by [C22, Q24] .

2. The power supply circuit according to claim 1, wherein the assist circuit [30c, 40c, 50c, 50d] outputs from the first control means [OP32, OP52] of the first constant voltage circuit [30a, 40a, 50a]. The first control output [Vp] is changed to the constant voltage during a period in which the first control output [Vp] is changed from the interruption control output state [sleep state] to the constant voltage control output state [operation state]. It is a constant voltage control direction pull-in circuit [30c, 40c, 50c] that pulls in the direction of the control output state [operation state] .

2. The power supply circuit according to claim 1, wherein the constant voltage control direction pull-in circuit [30c, 40c, 50c] is an error amplifier [OP32] as the first control means [OP32, OP52], The first control output [Vp] and the first control output are obtained by amplifying the error between the control input [Va] based on the voltage [Vcc] of the line [+ Vcc] and the predetermined first reference input [Vr]. An error amplifier [OP32] capable of outputting to another first control output [Vn] independent of [Vp], and the first control output [Vp] based on the other first control output [Vn] And a transistor [Q34] that approaches the potential [Vt] in the constant voltage control output state [operation state] .

In the power supply circuit according to claim 2, the first power supply circuit based on the difference between the control input [Va] based on the voltage [Vcc] of the power supply line [+ Vcc] and the predetermined first reference input [Vr]. The first control means [OP32, OP52] capable of outputting the control output [Vp] and the first input voltage [VB] higher than the voltage [Vcc] of the power supply line [+ Vcc] among the voltages input from the outside. In accordance with the first control output [Vp], there is a first step-down means [Q21] that can be stepped down or cut off equally to the voltage [Vcc] of the power line [+ Vcc], and the first control output [Vp] is The voltage stepped down by the first step-down means [Q21] during the constant voltage control output state [operation state of the microcomputer MC5] capable of controlling the step-down of the first input voltage [VB] is supplied to the power supply line [+ Vcc]. As the voltage [Vcc] The power supply can be output to the power supply line [+ Vcc], and the power supply can be output during the interruption control output state [the microcomputer MC5 sleep state] in which the first control output [Vp] can control the interruption of the first input voltage [VB]. A first constant voltage circuit [30a, 40a, 50a] capable of shutting off the output to the line [+ Vcc];
Based on the difference between the first control output [Vp] output from the first control means [OP32, OP52] of the first constant voltage circuit [30a, 40a, 50a] and the predetermined second reference input [Vb]. The second control means [OP31] capable of outputting the second control output [Vs] and the first step-down means [Q21] of the first constant voltage circuit [30a, 40a, 50a] are connected to the first input voltage [VB]. The second input voltage [VB] that is higher than the voltage [Vcc] of the power supply line [+ Vcc] can be stepped down according to the second control output [Vs]. Second voltage step-down means [Q25], and the voltage stepped down by the second voltage step-down means [Q25] is set as the voltage [Vcc] of the power supply line [+ Vcc] during the cutoff control period. + Vcc] can be output to the second constant A voltage circuit [30b, 40b, 50b];
The first control output [Vp] output by the first control means [OP32, OP52] of the first constant voltage circuit [30a, 40a, 50a] is the constant voltage control output state [operation state] and the cutoff control. A delay factor circuit [C22, Q24] capable of delaying transition between the output state [sleep state] and a power supply circuit comprising:
The first control output [Vp] by the first constant voltage circuit [30a, 40a, 50a] transits from the cutoff control output state [sleep state] to the constant voltage control output state [operation state], or the first The delay factor circuit indicates that the first control output [Vp] by the one constant voltage circuit [30a, 40a, 50a] transits from the constant voltage control output state [operation state] to the cutoff control output state [sleep state]. Provided is an assist circuit [30c, 40c, 50c, 50d] that is enabled without being affected by [C22, Q24].
3. The power supply circuit according to claim 2, wherein the assist circuit [50d] has a first control output [Vp] output from first control means [OP52] of the first constant voltage circuit [50a]. Interruption control that draws the first control output [Vp] in the direction of the interruption control output state [sleep state] during the period of transition from the constant voltage control output state [operation state] to the interruption control output state [sleep state]. Direction pull-in circuit [50d] .

3. The power supply circuit according to claim 2, wherein the cutoff control direction pull-in circuit [50d] is an error amplifier [OP52] as the first control means [OP32, OP52], and is connected to the power supply line [+ Vcc]. Amplified error between the control input [Va] based on the voltage [Vcc] and the predetermined first reference input [Vr] is independent of the first control output [Vp] and the first control output [Vp]. The error amplifier [OP52] capable of outputting to the other first control output [Vn ′], and the first control output [Vp] based on the other first control output [Vn ′]. And a transistor [Q54] that approaches the potential [Vb] of the state [sleep state] .

  In the invention of claim 1, since the assist circuit [30c, 40c, 50c, 50d] is provided, the first control output [Vp] by the first constant voltage circuit [30a, 40a, 50a] From the constant voltage control output state [operating state] to the first control output [Vp] by the first constant voltage circuit [30a, 40a, 50a]. Transition to the output state [sleep state] is possible without being affected by the delay factor circuit [C22, Q24].

  As a result, when the switching control output state [sleep state] transitions to the constant voltage control output state [operation state], the state transition of the first control output [Vp] is affected by the delay factor circuit [C22, Q24]. Therefore, the first step-down voltage means [Q21] causes a delay in the first control output [Vp] during such state transition (output response delay) due to the control delay of the first step-down voltage means [Q21]. It is possible to suppress the sinking of the voltage [Vcc] of the power supply line [+ Vcc] that occurs with a delay in switching from the cut-off voltage to the power supply line [+ Vcc] to the output (see FIG. 12). . Therefore, in order to suppress the voltage drop of the power supply line [+ Vcc] due to such sinking, the microcomputer [MC5 that enables the stable supply of the voltage [Vcc] by the power supply line [+ Vcc] and receives the supply of the voltage [Vcc]. ] Can be prevented.

  In addition, when the constant voltage control output state [operation state] transitions to the cutoff control output state [sleep state], the state transition of the first control output [Vp] is affected by the delay factor circuit [C22, Q24]. The control delay of the second step-down means [Q25] by the second control means [OP31] due to the delay of the first control output [Vp] (output response delay) at the time of such a state transition. Therefore, the overshoot of the voltage [Vcc] of the power supply line [+ Vcc], which is generated with a delay in the output of the voltage stepped down by the second step-down means [Q25] to the power supply line [+ Vcc] (see FIG. 13), is suppressed. It becomes possible. Therefore, in order to suppress an increase in the voltage of the power supply line [+ Vcc] due to such overshoot, the microcomputer [MC5 that enables the stable supply of the voltage [Vcc] by the power supply line [+ Vcc] and receives the supply of the voltage [Vcc]. ] Can be prevented.

In the invention of claim 1 , the constant voltage control direction pull-in circuit [30c, 40c, 50c], which is the assist circuit [30c, 40c, 50c, 50d], is the same as the first constant voltage circuit [30a, 40a, 50a]. During the period in which the first control output [Vp] output from the first control means [OP32, OP52] transitions from the cutoff control output state [sleep state] to the constant voltage control output state [operation state], the first control is performed. The output [Vp] is pulled in the direction of the constant voltage control output state [operation state]. As a result, during the state transition period, the first control output [Vp] is pulled in the direction of the constant voltage control output state [operation state], so that the first control output [Vp] Without being influenced by the circuit [C22, Q24], it is possible to make a quick transition to the constant voltage control output state [operation state]. Accordingly, the sinking of the voltage [Vcc] of the power supply line [+ Vcc] (see FIG. 12) can be suppressed, so that the voltage [Vcc] can be stably supplied by the power supply line [+ Vcc] and the supply of the voltage [Vcc] can be performed. It is possible to prevent a system reset of the receiving microcomputer [MC5] or the like.

Further, in the first aspect of the invention, the constant voltage control direction pull-in circuit [30c, 40c, 50c] is an error amplifier [OP32] as the first control means [OP32, OP52], and is connected to the power line [+ Vcc]. Amplified error between the control input [Va] based on the voltage [Vcc] and the predetermined first reference input [Vr] is obtained as another independent of the first control output [Vp] and the first control output [Vp]. The error amplifier [OP32] that can be output to the first control output [Vn], and the potential of the first control output [Vp] based on the other first control output [Vn] in the constant voltage control output state [operation state] And a transistor [Q34] that approaches [Vt]. As a result, during the period in which the first control output [Vp] transitions from the cutoff control output state [sleep state] to the constant voltage control output state [operation state], the transistor [Q34] causes the first control output [Vp]. ] Is pulled in the direction of the constant voltage control output state [operation state], the first control output [Vp] is not affected by the delay factor circuit [C22, Q24], and the constant voltage control output state [operation It is possible to make a quick transition to [Status]. Accordingly, the sinking of the voltage [Vcc] of the power supply line [+ Vcc] (see FIG. 12) can be suppressed, so that the voltage [Vcc] can be stably supplied by the power supply line [+ Vcc] and the supply of the voltage [Vcc] can be performed. It is possible to prevent a system reset of the receiving microcomputer [MC5] or the like.

In the invention of claim 2, since the assist circuit [30c, 40c, 50c, 50d] is provided, the first control output [Vp] by the first constant voltage circuit [30a, 40a, 50a] is in the cutoff control output state [sleep state]. From the constant voltage control output state [operating state] to the first control output [Vp] by the first constant voltage circuit [30a, 40a, 50a]. Transition to the output state [sleep state] is possible without being affected by the delay factor circuit [C22, Q24].
As a result, when the switching control output state [sleep state] transitions to the constant voltage control output state [operation state], the state transition of the first control output [Vp] is affected by the delay factor circuit [C22, Q24]. Therefore, the first step-down voltage means [Q21] causes a delay in the first control output [Vp] during such state transition (output response delay) due to the control delay of the first step-down voltage means [Q21]. It is possible to suppress the sinking of the voltage [Vcc] of the power supply line [+ Vcc] that occurs with a delay in switching from the cut-off voltage to the power supply line [+ Vcc] to the output (see FIG. 12). . Therefore, in order to suppress the voltage drop of the power supply line [+ Vcc] due to such sinking, the microcomputer [MC5 that enables the stable supply of the voltage [Vcc] by the power supply line [+ Vcc] and receives the supply of the voltage [Vcc]. ] Can be prevented.
In addition, when the constant voltage control output state [operation state] transitions to the cutoff control output state [sleep state], the state transition of the first control output [Vp] is affected by the delay factor circuit [C22, Q24]. The control delay of the second step-down means [Q25] by the second control means [OP31] caused by the delay of the first control output [Vp] (output response delay) at the time of such a state transition. Therefore, the overshoot of the voltage [Vcc] of the power supply line [+ Vcc], which is generated with a delay in the output of the voltage stepped down by the second step-down means [Q25] to the power supply line [+ Vcc] (see FIG. 13), is suppressed. It becomes possible. Therefore, in order to suppress an increase in the voltage of the power supply line [+ Vcc] due to such overshoot, the microcomputer [MC5 that enables the stable supply of the voltage [Vcc] by the power supply line [+ Vcc] and receives the supply of the voltage [Vcc]. ] Can be prevented.
In the invention of claim 2 , the cutoff control direction pull-in circuit [50d] , which is the assist circuit [30c, 40c, 50c, 50d], is output from the first control means [OP52] of the first constant voltage circuit [50a]. The first control output [Vp] is changed from the constant voltage control output state [operation state] to the interruption control output state [sleep state] during the period in which the first control output [Vp] is changed to the interruption control output state [sleep]. Pull in the direction of [Status]. Thus, during the state transition period, the first control output [Vp] is drawn in the direction of the cutoff control output state [sleep state], and therefore the first control output [Vp] is the delay factor circuit. Without being influenced by [C22, Q24], it is possible to quickly transition to the shutoff control output state [sleep state]. Accordingly, since overshoot (see FIG. 13) of the power supply line [+ Vcc] can be suppressed, the microcomputer [MC5] that can stably supply the voltage [Vcc] by the power supply line [+ Vcc] and receives the supply of the voltage [Vcc]. Etc. can be prevented.

Further, in the invention of claim 2 , the cutoff control direction pull-in circuit [50d] which is the assist circuit [30c, 40c, 50c, 50d] is the error amplifier [OP52] as the first control means [OP32, OP52]. The first control output [Vp] and the first control output are obtained by amplifying the error between the control input [Va] based on the voltage [Vcc] of the power line [+ Vcc] and the predetermined first reference input [Vr]. Error amplifier [OP32] capable of outputting to other first control output [Vn ′] independent from [Vp], and first control output [Vp] cut off based on other first control output [Vn ′] And a transistor [Q54] for approaching the potential of the control output state. As a result, during the period in which the first control output [Vp] transitions from the constant voltage control output state [operation state] to the cutoff control output state [sleep state], the transistor [Q54] causes the first control output [Vp]. ] Is pulled in the direction of the cutoff control output state [sleep state], the first control output [Vp] is not affected by the delay factor circuit [C22, Q24], and the cutoff control output state [sleep state] It is possible to transition to agile. Accordingly, since overshoot (see FIG. 13) of the power supply line [+ Vcc] can be suppressed, the microcomputer [MC5] that can stably supply the voltage [Vcc] by the power supply line [+ Vcc] and receives the supply of the voltage [Vcc]. Etc. can be prevented.

  Hereinafter, embodiments of a power supply circuit of the present invention will be described with reference to the drawings. The power supply circuits 30, 40, 50 according to each embodiment described below are configured based on the power supply circuit 100 disclosed in Patent Document 1 described in the “Background Art” section. Therefore, in the description of these power supply circuits 30, 40, and 50, substantially the same components as those of the power supply circuit 100 are denoted by the same reference numerals, and description of the corresponding portions is omitted.

[First Embodiment]
First, the power supply circuit 30 according to the first embodiment will be described with reference to FIGS. The power supply circuit 30 according to the first embodiment can solve the “(1) problem when the microcomputer MC5 transitions from the sleep state to the operating state” described in the section “Problems to be solved by the invention”. Thus, the following [1], [2] and [3] are different from the power supply circuit 100 described above. The sleep state of the microcomputer MC5 can correspond to the “shutdown control output state” described in the claims, and the operation state of the microcomputer MC5 is the “constant voltage control output state” described in the claims. ".

  [1] The power supply circuit 30 includes a transistor Q34 that receives the output of an operational amplifier OP32 (corresponding to the operational amplifier 6 of the power supply circuit 100) that monitors and controls the drive voltage Vcc (see FIG. 1). The operational amplifier OP32 can correspond to an “error amplifier” recited in the claims, and is also referred to as a “differential amplifier”.

  The problem of the above (1) is a phase compensation circuit connected to the output of the operational amplifier OP6 constituting the power supply circuit 100 (capacitor C22, transistor Q24; one that can correspond to the “delay factor circuit” recited in the claims). This is based on the fact that the capacitor C22 takes time to discharge. Therefore, as shown in FIG. 1, in the power supply circuit 30 according to the first embodiment, the N-channel MOS transistor Q34 receives the reverse control voltage Vn (reverse phase output n) of the operational amplifier OP32 described in [2] below at the gate. Is provided between the positive phase output p of the operational amplifier OP32 (corresponding to the output of the operational amplifier 6 of the power supply circuit 100) and the ground. The source of the transistor Q34 is directly connected to the ground, and no load circuit or the like is connected between the transistor Q34 and the ground.

  Therefore, regardless of the presence or absence of the phase compensation circuit, the positive phase output p of the operational amplifier OP32 can be connected to the ground side via the transistor Q34. That is, the bypass circuit capable of directly connecting the positive phase output p of the operational amplifier OP32 to the ground is formed by the transistor Q34. As a result, even if the phase compensation circuit composed of the capacitor C22 and the resistance of the transistor Q24 is connected to the positive phase output p of the operational amplifier OP32, the positive phase output p of the operational amplifier OP32 is connected to the ground side by the switching operation of the transistor Q34. Therefore, when a response delay can occur in the output of the operational amplifier OP32, it is possible to improve the response delay by increasing the drive of the operational amplifier OP32. The circuit formed by the transistor Q34 may correspond to a part of the “constant voltage control direction pull-in circuit” described in the claims. In FIG. Part of the constant voltage control direction pull-in circuit).

  [2] As shown in FIG. 1, in the power supply circuit 30, an operational amplifier OP <b> 32 having two outputs is provided as an equivalent to the operational amplifier 6 of the power supply circuit 100. FIG. 2 shows a circuit example of the operational amplifier OP32, which will be described with reference to FIG.

  As shown in FIG. 2, the operational amplifier OP32 includes a differential section composed of transistors Q32a, Q32b, Q32f and Q32g, a constant current section composed of a resistor 32i and transistors Q32j and Q32k, and a positive phase composed of transistors Q32c, Q32d, Q32e and Q32h. An output section and a reverse phase output section composed of transistors Q32m to Q32p are provided.

  That is, the differential section of the operational amplifier OP32 causes a P-channel MOS transistor Q32a receiving the non-inverting input IN + at the gate, a P-channel MOS transistor Q32f receiving the inverting input IN− at the gate, and a current according to these differential inputs. N-channel MOS transistors Q32b and Q32g to be obtained. The differential portion can be supplied with a constant current by a P-channel MOS transistor Q32k in a current mirror relationship with the transistor Q32j constituting the constant current portion.

  The constant current section of the operational amplifier OP32 is interposed between the drive voltage line + Vcc and the ground, a resistor 32i that can generate a constant current based on the drive voltage Vcc supplied from the drive voltage line + Vcc, and this resistor P-channel MOS transistors Q32j and Q32k connected in series to 32i and connected in a current mirror relationship so that the constant current can be taken out by transistor Q32k.

  Further, the positive phase output section of the operational amplifier OP32 includes an N channel MOS transistor Q32c configured in a current mirror relationship with the transistor Q32b of the differential section described above, and a P channel MOS transistor Q32d connected in series to the transistor Q32c. P-channel MOS transistor Q32e configured in a current mirror relationship with transistor Q32d, and N-channel MOS transistor Q32h connected in series with transistor Q32e and configured in a current mirror relationship with differential transistor Q32g And having.

  The transistor Q32e capable of flowing a current proportional to the non-inverting input IN + is placed on the drive voltage Vcc side, and the transistor Q32h capable of flowing a current proportional to the inverting input IN- is placed on the ground side, so that both transistors are connected in series. They are connected and interposed between the drive voltage Vcc and the ground. As a result, the control voltage Vn can be output from the connection point between the non-inverting input IN + and the inverting input IN− as the positive phase output p. The positive phase output p corresponds to the output of a normal operational amplifier (for example, the operational amplifier 6 of the power supply circuit 100).

  In the operational amplifier OP32, in addition to the positive-phase output unit that can output the control voltage Vn (positive-phase output p), an N-channel MOS transistor configured in the relationship between the transistor Q32g of the differential unit and the current mirror described above. Q32m, a P-channel MOS transistor Q32n connected in series to this transistor Q32m, an N-channel MOS transistor Q32p configured in a current mirror relationship with the transistor Q32b in the differential section, and connected in series to this transistor Q32p In addition, it has a reverse phase output portion comprising a transistor Q32n and a P-channel MOS transistor Q32o configured in a current mirror relationship.

  The transistor Q32o that can flow a current proportional to the inverting input IN- is on the drive voltage Vcc side, and the transistor Q32p that can flow a current proportional to the non-inverting input IN + is on the ground side. They are connected and interposed between the drive voltage Vcc and the ground. As a result, the reverse control voltage Vn can be output using the difference voltage between the inverting input IN− and the non-inverting input IN + as the reverse phase output n from the connection point between the two. The circuit formed by the transistors Q32m, Q32n, Q32o, and Q32p can correspond to the remainder of the “constant voltage control direction pull-in circuit” recited in the claims. In FIG. 2, a broken line denoted by reference numeral 30c. The range corresponds to the rest of the assist circuit (constant voltage control direction pull-in circuit).

  With this configuration, in the operational amplifier OP32, in addition to the normal phase output p corresponding to the output of a normal operational amplifier, a negative phase output n that can obtain an output having a reverse polarity independent of the normal phase output p is provided. It becomes possible to output (the output voltage by the reverse phase output n is referred to as “reverse control voltage Vn”). Therefore, by connecting the negative-phase output n to the gate of the N-channel MOS transistor Q34 described above, as described in [1] above, when the microcomputer MC5 transitions from the sleep state to the operating state, the transistor Q34. With this switching operation, the positive phase output of the operational amplifier OP32 can be bypassed to the ground side. Note that the reverse phase output n and the reverse control voltage Vn can correspond to “another first control output” recited in the claims.

  [3] In the power supply circuit 30, the channel width W of the transistor Q32p constituting the operational amplifier OP32 is set to be larger than the channel width W of the transistor Q32b constituting the operational amplifier OP32. Note that the channel width W is a width in a direction orthogonal to a channel length L (a drain-source separation distance) of a semiconductor device in which the transistor is formed.

  That is, by setting the channel width Wb of the transistor Q32b and the channel width Wp of the transistor Q32p formed of the transistor Q32b and the current mirror to a relationship of Wb <Wp, as shown in FIG. The output relation between the positive phase output p and the negative phase output n with respect to the differential input is made asymmetric (the broken line shown in FIG. 3 is a symmetric output), and the switching operation point of the transistor Q34 by the negative phase output n Von is set so that it is outside the expected movable region of the control voltage Vp. The positive phase output p and the control voltage Vp can correspond to the “first control output” recited in the claims.

  As a result, since the switching-on operation by the transistor Q34 is not performed within the movable region of the control voltage Vp by the operational amplifier OP32, operation of the constant voltage supply unit 30a and the current sink unit 30b is not hindered. That is, during the period when the microcomputer MC5 transitions from the sleep state to the operation state, the switching operation by the transistor Q34 can be performed, and the positive phase output p of the operational amplifier OP32 can be bypassed to the ground side.

  Therefore, as shown in FIG. 4, in the sleep state of the microcomputer MC5, the control voltage Vp from the positive phase output p of the operational amplifier OP32 is almost equal to the detection voltage Vb obtained by voltage division between the resistor R25 and the resistors R26 and R27. An equally controlled voltage (about 2 V when the drive voltage Vcc is 5 V) is output. This is because, as described in the “Background Art” section, the current sink 30b calculates the divided voltage of the allowable voltage at the terminal T7, that is, the drive voltage Vcc (here, 5V) regardless of the operating state of the microcomputer MC5. This is because the detection voltage Vb is used, and the operation voltage is monitored by the operational amplifier OP32 so that the control voltage Vp of the operational amplifier OP32 becomes equal to the detection voltage Vb with reference to this detection voltage Vb, and the transistor Q25 is controlled by outputting the sink voltage Vs. . The sink voltage Vs can correspond to the “second control output” recited in the claims.

  When a transition is made from such a sleep state to the operation state of the microcomputer MC5, the transistor Q34 is turned off by the reverse control voltage Vn output from the reverse phase output n of the operational amplifier OP32 during the state transition. Transition to ON operation. Therefore, since the positive phase output p of the operational amplifier OP32 is connected to the ground side, the control voltage Vp is forcibly pulled in the direction of the threshold voltage Vt of the transistor Q23 (about 1V when the drive voltage Vcc is 5V). . As a result, even if the phase compensation circuit (C22, Q24) is connected to the positive phase output p of the operational amplifier OP32, the control voltage Vp transitions rapidly to the threshold voltage Vt of the transistor Q23 without being affected by it. It becomes possible.

  Therefore, as apparent from a comparison between FIG. 4 and FIG. 12, the delay in the output response by the operational amplifier OP32 can be greatly improved, and the sinking of the drive voltage Vcc due to the output response delay of the operational amplifier OP32 can be suppressed. Yes. Therefore, since the stable supply of the drive voltage Vcc by the drive voltage line + Vcc (power supply line) is enabled, it is possible to prevent the system reset of the microcomputer MC5 or the like that receives the supply of the drive voltage Vcc. Note that the dotted waveform indicated by the symbol K in FIG. 4 is an example of an output response waveform when the capacitor C22 is not present.

  As described above, in the power supply circuit 30 according to the first embodiment, the positive phase output p (control) is obtained by amplifying the error between the detection voltage Va based on the drive voltage Vcc of the drive voltage line + Vcc and the reference voltage Vr. Voltage Vp) and an operational amplifier OP32 capable of outputting a negative phase output n (reverse control voltage Vn) independent of the normal phase output p (control voltage Vp), and a positive phase based on the negative phase output n (reverse control voltage Vn). The assist circuit 30c is provided with a transistor Q34 that brings the output p (control voltage Vp) close to the potential Vt of the operating state of the microcomputer MC5.

  Thus, during the period in which the positive phase output p (control voltage Vp) transitions from the sleep state to the operation state of the microcomputer MC5, the transistor Q34 causes the positive phase output p (control voltage Vp) to become the potential Vt of the operation state. Therefore, the positive-phase output p (control voltage Vp) can quickly transition to the operating state potential Vt of the microcomputer MC5 without being affected by the phase compensation circuit (C22, Q24). Become. Therefore, the sinking of the drive voltage Vcc of the drive voltage line + Vcc (see FIG. 12) can be suppressed, so that the drive voltage Vcc can be stably supplied by the drive voltage line + Vcc and the microcomputer MC5 or the like receiving the drive voltage Vcc can be supplied. System reset can be prevented.

  Here, as a modification of the power supply circuit 30 according to the first embodiment, the configuration of the power supply circuit 40 will be described with reference to FIGS. 5 and 6. In the power supply circuit 30 described above, the transistor Q34 is provided so as to be directly interposed between the positive phase output p of the operational amplifier OP32 and the ground, whereas in the assist circuit 40c constituting the power supply circuit 40 of the present modified example, the transistor Q34 is provided. The difference from the power supply circuit 30 described above is that the transistor Q42 in a current mirror relationship with Q23 is provided between the positive phase output p of the operational amplifier OP32 and the drain of the transistor Q34. For this reason, in FIG. 5, the same reference numerals are given to the substantially same components as those of the power supply circuit 30 shown in FIG. In FIG. 5, reference numeral 40a denotes a constant voltage supply unit, and reference numeral 40b denotes a current sink unit, which are configured in the same manner as the constant voltage supply unit 30a and the current sink unit 30b of the power supply circuit 30 described above.

  That is, as shown in FIG. 5, in the assist circuit 40c, the source of the transistor Q42 receiving the same positive phase output p at the gate and the drain is connected to the transistor Q23 with respect to the transistor Q23 receiving the positive phase output p of the operational amplifier OP32. Connect to the drain. Further, the arrangement of the transistor Q42 on the semiconductor substrate of the IC 21 is set so as to be adjacent to the transistor Q23 formed on the semiconductor substrate in a mirror-symmetrical manner.

  Thus, since the transistor Q42 and the transistor Q23 are in a current mirror relationship both electrically and mechanically (thermally), a drain current substantially equal to the drain current flowing between the drain and source of the transistor Q23 is a transistor. It also flows between the drain and source of Q42. For this reason, when the control voltage Vp output from the positive phase output p of the operational amplifier OP32 is lower than the threshold voltage Vt of the transistor Q23, the transistor Q23 transitions to a cut-off state (off state) and drain current Therefore, the transistor Q42, which is in the relationship of current mirror with the transistor Q23, can also be changed to the cut-off state (off state).

  Therefore, as shown in FIG. 6, even when the microcomputer MC5 transitions from the sleep state to the operating state, the positive phase output p (control voltage Vp) of the operational amplifier OP32 can be further pulled to the ground side by the assist circuit 40c described above. (Within the broken line ellipse indicated by α in FIG. 6), the positive phase output p (control voltage Vp) falls below the threshold voltage Vt of the transistor Q23, and at the same time, the transistor Q23 transitions to a cut-off state (off state). Almost simultaneously with this, the transistor Q42 also changes to the cutoff state (off state).

  For this reason, as in the assist circuit 30c constituting the power supply circuit 30 described above, the phenomenon that the positive phase output p (control voltage Vp) output from the positive phase output p of the operational amplifier OP32 is excessively pulled to the ground side ( 6 does not occur (see FIG. 4), a ripple voltage due to overshoot is generated in the drive voltage Vcc controlled by the transistor Q23 via the transistors Q22 and Q21. (A waveform by a broken line in an ellipse with a symbol β shown in FIG. 6). Therefore, since the generation of the ripple voltage can be prevented in the power supply circuit 40, not only the driving voltage Vcc can be stably supplied by the driving voltage line + Vcc, but also the power supply noise caused by the ripple voltage can be suppressed. become.

[Second Embodiment]
Next, the power supply circuit 50 according to the second embodiment will be described with reference to FIGS. The power supply circuit 50 according to the second embodiment includes “(1) Problems when the microcomputer MC5 transits from the sleep state to the operating state” described in the section “Problems to be solved by the invention”. (2) The problem that occurs when the microcomputer MC5 transitions from the operating state to the sleep state "is also solved. The power supply circuit 100 described above is the same as [1], [2] and [3] described in the first embodiment. ], [4], [5] and [6] are different.

  Here, the description will be centered on the configuration of [4], [5] and [6], and the configuration of [1], [2] and [3] will be described in the first embodiment. Since the configuration is the same as that of the power supply circuit, the power supply circuit 50 also includes the configurations [1], [2], and [3], so that the same operations and effects as those according to the first embodiment can be obtained. In FIG. 7, reference numeral 50a denotes a constant voltage supply unit, and reference numeral 50b denotes a current sink unit, which are configured in the same manner as the constant voltage supply unit 30a and the current sink unit 30b of the power supply circuit 30 described above. In addition, substantially the same components as those of the power supply circuit 30 of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  [4] The power supply circuit 50 is provided with a transistor Q54 that receives the output of an operational amplifier OP52 (corresponding to the operational amplifier 6 of the power supply circuit 100) that monitors and controls the drive voltage Vcc (see FIG. 7). The operational amplifier OP52 can correspond to an “error amplifier” recited in the claims, and is also referred to as a “differential amplifier”.

  The above problem (2) is based on the fact that the phase compensation circuit (capacitor C22, transistor Q24) connected to the output of the operational amplifier OP6 constituting the power supply circuit 100 acts as a load of the operational amplifier 6. Therefore, as shown in FIG. 7, in the power supply circuit 50 according to the second embodiment, as will be described in the next item [5], the operational amplifier OP52 includes the operational amplifier OP52 that constitutes the constant voltage supply unit 30a described above. An N-channel MOS transistor Q34 that receives a negative-phase output n (reverse control voltage Vn) at its gate is provided between the positive-phase output p of the operational amplifier OP52 and the ground via the transistor Q42. In the second embodiment, the operational amplifier A P-channel MOS transistor Q54 that receives another negative-phase output n ′ (reverse control voltage Vn ′) of OP52 at its gate is provided between the positive-phase output p of the operational amplifier OP52 and the drive power supply Vcc. The drain of the transistor Q54 is directly connected to the drive power supply Vcc, and no load circuit or the like is connected between the transistor Q54 and the drive power supply Vcc.

  Therefore, regardless of the presence or absence of the phase compensation circuit, the positive phase output p of the operational amplifier OP52 can be connected to the drive voltage Vcc side via the transistor Q54. That is, the bypass circuit that can directly connect the positive phase output p of the operational amplifier OP52 to the drive voltage Vcc is formed by the transistor Q54. As a result, even if the phase compensation circuit including the capacitor C22 and the resistance of the transistor Q24 is connected to the positive phase output p of the operational amplifier OP52, the positive phase output p of the operational amplifier OP52 is driven by the switching operation of the transistor Q54. Since it can be bypassed to the Vcc side, when a response delay may occur in the output of the operational amplifier OP52, it becomes possible to improve the response delay by increasing the drive of the operational amplifier OP52. The circuit formed by the transistor Q54 can correspond to a part of the “cut-off control direction pull-in circuit” recited in the claims. In FIG. 7, the broken line range denoted by reference numeral 50c is an assist circuit (cut-off circuit). Part of the control direction pull-in circuit).

  [5] As shown in FIG. 7, in the power supply circuit 50, an operational amplifier OP <b> 52 having three outputs is provided as an equivalent to the operational amplifier 6 of the power supply circuit 100. The circuit example of the operational amplifier OP52 shown in FIG. 8 is obtained by adding an assist circuit 50d to the circuit example (see FIG. 2) of the operational amplifier OP32 constituting the constant voltage supply unit 30a of the power supply circuit 30 of the first embodiment described above. It corresponds to. Therefore, in FIG. 8, components that are substantially the same as those of the operational amplifier OP32 of FIG.

  As shown in FIG. 8, the operational amplifier OP52 has a differential section composed of transistors Q32a, Q32b, Q32f and Q32g, a constant current section composed of a resistor 32i and transistors Q32j and Q32k, and a positive phase composed of transistors Q32c, Q32d, Q32e and Q32h. An output unit, a first negative phase output unit including transistors Q32m to Q32p, and a second negative phase output unit including transistors Q52a and Q52b are provided. The differential unit, the constant current unit, and the positive phase output unit are configured in the same manner as the differential unit, the constant current unit, and the positive phase output unit that constitute the operational amplifier OP32, and the first negative phase output unit is the operational amplifier. Since it corresponds to the reverse phase output part which comprises OP32, and is comprised similarly to it, these description is abbreviate | omitted here.

  In the operational amplifier OP52, the control voltage Vn (positive phase output p) is output from the differential unit, constant current unit, and positive phase output unit, and the reverse control voltage is output from the differential unit, constant current unit, and first negative phase output unit. In addition to being able to output Vn (reverse phase output n), the differential unit, the constant current unit and the second reverse phase output unit are configured to output a reverse phase output n ′ (reverse control voltage Vn ′). Has been.

  In the second negative phase output unit, a P-channel MOS transistor Q52a configured in a current mirror relationship with the transistor Q32n in the first negative phase output unit, and an N configured in a current mirror relationship with the transistor Q32b in the differential unit. A channel MOS transistor Q52b, and a second negative phase output section. That is, the transistor Q32n of the first negative phase output unit and the transistor Q52a of the second negative phase output unit are connected to the current mirror in the same manner as the transistor Q32n and the transistor Q32o of the first negative phase output unit have a current mirror relationship. Configure the relationship. Similarly, the transistor Q32b in the differential section and the transistor Q52b in the second negative-phase output section are current-driven in the same manner as the transistor Q32b in the differential section and the transistor Q32p in the first negative-phase output section are in a current mirror relationship. Configure to mirror relationship.

  Thus, the second negative phase output unit is configured in the same manner as the output stage of the first negative phase output unit including the transistors Q32o and Q32p, and therefore, from the negative phase output n ′ of the second negative phase output unit. The reverse control voltage Vn ′ corresponding to the reverse control voltage Vn output from the reverse phase output n of the first reverse phase output unit can be output. The circuit composed of the transistors Q32m, Q32n, Q32o, and Q32p can correspond to the “constant voltage control direction pull-in circuit” described in the claims together with the transistors Q34 and Q42. The circuit formed by the transistors Q52a and Q52b can correspond to the remaining part of the “cut-off control direction pull-in circuit” recited in the claims. In FIG. 8, the broken line range denoted by reference numeral 50c is an assist circuit (cut-off control direction). It corresponds to the rest of the pull-in circuit.

  With this configuration, in the operational amplifier OP52, in addition to the positive phase output p corresponding to the output of the normal operational amplifier, the negative phase output n that can obtain an output having a reverse polarity independent of the normal phase output p, n ′ can be output (the output voltage by the negative phase output n is referred to as “reverse control voltage Vn”, and the output voltage by the negative phase output n ′ is referred to as “reverse control voltage Vn ′”). . Therefore, by connecting the anti-phase output n ′ out of the anti-phase outputs n and n ′ to the gate of the transistor Q54 described above, the microcomputer MC5 is brought into the sleep state from the operating state as described in [4] above. At the time of transition to the state, the positive phase output of the operational amplifier OP52 can be bypassed to the drive voltage Vcc side by the switching operation of the transistor Q54. Further, by connecting the negative-phase output n to the gate of the transistor Q34 described above, as described in [1] above, when the microcomputer MC5 transitions from the sleep state to the operation state, the switching operation of the transistor Q34 causes It becomes possible to bypass the positive phase output of the operational amplifier OP52 to the ground side. Note that the reverse phase output n ′ and the reverse control voltage Vn ′ can correspond to “another first control output” recited in the claims.

  [6] In the power supply circuit 50, the channel width W of the transistor Q52b constituting the operational amplifier OP52 is set to be smaller than the channel width W of the transistor Q52a constituting the operational amplifier OP52.

  That is, by setting the channel width Wb of the transistor Q52b and the channel width Wa of the transistor Q52a connected in series to the transistor Q32b to a relationship of Wb <Wa, as shown in FIG. Is different from the switching operation point Von 'in the case of the symmetric output (broken line shown in FIG. 9) so that the switching operation point Von of the transistor Q54 due to' is outside the movable region of the control voltage Vp. The moving input ΔV is set to increase.

  As a result, since the switching-on operation by the transistor Q54 is not performed within the movable region of the control voltage Vp by the operational amplifier OP52, the operation of the constant voltage supply unit 50a and the current sink unit 50b is not hindered. That is, during the period when the microcomputer MC5 transitions from the operating state to the sleep state, the switching operation by the transistor Q54 can be performed, and the positive phase output p of the operational amplifier OP52 can be bypassed to the drive voltage Vcc side.

  For this reason, as shown in FIG. 10, in the operating state of the microcomputer MC5, the control voltage Vp from the positive phase output p of the operational amplifier OP52 is controlled to a voltage (drive) that is controlled almost equal to the threshold voltage Vt of the transistor Q23. When the voltage Vcc is 5V, about 1V) is output. As described in the “Background Art” section, when the microcomputer MC5 is in the operating state, the operational amplifier OP32 allows the analog control of the transistor Q21 via the transistor Q22. This is because the transistor Q23 is controlled in the saturation region.

  When the microcomputer MC5 transitions to the sleep state from such an operating state, the transistor Q54 is turned off by the reverse control voltage Vn ′ output from the reverse phase output n ′ of the operational amplifier OP52 during the state transition period. Transition from operation to on operation. Therefore, since the positive phase output p of the operational amplifier OP52 is connected to the drive voltage Vcc side, the control voltage Vp is detected by the divided voltage of the resistor R25 and the resistors R26 and R27 (when the drive voltage Vcc is 5V, about 2V) is forcibly drawn in. As a result, even if the phase compensation circuit (C22, Q24) is connected to the positive phase output p of the operational amplifier OP52, the control voltage Vp is quickly changed to the detection voltage Vb by the divided voltage without being affected by the connection. Is possible.

  Therefore, as apparent from a comparison between FIG. 10 and FIG. 13, the delay of the output response due to the operational amplifier OP52 can be greatly improved, and the overshoot of the drive voltage Vcc due to the output response delay of the operational amplifier OP52 can be suppressed. (Inside the broken line ellipse indicated by γ in FIG. 10). Accordingly, since the drive voltage Vcc can be stably supplied by the drive voltage line + Vcc (power supply line), it is possible to prevent a failure of the microcomputer MC5 or the like that receives the supply of the drive voltage Vcc.

  As described above, in the power supply circuit 50 according to the second embodiment, the positive phase output p (control) is obtained by amplifying the error between the detection voltage Va based on the drive voltage Vcc of the drive voltage line + Vcc and the reference voltage Vr. The operational amplifier OP52 capable of outputting to the negative phase output n ′ (reverse control voltage Vn ′) independent of the voltage Vp) and the normal phase output p (control voltage Vp), and the negative phase output n ′ (reverse control voltage Vn ′). And an assist circuit 50c including a transistor Q54 that brings the positive phase output p (control voltage Vp) close to the sleep state potential Vb of the microcomputer MC5.

  Thus, during the period in which the positive phase output p (control voltage Vp) transitions from the operation state of the microcomputer MC5 to the sleep state, the transistor Q54 causes the positive phase output p (control voltage Vp) to be changed to the potential Vb of the sleep state. Therefore, the positive-phase output p (control voltage Vp) can quickly transition to the sleep state potential Vb of the microcomputer MC5 without being affected by the phase compensation circuit (C22, Q24). Become. Therefore, the overshoot (see FIG. 13) of the drive voltage Vcc of the drive voltage line + Vcc can be suppressed, so that the drive voltage Vcc can be stably supplied by the drive voltage line + Vcc and the microcomputer MC5 or the like receiving the drive voltage Vcc can be supplied. Failure can be prevented.

It is a circuit diagram showing an example of composition of a power circuit concerning a 1st embodiment of the present invention. It is a circuit diagram which shows the circuit example of the operational amplifier which comprises the constant voltage supply part of the power supply circuit which concerns on this 1st Embodiment. It is explanatory drawing which shows the output characteristic with respect to the differential input of the operational amplifier shown in FIG. It is explanatory drawing which shows operation | movement of the power supply circuit which concerns on this 1st Embodiment, and shows the fluctuation characteristics of the control voltages Vp and Vn and the drive voltage Vcc when a microcomputer changes from a sleep state to an operation state. It is a circuit diagram which shows the modification of the power supply circuit which concerns on 1st Embodiment of this invention. It is explanatory drawing which shows the operation | movement of the modification of the power supply circuit which concerns on this 1st Embodiment, and shows the fluctuation characteristics of the control voltage Vp and the drive voltage Vcc when a microcomputer changes from a sleep state to an operation state. It is a circuit diagram which shows the structural example of the power supply circuit which concerns on 2nd Embodiment of this invention. It is a circuit diagram which shows the circuit example of the operational amplifier which comprises the constant voltage supply part of the power supply circuit which concerns on this 2nd Embodiment. It is explanatory drawing which shows the output characteristic with respect to the differential input of the operational amplifier shown in FIG. It is explanatory drawing which shows operation | movement of the power supply circuit which concerns on this 2nd Embodiment, and shows the fluctuation characteristics of the control voltages Vp and Vn and the drive voltage Vcc when a microcomputer changes from an operation state to a sleep state. FIG. 11 is a circuit diagram illustrating a configuration example of a power supply circuit disclosed in Patent Document 1. It is explanatory drawing which shows operation | movement of the power supply circuit disclosed by patent document 1, and shows the fluctuation characteristics of the control voltage Vp and the drive voltage Vcc when a microcomputer changes from a sleep state to an operation state. It is explanatory drawing which shows operation | movement of the power supply circuit disclosed by patent document 1, and shows the fluctuation characteristics of the control voltage Vp and the drive voltage Vcc when a microcomputer changes to a sleep state from an operation state.

Explanation of symbols

30, 40, 50 ... power supply circuit 30a, 40a, 50a ... constant voltage supply section (first constant voltage circuit)
30b, 40b, 50b ... current sink (second constant voltage circuit)
30c, 40c, 50c ... assist circuit (constant voltage control direction pull-in circuit)
50d ... Assist circuit (cut-off control direction pull-in circuit)
C22: Capacitor (delay factor circuit)
C21, C23 ... Capacitor CV29 ... Constant voltage source D3 ... Diode Io ... Injection current Ix ... Load current n ... Reverse phase output (other first control output)
OP31 ... operational amplifier (second control means)
OP32 ... operational amplifier (first control means, constant voltage control direction pull-in circuit, error amplifier)
OP52 ... operational amplifier (first control means, cutoff control direction pull-in circuit, error amplifier)
p: Positive phase output (first control output)
Q21 ... Transistor (first step-down means)
Q24 ... Transistor (delay factor circuit)
Q22, Q23 ... transistor Q25 ... transistor (second step-down means)
Q34 ... Transistor (Constant voltage control direction pull-in circuit)
Q42 ... Transistor (Constant voltage control direction pull-in circuit)
Q54 ... Transistor (cut-off control direction pull-in circuit)
R21, R22, R23, R24, R25, R26, R27 ... Resistance T7, T9, T23, T25, T26 ... Terminal MC5 ... Microcomputer Va ... Detection voltage (control input)
Vb: detection voltage (second reference input, potential in the cutoff control output state)
VB: Battery voltage (first input voltage, second input voltage)
Vcc drive voltage (power line voltage)
Vn: reverse control voltage (other first control output)
Vp: Control voltage (first control output)
Vr: Reference voltage (first reference input)
Vs: Sink voltage (second control output)
Vt: Threshold voltage (potential in constant voltage control output state)
+ VB ... Battery voltage line + Vcc ... Drive voltage line (power supply line)

Claims (2)

A first control means capable of outputting a first control output based on a difference between a control input based on a voltage of the power supply line and a predetermined first reference input; and a voltage input from the outside with respect to the voltage of the power supply line A first step-down means capable of stepping down or shutting off a high first input voltage equally to the voltage of the power supply line according to the first control output, wherein the first control output can control step-down of the first input voltage; The voltage stepped down by the first step-down means can be output to the power supply line as the voltage of the power supply line during the period of the constant voltage control output state, and the first control output controls the interruption of the first input voltage. A first constant voltage circuit capable of shutting off the output to the power line during a possible shutoff control output state;
Second control means capable of outputting a second control output based on a difference between a first control output outputted by the first control means of the first constant voltage circuit and a predetermined second reference input; and According to the second control output, a second input voltage that is higher than the voltage of the power supply line is inputted during the period when the first step-down means of the constant voltage circuit is controlled to cut off the first input voltage. A second constant voltage circuit capable of outputting the voltage stepped down by the second step-down voltage unit to the power line as the voltage of the power line during the shut-off control;
A delay factor circuit capable of delaying transition of the first control output outputted by the first control means of the first constant voltage circuit between the constant voltage control output state and the cutoff control output state;
A power supply circuit comprising:
The first control output by the first constant voltage circuit transitions from the cutoff control output state to the constant voltage control output state, or the first control output by the first constant voltage circuit changes from the constant voltage control output state to the constant voltage control output state. Comprising an assist circuit that enables transition to a cutoff control output state without being affected by the delay factor circuit ;
The assist circuit includes the first control output during a period in which the first control output output from the first control means of the first constant voltage circuit transitions from the cutoff control output state to the constant voltage control output state. Is a constant voltage control direction pull-in circuit that pulls in the direction of the constant voltage control output state,
The constant voltage control direction pull-in circuit is
An error amplifier as the first control means, wherein an error between a control input based on the voltage of the power supply line and the predetermined first reference input is amplified, the first control output and the first control output An error amplifier capable of outputting to another first control output independent of
A power supply circuit comprising: a transistor that causes the first control output to approach the potential of the constant voltage control output state based on the other first control output . A first control means capable of outputting a first control output based on a difference between a control input based on a voltage of the power supply line and a predetermined first reference input; and a voltage input from the outside with respect to the voltage of the power supply line A first step-down means capable of stepping down or shutting off a high first input voltage equally to the voltage of the power supply line according to the first control output, wherein the first control output can control step-down of the first input voltage; The voltage stepped down by the first step-down means can be output to the power supply line as the voltage of the power supply line during the period of the constant voltage control output state, and the first control output controls the interruption of the first input voltage. A first constant voltage circuit capable of shutting off the output to the power line during a possible shutoff control output state;
Second control means capable of outputting a second control output based on a difference between a first control output outputted by the first control means of the first constant voltage circuit and a predetermined second reference input; and According to the second control output, a second input voltage that is higher than the voltage of the power supply line is inputted during the period when the first step-down means of the constant voltage circuit is controlled to cut off the first input voltage. A second constant voltage circuit capable of outputting the voltage stepped down by the second step-down voltage unit to the power line as the voltage of the power line during the shut-off control;
A delay factor circuit capable of delaying transition of the first control output outputted by the first control means of the first constant voltage circuit between the constant voltage control output state and the cutoff control output state;
A power supply circuit comprising:
The first control output by the first constant voltage circuit transitions from the cutoff control output state to the constant voltage control output state, or the first control output by the first constant voltage circuit changes from the constant voltage control output state to the constant voltage control output state. Comprising an assist circuit that enables transition to a cutoff control output state without being affected by the delay factor circuit ;
The assist circuit includes the first control output during a period in which the first control output output from the first control means of the first constant voltage circuit transitions from the constant voltage control output state to the cutoff control output state. Is a shutoff control direction pull-in circuit that pulls in the direction of the shutoff control output state,
The cutoff control direction pull-in circuit is
An error amplifier as the first control means, wherein an error between a control input based on the voltage of the power supply line and the predetermined first reference input is amplified, the first control output and the first control output An error amplifier capable of outputting to another first control output independent of
A power supply circuit comprising: a transistor that causes the first control output to approach the potential of the cutoff control output state based on the other first control output .

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