JP4569368B2 - Computer system, memory initialization method, and computer system program - Google Patents

Description

  The present invention relates to a computer system of a multiprocessor system including a plurality of processors and a plurality of memories, a memory initialization method, and a program.

  In general, a computer system often uses a DRAM as a main memory. However, since this DRAM does not guarantee data when the power is turned on, it is necessary to initialize the computer including a redundant code such as an ECC memory (Error Check and Correct memory) at the time of starting the computer.

Also, as a conventional technique for performing initialization, there is a technique in which a plurality of slave boards generate initialization data and initialize a circuit in response to an initialization command from a host board (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 2-64810

However, the main storage capacity of large-sized servers tends to increase year by year, and in such a server capable of mounting a large-capacity memory, memory initialization tends to take time when power is turned on.
That is, in the above-described conventional computer system, even if it is a symmetric multiprocessor system, one main boot processor determined by some means performs the initial processing of all main memories. As described above, since initialization processing is performed with a single processor processing capacity for a large-capacity memory, there is a problem in that the startup time of the system is delayed.

In the above-mentioned Patent Document 1, only initialization is shared by a plurality of slave boards, and memory initialization processing across packages is not performed based on the mounting state of the processor and memory in the package. It wasn't even taken up to do.
That is, in the memory access inside each package in which the processor and the memory are packaged in one package and in the memory access across the packages, the latter takes time for memory access. Focusing on this time difference, it has not been considered to speed up memory initialization.

  The present invention has been made in view of such a situation, and performs memory initialization by performing initialization processing for all memories that need to be initialized without performing memory initialization across packages. An object of the present invention is to provide a computer system, a memory initialization method, and a program that can increase the speed of the program.

  In order to achieve this object, a computer system according to a first aspect of the present invention includes a plurality of processors and a plurality of memories in one package, a plurality of such packages, a plurality of processors and a plurality of memories. A main boot processor included in any one of the plurality of packages at the time of starting the computer system; and a package other than the package including the main boot processor. On the other hand, when one of the processors included in the package is selected as a sub-boot processor, and the selected sub-boot processor receives a boot request, the memory included in the package including the sub-boot processor is initialized. The memory contained in other packages is not initialized To.

  For a package including the main boot processor described above, it is preferable that the main boot processor initializes the memory included in the package.

  For a package including the main boot processor described above, a sub-boot processor that initializes a memory included in the package may be selected separately from the main boot processor.

  The sub-boot processor described above preferably transmits a completion notice to the main boot processor when the initialization of the memory is completed, and the main boot processor executes the OS boot process after receiving the completion notice.

  The memory initialization method according to the second aspect of the present invention includes a plurality of processors and a plurality of memories in one package, a plurality of the packages, and a plurality of processors and a plurality of memories. A memory initialization method for a computer system, wherein when the computer system is started, a main boot processor included in any one of the plurality of packages has a package other than the package including the main boot processor. In contrast, a sub-boot processor selection step for selecting any of the processors included in the package as a sub-boot processor, and a sub-boot processor selected in the sub-boot processor selection step is a package containing the sub-boot processor. An initialization process for initializing the memory included in the In the initialization step, the sub-activation processor, characterized in that does not perform the initialization of the memory in the package other than the package that contains the sub-activation processor.

  In the sub-boot processor selection step, no sub-boot processor other than the main boot processor is selected for the package containing the main boot processor, and in the initialization step, the memory contained in the package is stored in the main boot processor. It is preferred that the boot processor initialize.

  In the sub-boot processor selection step described above, a sub-boot processor that initializes a memory included in the package may be selected separately from the main boot processor for a package including the main boot processor.

  After the initialization of the memory is completed in the above-described initialization process, the sub-boot processor transmits a completion notice to the main boot processor, and the OS boot process is performed after the main boot processor receives the completion notice. It is preferable to include an OS startup process to be executed.

  The computer system program according to the third aspect of the present invention includes a plurality of processors and a plurality of memories in one package, a plurality of the packages, and a plurality of processors and a plurality of memories. In the computer system, during the startup process of the computer system, the main boot processor included in any one of the plurality of packages is associated with each package other than the package including the main boot processor. The sub-boot processor selection process for selecting one of the processors included in the package as the sub-boot processor, and the sub-boot processor selected in the sub-boot processor selection process are included in the package including the sub-boot processor. Note that memory is initialized and included in other packages Initialization process and that does not perform initialization of, characterized in that to the execution.

  In the sub-boot processor selection process described above, no sub-boot processor other than the main boot processor is selected for the package including the main boot processor, and in the initialization process described above, the memory included in the package is stored in the main boot processor. It is preferred that the boot processor initialize.

  In the sub-boot processor selection process described above, for a package including the main boot processor, a sub-boot processor that initializes the memory included in the package may be selected separately from the main boot processor.

  After the initialization of the memory is completed by the above-described initialization process, a completion notification transmission process in which the sub activation processor transmits a completion notification to the main activation processor, and the OS is activated after the main activation processor receives the completion notification. It is preferable to execute the OS boot process.

  As described above, according to the present invention, the memory initialization process is speeded up by performing the initialization process on all the memories that need to be initialized without performing the memory initialization across the packages. And the startup time can be shortened.

Next, an embodiment in which a computer system, a memory initialization method, and a program according to the present invention are applied to a multiprocessor system will be described in detail with reference to the drawings.
The multiprocessor system of the present embodiment exemplifies a suitable system that can shorten the initialization time by performing the memory initialization process at the time of system startup in consideration of the system mounting format.

  As shown in FIG. 1, a multiprocessor system (1) according to an embodiment of the present invention includes MCPs 0 to 3 as a multichip package (hereinafter referred to as MCP) in which a plurality of processors and memories are packaged, and each MCP. Are connected via the MCP connection (100).

  As the storage unit (memory) of each MCP, for example, a DRAM or the like that requires initialization when the system is started is used. Therefore, when the system is activated, all main storage units (MMU00-02, MMU10-11, MMU20-22, MMU30-33) are initialized.

In the multiprocessor system according to the present embodiment, initialization of these MMUs (main memory units) is performed in parallel by the processors CPU00 (1010), CPU10 (2010), CPU20 (3010), and CPU30 (4010), thereby achieving high speed. Initialize memory.
At this time, it is assumed that each of the CPUs described above is responsible for initializing the MMU under the multichip package (hereinafter referred to as MCP) to which the CPU belongs. This is because, generally, memory access within the same MCP can be performed at a higher speed than access to other MCP memories.
In the example illustrated in FIG. 1 of the present embodiment, the CPU 10 (2010) is responsible for initialization of the MMU 10 (2020) and the MMU 11 (2021).

  In the multiprocessor system (1) of the present embodiment, as shown in FIG. 1, a multi-chip package (hereinafter referred to as MCP) system is adopted, and a plurality of packages (10, 20, 30, 40) mounted with a plurality of processors are used. Are connected to each other to realize a multiprocessor system.

Specifically, the multi-chip package MCP0 (10) has four processors, CPU00 (1010), CPU01 (1011), CPU02 (1012), and CPU03 (1013), and the main memory is MMU00 ( 1020), MMU01 (1021), and MMU02 (1022). A plurality of MCPs having a plurality of processors and a plurality of MMUs are connected by an inter-MCP connection mechanism (100), and the multiprocessor system according to the present embodiment is configured as a whole.
In the example of FIG. 1, four MCPs equipped with four processors are combined to form a 16-processor multiprocessor system as a whole.

Next, the operation of this embodiment will be described in detail with reference to FIG.
In this embodiment, in order to shorten the time of the memory initialization process, the memory clear process is performed not only by the main activation processor but also by other processors. Here, which processor initializes which main storage area Is a problem.

  In general, in the computer as shown in FIG. 1, the access time from the processor in each MCP to the main memory in the same MCP and the access time from the processor in one MCP to the main memory installed in another MCP are as follows. The latter takes more time.

  Therefore, in this embodiment, the main boot processor (Bootstrap-Processor) selects and defines one sub-boot processor (Sub-Bootstrap-Processor) in each MCP, and the main memory (MMU) under each MCP It is assumed that initialization processing is performed by the main boot processor or the sub boot processor defined in the MCP.

  Specifically, the MMUs 10 to 11 (2020, 2021) mounted on the MCP1 (20) are initialized by the CPU 10 (2010), which is a sub-activation processor of the MCP1 (20), and similarly the MCP2 (30). Then, the CPU 20 (3010), and the CPU 30 (4010) in the MCP3 (40) initializes the memory in each included MCP.

In addition, MMU00-02 (1020, 1021, 1022) mounted on MCP0 (10) is initialized by CPU00 (1010) which is a main activation processor included in MCP0 (10).
In other words, in the MCP including the main activation processor, the main activation processor itself also serves as a sub activation processor.

  With this configuration, memory clear processing across MCPs is not performed, and the selected main boot processor or sub-boot processor only performs initialization processing by memory access inside the MCP, thereby reducing memory initialization time. It becomes possible.

The operation of this embodiment will be described in the order of processor startup with reference to the flowchart of FIG.
In the operation example of FIG. 2, the CPU 00 (1010) is given as an example of the processor selected as the main startup processor, and the CPU 10 (2010) is given as an example of the processor selected as the sub startup processor. CPU11 (2011) is mentioned.

After power-on (steps S10, S20, and S30), first, even in a symmetric multiprocessor system, a main activation processor is usually selected for processing such as a loader (step S11).
The selection of the main boot processor is to define any one processor included in the multiprocessor system as the main embodiment as the main boot processor, and generally the lowest processor ID uniquely assigned to the system. Often.

In the configuration example of FIG. 1, it is assumed that the CPU 00 (1010) on the MCP 0 is selected as the main activation processor.
On the other hand, the processor not selected as the main activation processor waits for the boot rendezvous (steps S21 and S31).

  Next, the CPU 00, which is the main activation processor, checks the mounting state of the processor and memory included in the system (step S12). Such mounting state information can be obtained by accessing information provided from the BIOS or directly accessing the hardware.

Based on the obtained information, the main boot processor selects one parent processor on each MCP, that is, a sub-boot processor that is one processor that performs MMU initialization in each MCP, and issues a boot request. (Steps S13 and S23).
In this selection of the sub-boot processor, any one processor included in each MCP other than the MCP including the main boot processor is defined as a sub-boot processor. It is simple that the processor ID assigned uniquely is the youngest number. For the MCP including the main activation processor, the main activation processor also serves as the sub activation processor, so that a new sub activation processor is not defined.

The sub-activation processor that has received the activation request initializes the MMU under the MCP to which it belongs (step S24).
After completion of the initialization process, each sub-boot processor issues an initialization process completion notice to the main boot processor (step S25), and waits for the boot rendezvous again until it is started as an OS (Operating System) (step S26). .

  Specifically, taking MCP1 in FIG. 1 as an example, CPU 10 is selected as a sub-boot processor, completes initialization of MMU 10 and MMU 11, and issues initialization process completion notification to CPU 00, which is the main boot processor. To do. After the completion notification is issued, the boot rendezvous wait state is entered again until the OS is started.

  On the other hand, the main activation processor that activated the sub-activation processor initializes the memory unit under its MCP (step S14). That is, the main boot processor also serves as a sub-boot processor in the MCP to which the main boot processor belongs, and in the example of FIG. 1, the CPU 00 is responsible for initialization processing of the MMU 00, MMU 01, and MMU 02. .

  The main boot processor that has completed the initialization process in the MCP to which it belongs confirms the completion notification from each sub-boot processor that has shared the processing (step S15). If the completion notification is not received for a certain period of time, error processing is performed separately.

When the memory initialization completion notification is received from all the sub-boot processors, normal system startup processing is performed (step S16). When all the processors are ready to boot, the boot rendezvous state release notification is sent to all processors. Is issued (step S17), and startup by a normal operating system is performed (steps S27 and S37). Note that the CPU 11 that does not perform initialization processing is activated for the first time at this time.
Thereafter, the normal OS operation state is transitioned (step S8).

As described above, according to the multiprocessor system of the above-described embodiment, the memory initialization processing is distributed according to the processor mounted on the MCP and the mounting format of the memory, so that the memory access latency of the platform is taken into consideration. Memory initialization processing can be realized.
That is, all memory (MMUs) that need to be initialized only by memory access within the MCP, without performing memory initialization across the MCP, based on the mounting format of the processor and memory mounted in each MCP. Initialization processing can be performed on the device.
As a result, even if the memory mounted in the multiprocessor system has a large capacity, it can be initialized at high speed. As a result, the system startup process can be speeded up and the startup time can be shortened.

[Other Embodiments]
Next, a multiprocessor system as another embodiment of the present invention will be described.
In the above-described embodiment, the main activation processor performs activation of the sub activation processor in the other MCP, confirmation of completion notification, and initialization of the memory under the MCP0 (10) to which the main activation processor belongs. In other embodiments, in order to prevent the processing of the main boot processor from becoming complicated, the role of the main boot processor is <1> activation of the sub-boot processor and confirmation of completion notification <2> subordinate to the MCP to which the user belongs. Dividing into memory initialization processing, the main boot processor processing is simplified.

That is, in another embodiment described here, the main activation processor is responsible only for the process <1>, and the sub-activation processor is also selected for the MCP0 (10) and is responsible for the process <2>. I try to let them.
As a result, the memory initialization process and the completion notification confirmation process by the main activation processor can be made special only by MCP0, and the system can be simplified and simplified.

  The operation in this other embodiment will be described with reference to the flowchart of FIG. The same operations as those in the flowchart of FIG. 2 described above are denoted by the same reference numerals, and description thereof is omitted.

  When the main activation processor acquires the mounting state information of the processor and memory included in the system (step S12), based on the obtained information, one of the processors on each MCP, that is, the MMU initial stage in each MCP The sub-activation processor that is one processor that performs the conversion is selected for all MCPs including the MCP including the main activation processor, and an activation request is transmitted to the selected sub-activation processor (steps S43 and S53). .

The sub-activation processor that has received the activation request initializes the MMU under the MCP to which it belongs (step S54).
After completion of the initialization process, each sub-boot processor issues an initialization process completion notice to the main boot processor (step S55), and waits for the boot rendezvous again until the OS is booted (step S26).

As still another embodiment of the present invention, the memory in the MCP is divided by the number of installed processors, and each installed processor functions as a sub-boot processor in each of the above-described embodiments, and performs memory initialization processing in parallel. It is good as well.
In the example of FIG. 1, this means that MMU 30, MMU 31, MMU 32, and MMU 33 are divided and cleared by four processors on MCP 3.
In this case as well, memory clear (initialization) across MCPs can be prevented, and the memory initialization can be further speeded up.

Each of the above-described embodiments is a preferred embodiment of the present invention, and the present invention is not limited to this, and various modifications can be made based on the technical idea of the present invention.
For example, by recording the processing procedure for realizing the multiprocessor system as each embodiment described above as a program on a recording medium, the above-described functions according to each embodiment of the present invention are supplied from the recording medium. The program can be realized by causing a CPU of a computer constituting the system to perform processing.
In this case, the present invention can be applied even when an information group including a program is supplied to the output device from the above recording medium or from an external recording medium via a network.
That is, the program code itself read from the recording medium realizes the novel function of the present invention, and the recording medium storing the program code and the signal read from the recording medium constitute the present invention. It will be.
As this recording medium, for example, a floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD-R, magnetic tape, nonvolatile memory card, ROM, EEPROM, or the like may be used.

  According to the program according to the present invention, each function in the multiprocessor system as each embodiment according to the present invention described above can be realized in the computer system controlled by the program.

It is a figure which shows the structural example of the multiprocessor system as embodiment of this invention. It is a flowchart which shows the memory initialization operation | movement of this multiprocessor system. It is a flowchart which shows the memory initialization operation | movement with the package containing the main starting processor in the multiprocessor system as other embodiment.

Explanation of symbols

1 Multiprocessor system 10, 20, 30, 40 MCP (multi-chip package)
1010-1013, 2010-102013, 3010-3013, 4010-4013 CPU (processor)
1020-1022, 2020-2021, 3020-3020, 4020-4023 MMU (Main Memory Unit)

Claims (12)

A computer system comprising a plurality of processors and a plurality of memories in one package, a plurality of the packages, and a plurality of processors and a plurality of memories,
When starting the computer system,
The main boot processor included in any one of the plurality of packages selects one of the processors included in the package as a sub boot processor for each package other than the package including the main boot processor. And
When the selected sub-boot processor receives a boot request, it initializes the memory included in the package including the sub-boot processor, and does not initialize the memory included in the other package. calculation system shall be the. Wherein for the packages included main activation processor computer system according to claim 1, wherein the memory included in the package the main activation processor, wherein the initializing. The main For activation packages included processor computer system according to claim 1, wherein the sub-activation processor for initializing the memory contained in the package separately selected from the main activation processor. When the initialization of the memory is completed, the sub-boot processor sends a completion notification to the main boot processor,
The main activation processor after receiving the completion notification, the computer system according to any one of claims 1 to 3, characterized in that executing the OS startup process. A memory initialization method in a computer system in which a plurality of processors and a plurality of memories are packaged, the plurality of the packages are provided, and the plurality of processors and the plurality of memories are provided.
When starting the computer system,
The main boot processor included in any one of the plurality of packages selects one of the processors included in the package as a sub boot processor for each package other than the package including the main boot processor. A sub-boot processor selection step,
The sub-boot processor selected in the sub-boot processor selection step includes an initialization step of initializing a memory included in a package including the sub-boot processor,
In the initialization step, the sub-activation processor, features and be Rume Mori initialization method that does not perform the initialization of the memory in the package other than the package that contains the sub-activation processor. In the sub-boot processor selection step, a sub-boot processor other than the main boot processor is not selected for the package including the main boot processor,
6. The memory initialization method according to claim 5, wherein in the initialization step, the main boot processor initializes a memory included in the package. The sub-boot processor selection step selects a sub-boot processor that initializes a memory included in the package separately from the main boot processor for a package including the main boot processor. 6. The memory initialization method according to 5 . A completion notification transmission step in which the sub activation processor transmits a completion notification to the main activation processor after the initialization of the memory is completed in the initialization step;
The main activation processor memory initialization method according to any one of claims 5 7, characterized in that a OS startup step of executing an OS boot process after receiving the completion notification. A computer system including a plurality of processors and a plurality of memories in one package, a plurality of the packages, and a plurality of processors and a plurality of memories.
During the startup process of the computer system,
The main boot processor included in any one of the plurality of packages selects one of the processors included in the package as a sub boot processor for each package other than the package including the main boot processor. Sub-boot processor selection processing to
Initial sub activation processor selected in the previous SL sub activation processor selection process, a memory that is included in the package that contains the sub activation processor initializes and does not initialize the memory that is included in another package calculation system program you characterized in that to execute a process, the. In the sub-boot processor selection process, a sub-boot processor other than the main boot processor is not selected for the package including the main boot processor,
10. The computer system program according to claim 9, wherein in the initialization process, the main boot processor initializes a memory included in the package. The sub-boot processor selection process selects a sub-boot processor that initializes a memory included in the package, separately from the main boot processor, for a package including the main boot processor. 9. The computer system program according to 9 . A completion notification transmission process in which the sub activation processor transmits a completion notification to the main activation processor after the initialization of the memory is completed in the initialization process;
The computer system program according to any one of claims 9 to 11 , wherein the main boot processor executes an OS boot process for booting an OS after receiving the completion notification.

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