CN114253749A - Interaction method and device, electronic equipment and storage medium - Google Patents

Interaction method and device, electronic equipment and storage medium Download PDF

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Publication number
CN114253749A
CN114253749A CN202210174241.2A CN202210174241A CN114253749A CN 114253749 A CN114253749 A CN 114253749A CN 202210174241 A CN202210174241 A CN 202210174241A CN 114253749 A CN114253749 A CN 114253749A
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Prior art keywords
host
shared memory
bmc
interaction
memory
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Inventor
杨少俊
王兵
金立江
李道童
罗鹏芳
曲勇
胡雁
张秀波
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G06F15/17331—Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/54—Indexing scheme relating to G06F9/54
    • G06F2209/547—Messaging middleware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/54—Indexing scheme relating to G06F9/54
    • G06F2209/548—Queue

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Storage Device Security (AREA)

Abstract

The application discloses an interaction method, an interaction device, an electronic device and a computer readable storage medium, wherein the method comprises the following steps: enabling an H2B device, and distributing a shared memory for the interaction of the host and the BMC; locking the shared memory after the host initializes the H2B device and before loading the operating system; when an interaction request sent by the host is received, starting the shared memory so that the host and the BMC can interact through the shared memory; and after receiving an interaction completion notification sent by the host, re-locking the shared memory. The method and the device realize interaction of characteristics such as high transmission speed, strong safety mechanism, strong compatibility, good stability and the like between the Host and the BMC based on the H2B equipment.

Description

Interaction method and device, electronic equipment and storage medium
Technical Field
The present application relates to the field of computer technologies, and in particular, to an interaction method, an interaction apparatus, an electronic device, and a computer-readable storage medium.
Background
On a server, there is a lot of interaction between a Host and a BMC (Baseboard Management Controller), and under the trend that the server functions are more and more powerful, and the requirements for manageability, usability, stability and serviceability are more and more high, the requirements for the interaction interface between the Host and the BMC are also more and more high.
The IPMI (Intelligent Platform Management Interface) is an open free industrial standard, is a classic server Management Interface, and has wide application, good compatibility and stability. On the server, Host and BMC have a lot of interaction through IPMI interface. The performance and the safety of the IPMI interface directly influence the usability and the safety of the server, and further influence the usability and the safety of a data center and the whole service.
In the related art, there is a problem that a security mechanism of interaction between the Host and the BMC is weak, and therefore, how to improve security of interaction between the Host and the BMC is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The application aims to provide an interaction method, an interaction device, an electronic device and a computer readable storage medium, and the interaction of the characteristics of high transmission speed, strong security mechanism, strong compatibility, good stability and the like between a Host and a BMC is realized.
In order to achieve the above object, the present application provides an interaction method applied to BMC, the method including:
enabling an H2B device, and distributing a shared memory for the interaction of the host and the BMC;
locking the shared memory after the host initializes the H2B device and before loading the operating system;
when an interaction request sent by the host is received, starting the shared memory so that the host and the BMC can interact through the shared memory;
and after receiving an interaction completion notification sent by the host, re-locking the shared memory.
The host initializes the H2B device, enables a target MMIO resource in a decoder, enables the H2B device to access a link, allocates BUS resources and the target MMIO resource for the H2B device, and enables the H2B device.
Wherein, after the host initializes the H2B device, the PPI and Lib of the H2B device are installed in the PEI phase, and the Protcol and Lib of the H2B device are installed in the DXE phase.
After the shared memory is allocated for the interaction between the host and the BMC, the method further includes:
mapping the shared memory to a first target interface of the H2B device, so that the host accesses the shared memory through the first target interface.
Wherein, the host and the BMC interact through the shared memory, including:
the host stores target data to the shared memory through the first target interface, and the BMC acquires the target data from the shared memory.
After the host stores the target data to the shared memory through the first target interface, the method further includes:
the host accesses a message queue mechanism of the H2B device through a second target interface to send an interrupt signal to the BMC;
correspondingly, the obtaining, by the BMC, the target data from the shared memory includes:
and when the BMC receives the interrupt signal, acquiring the target data from the shared memory.
Wherein, still include:
in the operating stage of the operating system, when an interactive authentication request sent by the host is received, authenticating the interactive authentication request, and after the authentication is passed, starting the shared memory so that the host and the BMC can interact through the shared memory;
and after receiving an interaction completion notification sent by the host, re-locking the shared memory.
In order to achieve the above object, the present application provides an interactive device applied to BMC, the device comprising:
the enabling module is used for enabling the H2B equipment and distributing a shared memory for the interaction of the host and the BMC;
a first locking module, configured to lock the shared memory after the host initializes the H2B device and before an operating system is loaded;
the first starting module is used for starting the shared memory when receiving an interaction request sent by the host so as to facilitate the interaction between the host and the BMC through the shared memory;
and the second locking module is used for re-locking the shared memory after receiving the interaction completion notification sent by the host.
To achieve the above object, the present application provides an electronic device including:
a memory for storing a computer program;
a processor for implementing the steps of the above-described interaction method when executing the computer program.
To achieve the above object, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when being executed by a processor, realizes the steps of the above-mentioned interaction method.
According to the scheme, the interaction method provided by the application comprises the following steps: enabling an H2B (Host to BMC Device) Device, and distributing a shared memory for the interaction of the Host and the BMC; locking the shared memory after the host initializes the H2B device and before loading the operating system; when an interaction request sent by the host is received, starting the shared memory so that the host and the BMC can interact through the shared memory; and after receiving an interaction completion notification sent by the host, re-locking the shared memory.
This application realizes one kind based on H2B equipment fast, stability is good, it is simple to realize, high durability and easy use, the available time is early, the coupling is low, the interface is unified with the storage and shared memory capacity is big, the interactive interface that the security is good, and then both overcome traditional IPMI interactive interface speed slow, the weak shortcoming of safety protection mechanism, it is high to overcome the coupling that exists in other interfaces again, do not have shared memory, or shared memory is little, can't realize the safety mechanism, it is complicated to realize, the available time is late, poor stability, the not high grade shortcoming of speed, it is fast to have realized transmission speed between Host and the BMC, the safety mechanism is strong, compatibility is strong, the interaction of characteristics such as stability is good. The application also discloses an interaction device, an electronic device and a computer readable storage medium, which can also realize the technical effects.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts. The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
FIG. 1 is a flow chart illustrating an interaction method in accordance with an exemplary embodiment;
FIG. 2 is a schematic diagram illustrating an interaction flow between a Host and a BMC according to an example embodiment;
FIG. 3 is a block diagram illustrating an interactive device in accordance with an exemplary embodiment;
FIG. 4 is a block diagram illustrating an electronic device in accordance with an exemplary embodiment.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. In addition, in the embodiments of the present application, "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a specific order or a sequential order.
The embodiment of the application discloses an interaction method, which realizes the interaction of the characteristics of high transmission speed, strong safety mechanism, strong compatibility, good stability and the like between Host and BMC.
Referring to FIG. 1, a flowchart illustrating an interaction method according to an exemplary embodiment is shown, as shown in FIG. 1, including:
s101: enabling an H2B device, and distributing a shared memory for the interaction of the host and the BMC;
the H2B device is a PCI (Peripheral Component Interconnect) device in the BMC, can be used for Host and BMC interaction, and is disabled by default, and needs BMC enabling. When the BMC is started, the H2B device Driver is executed, the H2B device is enabled, and a section of DRAM (Dynamic Random Access Memory) is allocated, that is, a shared Memory in the DRAM of the BMC is provided to the Host, and the size of the allocated DRAM can be determined according to the requirement. After the BMC is enabled, the distributed DRAMs are mapped to Bar0 (a first target interface) of H2B and are accessed by a Host section, the Host end accesses the distributed DRAMs through the Bar0 of the H2B device, and interaction between the Host and the BMC is carried out in a BMC-sharing DRAM mode. That is, after allocating a shared memory for the interaction between the host and the BMC, mapping the shared memory to a first target interface of the H2B device, so that the host accesses the shared memory through the first target interface.
Further, the host initializes the H2B device, enables a target MMIO resource in a decoder, enables an H2B device to access a link, allocates BUS resources and the target MMIO (Memory Mapped IO, i.e., IO device Mapped in a Memory address space) resources for the H2B device, and enables the H2B device. In a specific implementation, the BIOS (Basic Input Output System) in the host initializes the H2B device: after Host is started, BIOS initializes H2B device in the initial stage of starting. Enabling a decoder of MMIO resource segment to be allocated, enabling PCI/PCIE equipment to access, allocating BUS and MMIO resources for H2B equipment, and enabling H2B equipment.
After the host initializes the H2B device, the PPI and Lib of the H2B device are installed in a PEI (Pre-EFI Initialization) phase, and the proccol (network data exchange rule) and Lib of the H2B device are installed in a DXE (Driver Execution Environment) phase. As shown in FIG. 2, the BMC automatically enables and initializes the H2B device, the host installs H2B PPI in the PEI phase for each module call of PEI to interact with BMC, and provides Lib (static library) used in the PEI phase for each module call of PEI phase to interact with BMC. Then entering DXE phase: protcol of types such as DXE, SMM (System Management Mode), Runtime and the like is installed for various types of module calls to interact with BMC, and Lib of types such as DXE, SMM, Runtime Base and the like is installed for various types of module calls to interact with BMC.
S102: locking the shared memory after the host initializes the H2B device and before loading the operating system;
in a specific implementation, H2B is locked before entering an OS (operating System) to protect data in the H2B shared memory from leakage and tampering.
S103: when an interaction request sent by the host is received, starting the shared memory so that the host and the BMC can interact through the shared memory;
the H2B device supports a Messages Queue mechanism, and the Host side accesses the interaction mechanism of Messages Queue and BMC of H2B through Bar1 (second target interface) of the H2B device. In the starting stage, before the BIOS interacts with the BMC, Shared Memory access of the H2B device is started through the Messages Queue of the H2B device, and the host interacts with the BMC through the Shared Memory.
As a possible implementation, the interacting between the host and the BMC through the shared memory includes: the host stores target data to the shared memory through the first target interface, and the BMC acquires the target data from the shared memory. For general big data, the host directly stores the target data into the shared memory through the first target interface, and the BMC acquires the target data from the shared memory.
As another possible implementation, after the host stores the target data in the shared memory through the first target interface, the method further includes: the host accesses a message queue mechanism of the H2B device through a second target interface to send an interrupt signal to the BMC; correspondingly, the obtaining, by the BMC, the target data from the shared memory includes: and when the BMC receives the interrupt signal, acquiring the target data from the shared memory. The Messages Queue mechanism supports an interrupt mechanism, and can realize real-time communication. In order to keep the communication effectiveness and reduce the communication burden of the BMC, an interrupt mode is selected for realization, and a polling mode is not adopted. Since H2B Shared Memory does not support interrupts, it is typically used for asynchronous transmissions. For information requiring real-time interaction, the real-time interaction mechanism of H2B Shared Memory can be realized by using the interruption of the H2B Messages Queue mechanism. After the Host end puts data into the H2B Shared Memory, the BMC is notified through an H2B Messages Queue mechanism, the Message mechanism notifies the BMC through interruption, and after the BMC receives an interruption signal, the Messages are analyzed to know that the H2B Shared Memory has data sent by the Host end to be processed, namely, the data in the H2B Shared Memory is processed, so that the purpose of real-time communication is achieved. And vice versa, the data communication from the BMC to the Host end is also realized.
S104: and after receiving an interaction completion notification sent by the host, re-locking the shared memory.
In particular implementations, after the interaction is complete, the H2B Shared Memory is closed by H2B Messages Queue.
Further, this embodiment further includes: in the operating stage of the operating system, when an interactive authentication request sent by the host is received, authenticating the interactive authentication request, and after the authentication is passed, starting the shared memory so that the host and the BMC can interact through the shared memory; and after receiving an interaction completion notification sent by the host, re-locking the shared memory. When the OS needs to interact with the BMC, if an interaction authentication request needs to be sent to the BMC in an out-of-band manner, such as Ipmi or Lan, as shown in fig. 2, an authentication procedure needs to be executed first, after the authentication is passed, the BMC opens an H2B Shared Memory channel, and the communication can be performed, and after the communication is completed, the BMC is notified out-of-band to lock the H2B Shared Memory and re-enter the protection mode. The BMC can also set the life cycle of the interface, and automatically close the interface when the life cycle of the interface is used up.
Further, the embodiment also supports an H2B Shared Memory content automatic unloading and recovering mechanism: the H2B Shared Memory is divided into several areas, each area has an Updated Flag to indicate whether the area data has been Updated. The BMC sets a periodic task, polls the Updated Flag, when the Updated Flag is set, transfers the data of the area to the nonvolatile memory, and clears the Updated Flag. For key data, after the data is stored in the H2B Shared Memroy, the BMC is informed of the readiness of the data through an H2B Messages Queue mechanism, and after receiving the notification, the BMC transfers the data to the nonvolatile memory except for processing the data. When the system is powered down, data in the BMC DRAM may be lost. After powering up again, the BMC restores the data stored in the nonvolatile Memory to the H2B Shared Memory.
The prior technical scheme has various defects and has the following main defects: slow transmission speed, poor compatibility, late availability stage, poor stability, weak security mechanism and the like. Specific comparative data are shown in table 1:
TABLE 1
Scheme(s) Shared memory content Measurement of Coupling of Property of (2) Speed of transmission Degree of rotation Available stage Segment of Security mechanism Complexity of Degree of rotation Stabilization Property of (2)
Ipmi Over SRAM (this implementation) Example) Small Is free of Fast-acting toy Early stage Is provided with Is low in Good taste
Ipmi Over USB Is free of Is free of Is quicker Night Is provided with Height of Is preferably used
Ipmi Over Kcs Is free of Is free of Slow Early stage Weak (weak) Is low in Good taste
Ipmi over BT Is free of Is free of Is quicker Early stage Weak (weak) Is low in Good taste
Ipmi Over SSIF Is free of Is free of Slow Earlier in time Weak (weak) Is low in Difference (D)
Ipmi Over SMIC Is free of Is free of Slow Earlier in time Weak (weak) Is low in Good taste
SRAM scheme Small Is free of Fast-acting toy Early stage Is provided with Is lower than Good taste
Shared Video Memory Big (a) Is provided with Fast-acting toy Early stage Because of the coupling with the Video function, the secure machine cannot be realized System for making Is lower than Good taste
Lan Over USB Is free of Is free of Is quicker Night Is provided with Height of Is preferably used
Wherein, Ipmi Over Kcs: the IPMI protocol is realized on an Kcs interface, IO port transmission is used, the speed is low, and the protection mechanism is weak. Ipmi Over BT: the IPMI protocol is realized on the BT interface, the IO port transmission is used, the block transmission is supported, the speed is high, and the protection mechanism is weak. Ipmi Over SSIF: the IPMI protocol is realized on the Smbus interface, the stability is poor, and the speed is low. Ipmi Over SMIC: the use is less, the support of a single chip is needed, the IO transmission is used, and no obvious advantage exists. Ipmi Over USB: the IPMI protocol is realized on the USB interface, the transmission speed is high, the compatibility and the stability are poor, the IPMI protocol can be used only after the initialization of the USB drive is completed, and the available stage is late. The SRAM interaction scheme is as follows: the SRAM (Static Random-Access Memory) of the BMC (baseboard management controller) is a Static Memory which is arranged in the BMC and can be directly accessed from a CPU (central processing unit) end through MMIO (monolithic integrated input/output) to serve as an interaction channel between the Host and the BMC, the transmission speed is high, frequent change is needed, and the shared Memory capacity is small. Share Video Memory interaction scheme: the interactive interface is coupled with the Video function, so that the interactive interface cannot be used under the condition of closing the Video function, and the Video function cannot be used under the condition of locking the interactive interface, so that a safety mechanism cannot be realized. Lan Over USB: the implementation is complex, a large number of drivers are needed to support, the interactive interface function is complex, the number of layers of the Driver Stack is too many, the interactive efficiency is not high, and the interface can be enabled only after the drivers of each layer are executed at the initial stage of the startup of the computer because a large number of Driver Stack layers are needed to support.
The embodiment of the application realizes one kind fast based on H2B equipment, the stability is good, the realization is simple, the use is simple, the available time is early, the coupling is low, the interface and the storage are unified, the shared memory capacity is large, the interactive interface with good safety, and then the defects of low speed and weak safety protection mechanism of the traditional IPMI interactive interface are overcome, the defects of high coupling, no shared memory or small shared memory existing in other interfaces are overcome, the safety mechanism cannot be realized, the realization is complex, the available time is late, the stability is poor, the speed is not high and the like, and the interaction of the characteristics of high transmission speed, strong safety mechanism, strong compatibility, good stability and the like between the Host and the BMC is realized. Therefore, the interaction speed, safety and efficiency of the Host and the BMC are improved. This increases the boot speed of the server, increasing the availability and serviceability of the server. Because the communication is safer, the safety of the server is improved, and the safe and stable operation of the server is guaranteed. Because the compatibility is good, the universality is strong, the interface can be used in an iterative way after being realized, and the maintenance cost is reduced.
In the following, an interactive device provided by an embodiment of the present application is introduced, and an interactive device described below and an interactive method described above may be referred to each other.
Referring to fig. 3, a block diagram of an interactive apparatus according to an exemplary embodiment is shown, as shown in fig. 3, including:
an enabling module 301, configured to enable an H2B device, and allocate a shared memory for interaction between the host and the BMC;
a first locking module 302, configured to lock the shared memory after the host initializes the H2B device and before an operating system is loaded;
a first starting module 303, configured to start the shared memory when receiving an interaction request sent by the host, so that the host and the BMC interact with each other through the shared memory;
a second locking module 304, configured to lock the shared memory again after receiving the interaction completion notification sent by the host.
The embodiment of the application realizes one kind fast based on H2B equipment, the stability is good, the realization is simple, the use is simple, the available time is early, the coupling is low, the interface and the storage are unified, the shared memory capacity is large, the interactive interface with good safety, and then the defects of low speed and weak safety protection mechanism of the traditional IPMI interactive interface are overcome, the defects of high coupling, no shared memory or small shared memory existing in other interfaces are overcome, the safety mechanism cannot be realized, the realization is complex, the available time is late, the stability is poor, the speed is not high and the like, and the interaction of the characteristics of high transmission speed, strong safety mechanism, strong compatibility, good stability and the like between the Host and the BMC is realized.
On the basis of the above embodiment, as a preferred implementation, the host initializes the H2B device, enables a target MMIO resource in a decoder, enables the H2B device to access a link, allocates a BUS resource and the target MMIO resource for the H2B device, and enables the H2B device.
Based on the above embodiment, as a preferred implementation, after the host initializes the H2B device, the PPI and Lib of the H2B device are installed in the PEI phase, and the Protcol and Lib of the H2B device are installed in the DXE phase.
On the basis of the above embodiment, as a preferred implementation, the method further includes:
a mapping module, configured to map the shared memory to a first target interface of the H2B device, so that the host accesses the shared memory through the first target interface.
On the basis of the foregoing embodiment, as a preferred implementation manner, the host stores target data to the shared memory through the first target interface, and the BMC acquires the target data from the shared memory.
Based on the above embodiment, as a preferred implementation, the host stores target data to the shared memory through the first target interface, and the host accesses a message queue mechanism of the H2B device through a second target interface to send an interrupt signal to the BMC; and when the BMC receives the interrupt signal, acquiring the target data from the shared memory.
On the basis of the above embodiment, as a preferred implementation, the method further includes:
the second starting module is used for authenticating the interactive authentication request when receiving the interactive authentication request sent by the host in the operating system operation stage, and starting the shared memory after the authentication is passed so as to facilitate the interaction between the host and the BMC through the shared memory;
and the third locking module is used for re-locking the shared memory after receiving the interaction completion notification sent by the host.
With regard to the apparatus in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.
Based on the hardware implementation of the program module, and in order to implement the method according to the embodiment of the present application, an embodiment of the present application further provides an electronic device, and fig. 4 is a structural diagram of an electronic device according to an exemplary embodiment, as shown in fig. 4, the electronic device includes:
a communication interface 1 capable of information interaction with other devices such as network devices and the like;
and the processor 2 is connected with the communication interface 1 to realize information interaction with other equipment, and is used for executing the interaction method provided by one or more technical schemes when running a computer program. And the computer program is stored on the memory 3.
In practice, of course, the various components in the electronic device are coupled together by the bus system 4. It will be appreciated that the bus system 4 is used to enable connection communication between these components. The bus system 4 comprises, in addition to a data bus, a power bus, a control bus and a status signal bus. For the sake of clarity, however, the various buses are labeled as bus system 4 in fig. 4.
The memory 3 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program for operating on an electronic device.
It will be appreciated that the memory 3 may be either volatile memory or nonvolatile memory, and may include both volatile and nonvolatile memory. Among them, the nonvolatile Memory may be a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a magnetic random access Memory (FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical disk, or a Compact Disc Read-Only Memory (CD-ROM); the magnetic surface storage may be disk storage or tape storage. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced DRAM), Synchronous Dynamic Random Access Memory (SLDRAM), Direct Memory (DRmb Access), and Random Access Memory (DRAM). The memory 3 described in the embodiments of the present application is intended to comprise, without being limited to, these and any other suitable types of memory.
The method disclosed in the above embodiment of the present application may be applied to the processor 2, or implemented by the processor 2. The processor 2 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 2. The processor 2 described above may be a general purpose processor, a DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 2 may implement or perform the methods, steps and logic blocks disclosed in the embodiments of the present application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium located in the memory 3, and the processor 2 reads the program in the memory 3 and in combination with its hardware performs the steps of the aforementioned method.
When the processor 2 executes the program, the corresponding processes in the methods according to the embodiments of the present application are realized, and for brevity, are not described herein again.
In an exemplary embodiment, the present application further provides a storage medium, i.e. a computer storage medium, specifically a computer readable storage medium, for example, including a memory 3 storing a computer program, which can be executed by a processor 2 to implement the steps of the foregoing method. The computer readable storage medium may be Memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface Memory, optical disk, or CD-ROM.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media that can store program code.
Alternatively, the integrated units described above in the present application may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or portions thereof that contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling an electronic device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media that can store program code.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. An interactive method applied to BMC, the method comprising:
enabling the H2B Device Host to BMC Device, and distributing shared memory for interaction between the Host and the BMC;
locking the shared memory after the host initializes the H2B device and before loading the operating system;
when an interaction request sent by the host is received, starting the shared memory so that the host and the BMC can interact through the shared memory;
and after receiving an interaction completion notification sent by the host, re-locking the shared memory.
2. The interaction method of claim 1, wherein the host initializes the H2B device, enables target MMIO resources in a decoder, enables the H2B device access link, allocates BUS resources for the H2B device and the target MMIO resources, and enables the H2B device.
3. The interaction method as claimed in claim 1, wherein after the H2B device is initialized by the host, the PPI and Lib of the H2B device are installed in a PEI phase, and the Protcol and Lib of the H2B device are installed in a DXE phase.
4. The interaction method of claim 1, further comprising, after allocating the shared memory for the interaction between the host and the BMC:
mapping the shared memory to a first target interface of the H2B device, so that the host accesses the shared memory through the first target interface.
5. The interaction method of claim 4, wherein the host and the BMC interact through the shared memory, comprising:
the host stores target data to the shared memory through the first target interface, and the BMC acquires the target data from the shared memory.
6. The interactive method as claimed in claim 5, wherein after the host stores the target data into the shared memory through the first target interface, the method further comprises:
the host accesses a message queue mechanism of the H2B device through a second target interface to send an interrupt signal to the BMC;
correspondingly, the obtaining, by the BMC, the target data from the shared memory includes:
and when the BMC receives the interrupt signal, acquiring the target data from the shared memory.
7. The interaction method of claim 1, further comprising:
in the operating stage of the operating system, when an interactive authentication request sent by the host is received, authenticating the interactive authentication request, and after the authentication is passed, starting the shared memory so that the host and the BMC can interact through the shared memory;
and after receiving an interaction completion notification sent by the host, re-locking the shared memory.
8. An interactive apparatus, applied to BMC, the apparatus comprising:
the enabling module is used for enabling the H2B equipment and distributing a shared memory for the interaction of the host and the BMC;
a first locking module, configured to lock the shared memory after the host initializes the H2B device and before an operating system is loaded;
the first starting module is used for starting the shared memory when receiving an interaction request sent by the host so as to facilitate the interaction between the host and the BMC through the shared memory;
and the second locking module is used for re-locking the shared memory after receiving the interaction completion notification sent by the host.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the interaction method according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the steps of the interaction method according to any one of claims 1 to 7.
CN202210174241.2A 2022-02-25 2022-02-25 Interaction method and device, electronic equipment and storage medium Pending CN114253749A (en)

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Application publication date: 20220329