CN113254380A - Communication method, device and equipment between host and baseboard management controller - Google Patents

Communication method, device and equipment between host and baseboard management controller Download PDF

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Publication number
CN113254380A
CN113254380A CN202110677461.2A CN202110677461A CN113254380A CN 113254380 A CN113254380 A CN 113254380A CN 202110677461 A CN202110677461 A CN 202110677461A CN 113254380 A CN113254380 A CN 113254380A
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host
ipmi command
ipmi
sram
management controller
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CN202110677461.2A
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CN113254380B (en
Inventor
杨少俊
罗鹏芳
王兵
姚藩益
钱慧娟
陈思彤
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/606—Protecting data by securing the transmission between two devices or processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping

Abstract

The application discloses a communication method, a device and equipment between a host and a substrate management controller, which comprises the following steps: reading an IPMI command from a static random access memory of a substrate management controller; the IPMI command is a command issued by a host BIOS to the SRAM, and the SRAM is enabled in a PEI stage; analyzing the IPMI command to obtain analysis data of the IPMI command; determining return data corresponding to the IPMI command according to the analysis data; placing the return data in the SRAM so that the host BIOS reads the return data from the SRAM. Therefore, the communication efficiency between the host and the baseboard management controller can be improved, the starting speed is improved, the stability is good, and the available stage is early.

Description

Communication method, device and equipment between host and baseboard management controller
Technical Field
The present application relates to the field of server technologies, and in particular, to a method, an apparatus, and a device for communication between a host and a baseboard management controller.
Background
On a server, there is a lot of interaction between a Host and a BMC (i.e., a Baseboard Management Controller), and the requirements on an interaction interface between the Host and the BMC are higher and higher under the trend that the server is more and more powerful, and the requirements on manageability, usability, stability and serviceability are higher and higher. The IPMI (Intelligent Platform Management Interface) is used as a classic server Management Interface and has wide application. On the server, Host and BMC have a lot of interaction through IPMI interface. The performance and the safety of the IPMI interface directly influence the usability and the safety of the server, and further influence the usability and the safety of a data center and the whole service.
At present, in the prior art, the IPMI protocol is implemented on Kcs (i.e., keyboard controller type/style) Interface, the IPMI protocol is implemented on BT (i.e., Block transmitter) Interface, the IPMI protocol is implemented on Smbus (i.e., System Management Bus) Interface, the IPMI protocol is implemented on SMIC (i.e., Server Management Interface Chip), and the IPMI protocol is implemented on USB (i.e., Universal Serial Bus) Interface, but all have various defects, including slow transmission speed, poor stability, late available stage, and the like.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a method, an apparatus, and a device for communication between a host and a baseboard management controller, which can improve the communication efficiency between the host and the baseboard management controller, thereby improving the boot speed, and having good stability and early availability. The specific scheme is as follows:
in a first aspect, the present application discloses a communication method between a host and a baseboard management controller, which is applied to the baseboard management controller, and includes:
reading an IPMI command from a static random access memory of a substrate management controller; the IPMI command is a command issued by a host BIOS to the SRAM, and the SRAM is enabled in a PEI stage;
analyzing the IPMI command to obtain analysis data of the IPMI command;
determining return data corresponding to the IPMI command according to the analysis data;
placing the return data in the SRAM so that the host BIOS reads the return data from the SRAM.
Optionally, the reading the IPMI command from the sram of the bmc includes:
when the preset interrupt occurs, the IPMI command is read from the SRAM of the BMC.
Optionally, the reading the IPMI command from the sram of the bmc includes:
reading an IPMI command from a dynamic region of a static random access memory of a baseboard management controller;
the dynamic area is a storage area which is divided in the static random access memory by the host BIOS and is used for carrying out IPMI command interaction; and the static random access memory also comprises a static area which is divided by the host BIOS and used for storing static data.
Optionally, the method further includes:
the SRAM is locked before the host enters the operating system.
Optionally, the method further includes:
and authenticating an IPMI command issued by a host operating system according to a preset IPMI command communication control mode, and if the authentication is passed, allowing the host operating system to access the static random access memory.
Optionally, the preset IPMI command communication control mode is a preset mode according to an IPMI command type, the preset IPMI command communication control mode of the standard IPMI command is a compatible mode, and the preset IPMI command communication control mode of the non-standard IPMI command is a protection mode;
correspondingly, the authenticating the IPMI command issued by the host operating system according to the preset IPMI command communication control mode includes:
and the method comprises the steps of authenticating a standard IPMI command issued by the host operating system by using a first preset authentication mode, and authenticating a non-standard IPMI command issued by the host operating system by using a second preset authentication mode.
Optionally, the method further includes:
and when the host operating system finishes accessing the static random access memory, the static random access memory is locked again.
In a second aspect, the present application discloses a communication device between a host and a baseboard management controller, applied to the baseboard management controller, including:
the IPMI command acquisition module is used for reading the IPMI command from the static random access memory of the substrate management controller; the IPMI command is a command issued by a host BIOS to the SRAM, and the SRAM is enabled in a PEI stage;
the IPMI command analysis module is used for analyzing the IPMI command to obtain analysis data of the IPMI command;
the return data determining module is used for determining the return data corresponding to the IPMI command according to the analysis data;
and the return data placement module is used for placing the return data in the static random access memory so that the host BIOS reads the return data from the static random access memory.
In a third aspect, the present application discloses an electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the method of communication between a host and a baseboard management controller according to any of claims 1 to 7.
In a fourth aspect, the present application discloses a computer-readable storage medium storing a computer program which, when executed by a processor, implements the aforementioned method of communication between a host and a baseboard management controller.
Therefore, the IPMI command is read from the static random access memory of the substrate management controller; the IPMI command is a command issued by a host BIOS to the SRAM, and the SRAM is enabled in a PEI stage; analyzing the IPMI command to obtain analysis data of the IPMI command; determining return data corresponding to the IPMI command according to the analysis data; placing the return data in the SRAM so that the host BIOS reads the return data from the SRAM. That is, the communication between the host and the baseboard management controller in the present application implements the IPMI protocol based on the sram, and the host and the baseboard management controller perform IPMI communication through the shared sram, so that the data transmission speed is high, and the sram is enabled at the PEI stage, so that the sram can be used for IPMI communication at an early stage of booting, and thus, the communication efficiency between the host and the baseboard management controller can be improved, thereby improving the booting speed, and having good stability and an early usable stage.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of a method of communication between a host and a baseboard management controller as disclosed herein;
FIG. 2 is a flow chart illustrating a method of communication between a particular host and a baseboard management controller according to the present disclosure;
FIG. 3 is a flow chart of a method of communication between a host and a baseboard management controller according to the present disclosure;
FIG. 4 is a flow chart illustrating a method of communication between a particular host and a baseboard management controller according to the present disclosure;
FIG. 5 is a schematic diagram of a communication device between a host and a baseboard management controller according to the present disclosure;
fig. 6 is a block diagram of an electronic device disclosed in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
At present, in the prior art, the IPMI protocol is implemented on an Kcs interface, the IPMI protocol is implemented on a BT interface, the IPMI protocol is implemented on a Smbus interface, the IPMI protocol is implemented on an SMIC interface, and the IPMI is implemented on a Usb interface, but all have various defects, mainly including slow transmission speed, poor stability, late availability, and the like. Therefore, the communication scheme between the host and the baseboard management controller is provided, the communication efficiency between the host and the baseboard management controller can be improved, the starting speed is improved, the stability is good, and the available stage is early.
Referring to fig. 1, an embodiment of the present application discloses a communication method between a host and a baseboard management controller, which is applied to the baseboard management controller, and includes:
step S11: reading an IPMI command from a static random access memory of a substrate management controller; the IPMI command is a command sent to the sram under the host BIOS (i.e., Basic Input Output System), and the sram is enabled at the PEI stage.
In a specific embodiment, the IPMI command is read from a dynamic region of a static random access memory of a baseboard management controller; the dynamic area is a storage area which is divided in the static random access memory by the host BIOS and is used for carrying out IPMI command interaction; and the static random access memory also comprises a static area which is divided by the host BIOS and used for storing static data.
That is, the host BIOS divides the sram into two areas, a dynamic area and a static area.
Further, in this embodiment, when the predetermined interrupt occurs, the IPMI command is read from the sram of the bmc.
It should be noted that, in order to maintain the effectiveness of communication and reduce the communication load of the BMC, the present embodiment selects an interrupt manner instead of a polling manner. Because the SRAM does not support the interrupt, GPIO (General-purpose input/output) interrupt can be selected, and a serial port register or a traditional KCS register is not used for realizing an interrupt mechanism. And filling a corresponding register in the BMC before issuing the IPMI command, triggering corresponding preassigned interrupt, and communicating after the BMC receives the interrupt. The enabling of the interrupt mechanism may be implemented by the BMC.
The sram is enabled by the host BIOS at a PEI (Pre-EFI Initialization, i.e., a program block for scheduling PEIM (PEI Modules, PEI phase), DXE (Driver Execution Environment) preparation Execution Environment), that is, at a start-up phase, after the sram is enabled, communication between the host and the board management controller may be performed through the sram, which is early in an available phase.
Also, SRAM was enabled early in the PEI phase. A PEIM can be implemented that enables SRAM early in PEI. It should be noted that, in the PEI phase, a PEI Dispatcher (PEIM scheduler) executes PEIMs listed in the prior file according to priority, and then executes PEIMs whose dependency conditions are satisfied according to dependency conditions between the PEIMs. The IPMI protocol is a basic service, needs to be enabled in early stage of PEI, provides IPMI service for other PEIM, and needs to enable SRAM in early stage of PEI in order to meet the use requirement of IPMI protocol. Specifically, a PEIM for initializing the SRAM is realized, the PEIM is added into the prior file, and the priority is set to be higher than the priority of the IPMI PEIM, so that the PEIM for initializing the SRAM is executed in the early stage of the PEI and before the IPMI PEIM is executed, the SRAM is enabled, and the protocol use requirement of the IPMI is ensured.
In a specific embodiment, in the Boot (Boot) phase, the PEI phase: the host BIOS initializes the PCIE device of the BMC, allocates BUS (BUS) and MMIO (Memory-mapped I/O) resources, enables SRAM access, and divides the SRAM into two regions, one is a static region and the other is a dynamic region for realizing IPMI communication. The static area stores fixed static data such as Flag, files and the like, and the convenience, adaptability and efficiency of interaction between the Host and the BMC are improved. The dynamic area is used for achieving IPMI communication, achieving super-large data block transmission by using SRAM and achieving rapid communication, and then installing IPMI PPI (namely PEIM and PEIM Interface, Interface between PEI Module and PEI Module), and providing IPMI Over SRAM Lib (namely Library Library of the scheme of the application) used in PEI stage. DXE: protcol (protocol) of DXE, SMM, Runtime, etc. type is provided for use by various types of modules (BIOS software modules, including DXE Driver and SMM (System Management Mode) Driver), and Lib of DXE, SMM, Runtime, etc. type is provided for use by various types of modules (BIOS software modules, including DXE Driver and SMM Driver). And after the host BIOS enables SRAM access, the BMC enables an interrupt mechanism.
Step S12: and analyzing the IPMI command to obtain analysis data of the IPMI command.
Step S13: and determining the return data corresponding to the IPMI command according to the analysis data.
Step S14: placing the return data in the SRAM so that the host BIOS reads the return data from the SRAM.
In a specific embodiment, the dynamic area includes a command area and a data area, wherein the command area is used for storing IPMI commands, and the data area is used for storing return data.
For example, the host BIOS issues an IPMI command for inquiring about a server start-up mode to the sram of the bmc, the bmc acquires the IPMI command, analyzes the IPMI command to obtain analysis data, and acquires a server start-up mode configured by a user from user configuration data according to the analysis data, for example, acquires return data by USB start-up. The host BIOS reads the return data from the static random access memory, and then starts up the return data through the USB, when the host BIOS is placed in the static random access memory, specifically, the dynamic area.
It should be noted that SRAM is accessed through MMIO, which is a PCIE link, and has better stability than Smbus.
Therefore, the IPMI command is read from the static random access memory of the substrate management controller in the embodiment of the application; the IPMI command is a command issued by a host BIOS to the SRAM, and the SRAM is enabled in a PEI stage; analyzing the IPMI command to obtain analysis data of the IPMI command; determining return data corresponding to the IPMI command according to the analysis data; placing the return data in the SRAM so that the host BIOS reads the return data from the SRAM. That is, the communication between the host and the baseboard management controller in the present application implements the IPMI protocol based on the sram, and the host and the baseboard management controller perform IPMI communication through the shared sram, so that the data transmission speed is high, and the sram is enabled at the PEI stage, so that the sram can be used for IPMI communication at an early stage of booting, and thus, the communication efficiency between the host and the baseboard management controller can be improved, thereby improving the booting speed, and having good stability and an early usable stage.
Referring to fig. 2, an embodiment of the present application discloses a specific communication method between a host and a baseboard management controller, which is applied to the baseboard management controller, and includes:
step S21: reading an IPMI command from a static random access memory of a substrate management controller; the IPMI command is a command issued by a host BIOS to the SRAM, and the SRAM is enabled at PEI stage.
Step S22: and analyzing the IPMI command to obtain analysis data of the IPMI command.
Step S23: and determining the return data corresponding to the IPMI command according to the analysis data.
Step S24: placing the return data in the SRAM so that the host BIOS reads the return data from the SRAM.
Step S25: the SRAM is locked before the host enters the operating system.
That is, the embodiment of the present application includes a protection mechanism, and before the host enters the operating system, the sram is locked for access control, so as to improve the communication security.
It should be noted that in some other embodiments, the static random access memory may also be locked by the BIOS through software or hardware before the host enters the operating system, wherein the hardware is more reliable.
Step S26: and authenticating an IPMI command issued by a host operating system according to a preset IPMI command communication control mode, and if the authentication is passed, allowing the host operating system to access the static random access memory.
The preset IPMI command communication control mode is a preset mode according to the IPMI command type, the preset IPMI command communication control mode of the standard IPMI command is a compatible mode, and the preset IPMI command communication control mode of the non-standard IPMI command is a protection mode. Among them, the non-standard IPMI command is custom command.
Correspondingly, the authenticating the IPMI command issued by the host operating system according to the preset IPMI command communication control mode includes:
and the method comprises the steps of authenticating a standard IPMI command issued by the host operating system by using a first preset authentication mode, and authenticating a non-standard IPMI command issued by the host operating system by using a second preset authentication mode.
It should be noted that the first preset authentication mode may be simple user name and password authentication, and the second preset authentication mode utilizes an authentication mode with higher complexity.
That is, the embodiment of the application can be compatible with standard IPMI commands and non-standard IPMI commands, inherits the compatibility and the universality of IPMI protocols, and has higher compatibility.
In a specific embodiment, a control switch may be added to set the IPMI command communication control mode. For standard IPMI commands, the default may be set to enable state, i.e. compatible mode, and for non-standard IPMI commands, the default may be protected mode.
In other embodiments, the IPMI command communication control mode of all types of IPMI commands may be set to protection mode or compatible mode according to the user's needs.
Step S27: and when the host operating system finishes accessing the static random access memory, the static random access memory is locked again.
In a specific embodiment, when the host os finishes accessing the dynamic area of the sram, the dynamic area of the sram is relocked.
In addition, for the static area, before the host enters the operating system, the static random access memory is locked, specifically, both the static area and the dynamic area are locked. That is, the static area is also locked before the host enters the operating system. And the host operating system accesses the static area, the baseboard management controller performs security authentication, after the authentication is passed, the host operating system is allowed to access the static area, and after the access is finished, the static area is locked again.
Referring to fig. 3, fig. 3 is a flowchart illustrating a communication method between a host and a bmc according to an embodiment of the present disclosure. And initializing the BMC SRAM in early stage of the PEI, starting a protection mechanism to lock the SRAM before entering an operating system, performing access authentication on SRAM access in the operating stage of the host operating system, and re-locking after the access is finished to start protection. Among them, UEFI (Unified Extensible Firmware Interface), OS (Operation System operating System). Where the ellipses in the arrows in fig. 3 indicate corresponding steps in the startup phase, reference may be made to the prior art.
Referring to fig. 4, fig. 4 is a flowchart illustrating a specific method for communication between a host and a bmc according to an embodiment of the present disclosure.
See table 1 for a comparison of the effect of the present protocol with the prior art protocol.
TABLE 1
Figure 127697DEST_PATH_IMAGE001
It can be seen that the prior art has the following characteristics:
1, Ipmi Over Kcs: the IPMI protocol is realized on an Kcs interface, IO port transmission is used, the speed is low, and the protection mechanism is weak.
Ipmi Over BT: the IPMI protocol is realized on the BT interface, the IO port transmission is used, the block transmission is supported, the speed is high, and the protection mechanism is weak.
Ipmi Over SSIF: the IPMI protocol is realized on the Smbus interface, the stability is poor, and the speed is low.
Ipmi Over SMIC: the use is less, the support of a single chip is needed, the IO transmission is used, and no obvious advantage exists.
Ipmi Over Usb: the IPMI protocol is realized on the Usb interface, the transmission speed is high, the compatibility and the stability are poor, the IPMI protocol can be used only after the initialization of the Usb drive is completed, and the available stage is late.
According to the scheme provided by the application, the IPMI protocol is realized on the SRAM, so that the IPMI communication can be realized, the SRAM communication can be realized at the same time, the fast transmission is realized by utilizing the SRAM super-large block transmission, and an interrupt mechanism and a safety mechanism are provided. Therefore, the defect of slow IPMI communication speed is improved by using SRAM super-large block transmission to realize fast transmission. The characteristic of poor availability of the Ipmi Over Usb technology is improved, the server can be used in the whole starting and running stage of the server, and the high availability and compatibility of the IPMI are kept. The SRAM is divided into a static area and a dynamic area, so that an IPMI protocol is realized, an SRAM communication mechanism is realized, the customization requirements are met, and an easy-to-use and safe customization interactive interface is realized. The security mechanism, the interrupt mechanism, etc. of the present application. Security and efficiency are maintained while compatibility and high speed of transmission are achieved. Therefore, the scheme of the application overcomes the defects that the traditional IPMI interactive interface is low in speed and the safety protection mechanism is weak, overcomes the defects that some non-standardized interactive interfaces are poor in compatibility and weak in universality and need to be continuously modified according to actual requirements, and achieves the characteristics of high transmission speed, strong safety mechanism, strong compatibility, good stability and the like. Therefore, the interaction speed, the security and the efficiency of Host and BMC are improved, and the compatibility is kept. Therefore, the starting speed of the server is improved, and the availability and serviceability of the server are improved. Because the communication is safer, the safety of the server is improved, and the safe and stable operation of the server is guaranteed. Because the compatibility is good, the universality is strong, the interface can be used in an iterative way after being realized, and the maintenance cost is reduced.
In addition, the existing SRAM scheme is only used for interacting customized data, and a customized customization protocol is realized. The large amount of IPMI interaction between BIOS and BMC during boot-up still uses traditional IPMI implementation, which has not improved the drawbacks (see Table 1). Only in the BDS phase, PCIE initialization is available after completion, and availability is limited.
The scheme of the application is as follows: the scheme of the prior SRAM is improved, so that the whole starting phase including PEI, DXE and BDS can use the SRAM, the available requirement of the whole starting phase of the IPMI protocol is met, and the realization of the IPMI protocol on the SRAM is supported. The method not only supports interactive customized data and a self-defined protocol and meets the customized requirement, but also realizes the IPMI protocol based on the SRAM, supports the transmission of super large blocks, improves the performance of the IPMI, and shortens the time for a large amount of IPMI interaction between the BIOS and the BMC in the starting-up stage, thereby accelerating the starting-up speed and improving the usability of the server.
In addition, the IPMI protocol may be based on two SRAMs in the BMC, wherein the SRAM powered by the battery can still maintain the data of the static region in case of power failure, and the configuration can be recovered without loss after power recovery. The idea of the present technique can be used in other fields, where the upper layer protocol is implemented based on different interfaces, buses or media. The security and efficiency are improved while maintaining compatibility.
Referring to fig. 5, an embodiment of the present application discloses a communication device between a host and a baseboard management controller, applied to the baseboard management controller, including:
an IPMI command obtaining module 11, configured to read an IPMI command from a sram of a bmc; the IPMI command is a command issued by a host BIOS to the SRAM, and the SRAM is enabled in a PEI stage;
the IPMI command analysis module 12 is used for analyzing the IPMI command to obtain analysis data of the IPMI command;
a return data determining module 13, configured to determine, according to the analysis data, return data corresponding to the IPMI command;
a return data placement module 14, configured to place the return data in the sram, so that the host BIOS reads the return data from the sram.
Therefore, the IPMI command is read from the static random access memory of the substrate management controller; the IPMI command is a command issued by a host BIOS to the SRAM, and the SRAM is enabled in a PEI stage; analyzing the IPMI command to obtain analysis data of the IPMI command; determining return data corresponding to the IPMI command according to the analysis data; placing the return data in the SRAM so that the host BIOS reads the return data from the SRAM. That is, the communication between the host and the baseboard management controller in the present application realizes the IPMI protocol based on the sram, and the host and the baseboard management controller perform IPMI communication through the shared sram, so that the data transmission speed is high, and the sram is enabled at the PEI stage, so that the sram can be used for IPMI communication at the early start of booting, and thus, the communication efficiency between the host and the baseboard management controller can be improved, thereby improving the booting speed, and the stability is good, and the available stage is early.
The IPMI command obtaining module 11 is specifically configured to read an IPMI command from a sram of a bmc when a predetermined interrupt occurs.
The IPMI command obtaining module 11 is specifically configured to read an IPMI command from a dynamic area of a sram of the bmc;
the dynamic area is a storage area which is divided in the static random access memory by the host BIOS and is used for carrying out IPMI command interaction; and the static random access memory also comprises a static area which is divided by the host BIOS and used for storing static data.
In addition, the device also comprises a static random access memory access control module used for locking the static random access memory before the host enters the operating system.
Further, the device further comprises a command authentication module, configured to authenticate an IPMI command issued by the host operating system according to a preset IPMI command communication control mode, and if the authentication passes, allow the host operating system to access the sram.
The preset IPMI command communication control mode is a preset mode according to the IPMI command type, the preset IPMI command communication control mode of the standard IPMI command is a compatible mode, and the preset IPMI command communication control mode of the non-standard IPMI command is a protection mode;
correspondingly, the command authentication module is used for authenticating the standard IPMI command issued by the host operating system by using a first preset authentication mode and authenticating the non-standard IPMI command issued by the host operating system by using a second preset authentication mode.
The SRAM access control module is further configured to relock the SRAM when the host OS finishes accessing the SRAM.
Referring to fig. 6, an embodiment of the present application discloses an electronic device, which includes a processor 21 and a memory 22; wherein, the memory 22 is used for saving computer programs; the processor 21 is configured to execute the computer program to implement the communication method between the host and the baseboard management controller disclosed in the foregoing embodiment.
For the specific process of the communication method between the host and the bmc, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and details are not repeated herein.
Further, an embodiment of the present application also discloses a computer readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the communication method between the host and the baseboard management controller disclosed in the foregoing embodiment.
For the specific process of the communication method between the host and the bmc, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and details are not repeated herein.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above detailed description is provided for a communication method, apparatus, and device between a host and a baseboard management controller, and a specific example is applied in the present disclosure to explain the principle and the implementation of the present disclosure, and the description of the above embodiment is only used to help understand the method and the core idea of the present disclosure; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. A communication method between a host and a baseboard management controller is applied to the baseboard management controller and comprises the following steps:
reading an IPMI command from a static random access memory of a substrate management controller; the IPMI command is a command issued by a host BIOS to the SRAM, and the SRAM is enabled in a PEI stage;
analyzing the IPMI command to obtain analysis data of the IPMI command;
determining return data corresponding to the IPMI command according to the analysis data;
placing the return data in the SRAM so that the host BIOS reads the return data from the SRAM.
2. The method of claim 1, wherein reading the IPMI command from the SRAM of the BMC comprises:
when the preset interrupt occurs, the IPMI command is read from the SRAM of the BMC.
3. The method of claim 1, wherein reading the IPMI command from the SRAM of the BMC comprises:
reading an IPMI command from a dynamic region of a static random access memory of a baseboard management controller;
the dynamic area is a storage area which is divided in the static random access memory by the host BIOS and is used for carrying out IPMI command interaction; and the static random access memory also comprises a static area which is divided by the host BIOS and used for storing static data.
4. The method of communicating between a host and a baseboard management controller of claim 1, further comprising:
the SRAM is locked before the host enters the operating system.
5. The method of communicating between a host and a baseboard management controller of claim 4, further comprising:
and authenticating an IPMI command issued by a host operating system according to a preset IPMI command communication control mode, and if the authentication is passed, allowing the host operating system to access the static random access memory.
6. The method of claim 5, wherein the predetermined IPMI command communication control mode is a predetermined mode according to IPMI command type, the predetermined IPMI command communication control mode of standard IPMI command is a compatible mode, and the predetermined IPMI command communication control mode of non-standard IPMI command is a protection mode;
correspondingly, the authenticating the IPMI command issued by the host operating system according to the preset IPMI command communication control mode includes:
and the method comprises the steps of authenticating a standard IPMI command issued by the host operating system by using a first preset authentication mode, and authenticating a non-standard IPMI command issued by the host operating system by using a second preset authentication mode.
7. The method of communicating between a host and a baseboard management controller of claim 5, further comprising:
and when the host operating system finishes accessing the static random access memory, the static random access memory is locked again.
8. A communication device between a host and a baseboard management controller is applied to the baseboard management controller and comprises:
the IPMI command acquisition module is used for reading the IPMI command from the static random access memory of the substrate management controller; the IPMI command is a command issued by a host BIOS to the SRAM, and the SRAM is enabled in a PEI stage;
the IPMI command analysis module is used for analyzing the IPMI command to obtain analysis data of the IPMI command;
the return data determining module is used for determining the return data corresponding to the IPMI command according to the analysis data;
and the return data placement module is used for placing the return data in the static random access memory so that the host BIOS reads the return data from the static random access memory.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the method of communication between a host and a baseboard management controller according to any of claims 1 to 7.
10. A computer-readable storage medium storing a computer program which, when executed by a processor, implements the method of communication between a host and a baseboard management controller according to any of claims 1 to 7.
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