JP4568304B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a technique for suppressing crystal defects generated in the manufacture of a semiconductor device, and in particular, manufacturing of a semiconductor device that suppresses dislocations generated in an impurity activation heat treatment step after ion implantation for a high concentration diffusion layer in the semiconductor device. It is related to the method.

2. Description of the Related Art Conventionally, a source or drain diffusion layer region (by selective ion implantation into a surface portion of a silicon substrate around the edge of a gate electrode of a field effect transistor (hereinafter referred to as a MOS transistor) including a MOS device or the like Hereinafter referred to as source / drain regions.)
In the case of forming the gate electrode, ion implantation is performed using a photoresist film or a silicon oxide film as a mask, and then the mask film is removed and heat treatment is performed to activate the source / drain regions.

Here, FIG. 10 shows a cross-sectional view of a conventional semiconductor device. In FIG. 10, the silicon substrate 2
A gate electrode 202 is formed on 01 through an insulating film (not shown). Then, a high concentration impurity is implanted into the silicon substrate 201 by ion implantation using the method as described above, and then a source / drain region 203 is formed by heat treatment to form a MOS transistor.

The region of the silicon substrate into which ions are implanted by the above-described ion implantation is made amorphous. This amorphized region is activated by the subsequent heat treatment, and solid phase epitaxial growth is performed using the single crystal region as a seed to become a single crystal. When activated by this heat treatment, crystal defects (hereinafter referred to as dislocations 210) generated in the recrystallization process as shown in FIG.
) Frequently occur in the silicon substrate 1 at the end portion of the gate electrode 202 (hereinafter referred to as the end portion 202a). This is caused by solid phase epitaxial growth proceeding in two different crystal axis directions as shown in FIG.

That is, when an activation heat treatment is performed on the amorphized source / drain region 203, the central portion 203b of the source / drain region 203 is solid-phase grown in the <100> direction, and the end portion 202a of the gate electrode of the source / drain region 203 is obtained. Solid phase growth occurs in the <111> direction at the nearby end 203a. As each solid phase growth collides, dislocations 210 are generated immediately below the end portion 202a.

Also, with recent MOS transistors, etc., there have been problems such as punch-through between the source and drain, and deterioration of characteristics due to hot electrons at the drain end due to miniaturization of elements due to higher speed and higher integration. .

Therefore, LDD (Lightly Doped Dr) prevents the deterioration of characteristics caused by hot electrons.
ain) structure is required, and a structure in which a low-concentration impurity region is formed prior to a high-concentration impurity region using the side wall of the gate electrode has been used.

Here, a semiconductor device of a MOS transistor using a conventional LDD structure will be described with reference to FIG. FIG. 11 shows a source / drain region forming process in a conventional LDD structure. In FIG. 11A, after forming a gate electrode 303 having a width of 0.25 μm on the gate insulating film 302 formed on the silicon substrate 301, phosphorus ions are implanted using the gate electrode 303 as a mask to form n-low concentration impurities. Region 305 is formed. This ion implantation is performed, for example, with phosphorus (P) under the conditions of an acceleration voltage of 20 keV and a dose of 1 × 10 ¹³ cm ⁻² .

Next, after depositing a SiN film on the gate insulating film 302 and the gate electrode 303 by LP-CVD (Low Pressure-Chemical Vapor Deposition), RIE (Reactive Ion Etching) is performed.
) To etch the SiN film to form gate electrode side walls 304 (film thickness 100 nm). S
In a state where the gate electrode sidewall 304 of the iN film is formed (FIG. 11A), the end portion 304a (hereinafter referred to as a pattern edge 304a) of the gate electrode sidewall 304 is highly strained (high stress) as shown in FIG. ) The area exists.

Next, as shown in FIG. 11B, an n + high concentration impurity region 306 is formed by ion implantation using the gate electrode side wall 304 or the like as a mask to form source / drain regions 307. In this ion implantation, for example, arsenic (As) is accelerated by an acceleration voltage of 40 keV and a dose amount of 4 × 10 ¹⁵ cm ^{−.
Performed under} the condition of ² . The dose of ion implantation is about 1 × 10 ¹⁵ cm ^{−2 and} the silicon substrate in the ion implantation region is completely amorphous. Subsequent source / drain regions 307
Activation by heat treatment is FA (Furnance Anneal)
Thus, it is performed at 950 ° C. for about 10 minutes in a nitrogen atmosphere (FIG. 11C).

As described above, by the ion implantation for forming the n + high concentration impurity region 306, the crystal structure of the silicon substrate 1 in the source / drain region 307 is destroyed and becomes an amorphous state. On the other hand, since the portion covered with the side wall 304 of the gate electrode is not amorphized,
In the silicon substrate 301 of the pattern edge 304a, it becomes a boundary between the amorphous structure and the single crystal.

Further, after the impurity implantation, when performing heat treatment for impurity activation and recrystallization (hereinafter referred to as activation heat treatment), stress based on the difference in thermal expansion coefficient depending on the material of the gate electrode side wall 304 and the gate insulating film High stress in the peripheral portion of the pattern edge such as compressive stress on the silicon substrate 301 due to 302 is applied, and recrystallization of the substrate without dislocation is inhibited. As a result, the stress at the pattern edge 304a becomes high, and the dislocation generated in the recrystallization process described with reference to FIG. 9 at the pattern edge 304a expands to relax this stress and penetrates the junction of the diffusion layer and the well. Thus, a long dislocation 310 occurs until the source / drain region 307 reaches the depletion layer (FIG. 11C). The long dislocation 310 increases the leakage current, and there is a problem that the semiconductor device may not operate when the leakage current is extremely large.

In this case, for example, if an activation heat treatment is performed at a high temperature of 1000 ° C. or more for 10 seconds to several tens of minutes, the amorphous state in the silicon substrate can be completely recrystallized, and dislocations generated in the recrystallization process can be obtained. However, if the high temperature heat treatment is performed for a long time in the activation heat treatment, the implanted impurity diffuses widely, making it difficult to obtain a desired impurity profile, and there is a problem that the device cannot be operated as a high performance semiconductor device. It was.

Further, as a method for suppressing the occurrence of dislocation due to the activation heat treatment of the source / drain regions, for example, in Patent Document 1 and Patent Document 2, the second adjacent to the side wall of the gate electrode is used.
The gate electrode side wall is formed, and the ion implantation opening is narrowed to perform ion implantation, and n
+ A high concentration impurity region is formed. Thereafter, a method for performing a heat treatment after removing the second gate electrode sidewall has been filed.

However, if the ion-implanted region is formed after the second gate electrode sidewall is formed, the size of the ion-implanted opening becomes narrower. Therefore, there has been a problem that it is difficult to obtain a desired impurity profile of the source / drain regions with higher integration and device miniaturization. Furthermore, the gate electrode material, for example, Poly-Si, is also applied to the end of the gate electrode.
The stress due to the above is concentrated, and if the gate electrode side wall is thinned, the stress is further increased by approaching the stress concentration portion of the pattern edge, so that there is a problem that the dislocation is expanded by the activation heat treatment.

Furthermore, stress is extremely concentrated around the point where the pattern edge and the edge of the element isolation oxide film intersect, and in the worst case, dislocations may occur in all elements including transistors.
This is because the stress concentration region is almost the same as the dislocation occurrence point at the pattern edge.
This is thought to be due to the activation heat treatment of the drain region. However, the conventional manufacturing process and the semiconductor device do not present an effective solution to the above-described problem.
Japanese Patent Laid-Open No. 5-211165 JP-A-10-178172

As described above, in the formation of the source / drain region in the conventional semiconductor device, when ions are implanted into the source / drain region, the silicon single crystal in the substrate has an amorphous structure at the edge of the side wall of the gate electrode, and the subsequent impurity activation Dislocation occurs at the pattern edge in the crystallization heat treatment, and it is difficult to sufficiently recrystallize the amorphous structure, resulting in a problem of leakage current of the source / drain junction.

The present invention has been made to solve the above-described problems. The activation heat treatment of the high concentration impurity region is achieved by reducing the stress generated around the pattern edge portion without performing the activation heat treatment for a long time at a high temperature. The present invention provides a method for manufacturing a semiconductor device that suppresses the expansion of dislocations generated in the semiconductor device.

A method of manufacturing a semiconductor device of the present invention that achieves the above object includes a step of forming a gate insulating film on a silicon semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and a gate electrode sidewall on the gate electrode. Forming a film; forming a gate electrode sidewall film; then performing a heat treatment so as to relieve stress on the silicon semiconductor substrate of the gate insulating film; and performing the heat treatment, and then performing the gate electrode sidewall film as at least a part of the mask to the front Symbol impurities are implanted into the silicon semiconductor substrate, forming an amorphous region, after forming the amorphous region, the light transmission on the gate electrode and the gate electrode side wall film Forming a prevention film; and forming the light transmission prevention film, and then forming the gate electrode of the silicon semiconductor substrate. RTA from the surface side, the spike annealing or flash annealing, possess and performing activation heat treatment of the amorphous region, in the step of performing the activation heat treatment, the temperature of the gate electrode by the light transmission preventing layer is the amorphous The temperature is lower than the temperature of the region, and the recrystallization of the amorphous region is made dominant in the <100> direction due to the difference in temperature .
A method of manufacturing a semiconductor device of the present invention that achieves the above object includes a step of forming a gate insulating film on a silicon semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and post-oxidation on the gate electrode. Forming an insulating film; forming a gate electrode sidewall film on the post-oxide insulating film; and forming the gate electrode sidewall film, and then forming the gate insulating film and the post-oxidized insulating film on the silicon semiconductor substrate. A step of performing a heat treatment to relieve stress, a step of implanting impurities into the silicon semiconductor substrate using the gate electrode sidewall film as at least part of a mask after the heat treatment, and forming an amorphous region; Forming a light transmission preventing film on the gate electrode and the gate electrode sidewall film after forming the region; and And performing an activation heat treatment of the amorphous region by RTA, spike annealing or flash annealing from the surface side of the silicon semiconductor substrate on which the gate electrode is formed, and performing the activation heat treatment In the process, the temperature of the gate electrode is lower than the temperature of the amorphous region by the light transmission preventing film, and the growth in the <100> direction is dominant in the recrystallization of the amorphous region due to the temperature difference. It is characterized by that.

A method of manufacturing a semiconductor device of the present invention that achieves the above object includes a step of forming a gate insulating film on a silicon semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and a gate electrode sidewall on the gate electrode. Forming a film; forming a gate electrode sidewall film; then performing a heat treatment so as to relieve stress on the silicon semiconductor substrate of the gate insulating film; and performing the heat treatment, and then performing the gate electrode sidewall film as at least a part of the mask, before Symbol impurities are implanted into the silicon semiconductor substrate, forming an amorphous region, after forming the amorphous region, to the on the amorphous region surface and the gate electrode on the surface, After forming a material having a different light absorption rate and forming a film material having a different light absorption rate, RTA from the surface side of the gate electrode of the emission semiconductor substrate is formed by a spike anneal or flash anneal, possess and performing activation heat treatment of the amorphous region, in the step of performing the activation heat treatment, the light (1) The temperature of the gate electrode is lower than the temperature of the amorphous region, and the recrystallization of the amorphous region is governed by the growth in the <100> direction due to the temperature difference. Or (2) the temperature of the gate electrode becomes higher than the temperature of the amorphous region, and growth in the <110> direction dominates recrystallization of the amorphous region due to the temperature difference. It is characterized by becoming .
A method of manufacturing a semiconductor device of the present invention that achieves the above object includes a step of forming a gate insulating film on a silicon semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and post-oxidation on the gate electrode. Forming an insulating film; forming a gate electrode sidewall film on the post-oxide insulating film; and forming the gate electrode sidewall film, and then forming the gate insulating film and the post-oxidized insulating film on the silicon semiconductor substrate. A step of performing a heat treatment to relieve stress, a step of implanting impurities into the silicon semiconductor substrate using the gate electrode sidewall film as at least part of a mask after the heat treatment, and forming an amorphous region; After forming the region, materials with different light absorption rates are formed on the surface of the gate electrode and the surface of the amorphous region, respectively. And forming the film material having a different light absorption rate, and then activating the amorphous region by RTA, spike annealing or flash annealing from the surface side of the silicon semiconductor substrate on which the gate electrode is formed. In the step of performing the activation heat treatment, (1) the temperature of the gate electrode is lower than the temperature of the amorphous region due to the material of the film having a different light absorption rate. The growth of the amorphous region in the <100> direction becomes dominant due to the difference of (2), or (2) the temperature of the gate electrode becomes higher than the temperature of the amorphous region, and the temperature According to the difference, the recrystallization of the amorphous region is made dominant in the <110> direction.

The semiconductor device according to the present invention suppresses the expansion of dislocations generated in the activation heat treatment of the high-concentration impurity region by reducing the stress generated around the pattern edge without performing the activation heat treatment at a high temperature for a long time. be able to.

Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.
First, FIG. 1A to FIG. 1D are cross-sectional views in order of steps for explaining the first embodiment of the present invention.

In this example, the present invention is applied to the manufacture of a MOS transistor having an LDD structure. First, as shown in FIG. 1A, a gate insulating film 102 is formed in a transistor formation region partitioned by forming an element isolation region (not shown) on a P-type silicon substrate 101,
After forming a gate electrode 103 having a width of 0.25 μm thereon, ion implantation is performed using the element isolation oxide film and the gate electrode 103 as an ion implantation mask, and an n − low concentration impurity region 106 is formed by heat treatment.

Thereafter, an SiN film is deposited on the gate insulating film 102 and the gate electrode 103 by LP-CVD, and then the SiN film is etched by RIE to form the first gate electrode sidewall 104 (film thickness 1
00 nm). Here, the film thickness on the side wall of the gate electrode means the film thickness at the contact point with the gate insulating film on the side wall of the gate electrode.

Next, as shown in FIG. 1B, an n + high concentration impurity region 107 is formed by ion implantation using the element isolation region and the gate electrode side wall 104 as a mask, thereby forming a source / drain region 108. In this ion implantation, for example, arsenic (As) is accelerated by an acceleration voltage of 40 keV and a dose amount of 4 ×.
It carries out on the conditions of 10 ^{< 15} > cm ^<-2> .

Further, LP is formed on the gate insulating film 102, the gate electrode 103, and the first gate electrode sidewall 104.
-A SiN film is deposited by CVD, and this SiN film is etched by RIE to form second gate electrode sidewalls 105 as shown in FIG. In this embodiment, the second gate electrode side wall 1
Although 05 is a SiN film, the side wall of the second gate electrode can be formed using a silicon oxide film such as Poly-Si or TEOS.

Thereafter, activation heat treatment of the source / drain region 108 is performed. This heat treatment was performed by FA for 10 minutes at 950 ° C. in a nitrogen atmosphere. Thereafter, the second gate electrode sidewall 105 may be removed by RIE or the like.

On the other hand, as shown in FIG. 1D, the SiN film 109 may be coated on the entire surface by LP-CVD instead of the second gate electrode sidewall 105 in FIG. Here, the film covering the entire surface is Si
Instead of the N film, a silicon oxide film such as Poly-Si or TEOS may be used.

Thereafter, activation heat treatment of the source / drain region 108 was performed. Next, S coated on the entire surface
The iN film may be removed.

Here, an experiment was conducted on the relationship between the film thickness at the pattern edge 105a of the second gate electrode sidewall 105 and the dislocation occurrence rate, and the result is shown in FIG. In this experiment, the second formed in FIG.
The film thickness of the gate electrode sidewall 105 is 5 nm, 10 nm, 30 nm, and 40 nm, respectively, and the second film is applied to the entire surface as shown in FIG. 1D (referred to as the entire film in FIG. 2). ), And the dislocation occurrence rate in the conventional method performed only on the first gate electrode sidewall 104 (the second gate electrode sidewall 105 is 0 nm) was investigated.

The rate of occurrence of dislocation was evaluated by observing etch pits (holes made by etching) on the surface after selective etching. Selective etching is performed by immersing the silicon substrate with the film peeled off in the light solution for 1 minute. Dislocation observation is performed by SEM (Scanning Electron Microscope). About 2000 pieces were observed, and the percentage of the number of dislocations generated with respect to the total number of observations was defined as the dislocation generation rate.

As shown in FIG. 2, it can be seen that the dislocation generation rate is drastically reduced as the thickness of the second gate electrode sidewall 105 is increased. The thickness of the second gate electrode side wall 105 is 10 nm, the dislocation generation rate is 6%, and 20 n
It is 2% for m and 0% for 30 nm or more (including the entire surface coating).

As described above, according to the method of the first embodiment, the stress generated at the pattern edge 105a of the second gate electrode sidewall 105 and the dislocation generated during the recrystallization process generated at the end 107a of the n + high concentration impurity region 107. It was possible to completely suppress the occurrence of long dislocations. Furthermore, by separating the stress generated at the pattern edge 105a of the second gate electrode sidewall 105 from the gate electrode 103, a more reliable device could be manufactured.

As a result, the distance to be separated from the edge 107a of the n + high concentration impurity region 107 by the pattern edge 105a of the second gate electrode sidewall 105 needs to be 30 nm or more with the gate electrode width of 0.25 μm. However, the device becomes smaller as the device becomes finer, and is also influenced by changes in stress due to differences in gate electrode material and sidewall material.

In addition, the semiconductor device using the second gate electrode sidewall 105 described in the present embodiment has a cross-sectional view, a plan view, and an oblique polished view using SCM (Scanning Capacitance Microscope), stain etching, or the like. When observed, the second gate electrode sidewall 1 adjacent to the first gate electrode sidewall 104 serving as an ion implantation mask for the n + high-concentration impurity region 107 is observed.
It can be confirmed whether or not the present embodiment is used since there is no long dislocation starting from the presence of 05 and the pattern edges of the first gate electrode 104 and the second gate electrode 105. In addition, even when the second gate electrode sidewall 105 or the SiN film 109 on the entire surface is removed, it is confirmed whether or not this embodiment is used because there is no long dislocation starting from the pattern edge of the first gate electrode 104. can do.

Next, a second embodiment of the present invention will be described with reference to FIGS. 3 and 4
FIG. 5 is a flow chart showing the order of steps of forming a source / drain region for explaining a second embodiment of the present invention. This embodiment is applied to a gate electrode or a silicon substrate at a high temperature of a gate insulating film or a post-oxidized insulating film that affects the expansion of dislocations at a pattern edge accompanying ion implantation into an n + high concentration impurity region and subsequent activation heat treatment. This is an embodiment that focuses on stress reduction.

First, as in FIG. 1A of the first embodiment, a gate insulating film 102 is formed in a transistor formation region partitioned by forming an element isolation oxide film (not shown) on a P-type silicon substrate 101, After forming a gate electrode 103 having a width of 0.25 μm thereon, ion implantation is performed using the element isolation oxide film and the gate electrode 103 as an ion implantation mask, and an n − low concentration impurity region 106 is formed by heat treatment ( FIG. 3 (a)).

Thereafter, an SiN film is deposited on the gate insulating film 102 and the gate electrode 103 by LP-CVD, and then the SiN film is etched by RIE to form the first gate electrode sidewall 104 (film thickness 1
00 nm) (FIG. 3B).

Thereafter, before the n + high concentration impurity region 117 is formed, creep heat treatment (high temperature heat treatment)
(FIG. 3C).

Further, using the element isolation oxide film and the gate electrode sidewall 104 as an ion implantation mask, an n + high concentration impurity region 117 is formed by ion implantation, and a source / drain region 118 is formed. In this ion implantation, for example, arsenic (As) is accelerated by an acceleration voltage of 40 keV and a dose amount of 4 × 10 ¹⁵ c.
The process is performed under the condition of m- ² (FIG. 3D).

Thereafter, activation heat treatment of the source / drain region 118 is performed. This heat treatment was an activation heat treatment at 950 ° C. for 10 minutes in a nitrogen atmosphere with FA (FIG. 3E).

Another embodiment of the present invention will be described with reference to FIG. In FIG. 4, until the formation of the gate electrode 103 is formed, it is prepared in the same manner as in FIG. 3, and then post-oxidation is performed at 800 ° C.
A post-oxidation insulating film 120 is formed on the gate electrode 103 and the like (FIG. 4A). Then, ion implantation is performed using the element isolation oxide film, the gate electrode 103 and the like as an ion implantation mask, and an n − low concentration impurity region 116 is formed by heat treatment (FIG. 4B).

Then, after depositing a SiN film on the post-oxide insulating film 120 by LP-CVD, RIE
Then, the SiN film is etched to form the first gate electrode sidewall 104 (film thickness 100 nm) (FIG. 4C).

Further, before the diffusion layer 117 of n + high concentration impurity is formed, a creep heat treatment is performed (FIG. 4).
(D)).

Further, using the element isolation oxide film and the gate electrode sidewall 104 as a mask, an n + high concentration impurity region 117 is formed by ion implantation, and a source / drain region 118 is formed. This ion implantation is performed, for example, using arsenic (As) under the conditions of an acceleration voltage of 40 keV and a dose of 4 × 10 ¹⁵ cm ⁻² (FIG. 4E).

Thereafter, activation heat treatment of the source / drain region 118 is performed. This heat treatment was an activation heat treatment at 950 ° C. for 10 minutes in a nitrogen atmosphere with FA. The method of FIG. 4 is effective in reducing the influence on the dislocation expansion caused by both the gate insulating film 102 and the post-oxide insulating film 120 (FIG. 4F).

Here, the relationship between the temperature of the creep heat treatment and the treatment time is shown in FIG. 5, and the range of the temperature and the treatment time of the creep heat treatment for reducing the stress that causes the dislocation expansion was investigated.

Creep heat treatment refers to a gate insulating film, such as SiO2, by maintaining a high temperature under stress.
_It refers to a heat treatment that causes a so-called creep phenomenon, showing relaxation of viscous deformation stress on a _two- film silicon substrate. In the experiment, the temperature is raised and lowered at a high speed in the FA method and the single wafer type heat treatment furnace, in which the temperature is raised and lowered relatively slowly in a batch type diffusion furnace used in semiconductor substrate processing and the heat treatment is performed for a long time at the maximum temperature. RTA (Rapid Therm
al Anneal-Rapid Heat Treatment) method. These systems result in the substrate being heated from both sides. In the experiment, the temperature of the creep heat treatment was set to 900 ° C., 1000 ° C., 10
Four conditions of 50 ° C, 1100 ° C, treatment time of 1 second, 10 seconds, 120 seconds, 7200 seconds 4
As one condition, a total of 16 conditions for both conditions were performed on each of the gate oxide film (in the case of the embodiment of FIG. 3) and the post-oxide insulating film + the gate insulating film (in the case of the embodiment of FIG. 4).

As a result of the experiment, in both the experiments of FIG. 3 and FIG. 4, the results of the presence or absence of dislocations are the same as in FIG. 5. In FIG. 5, the horizontal axis indicates the temperature of creep heat treatment (° C.), The axis shows the creep heat treatment time (seconds) in index. In FIG. 5, a circle indicates that no dislocation occurs.
The mark indicates the condition where dislocation occurred. Confirmation of dislocation generation was performed by the same method as described in the first embodiment.

According to FIG. 5, in the case of the MOS transistor for which the experiment was performed, the boundary line L between the circle and the cross
It can be seen that the time is exponentially shorter than the high temperature. Thus, the boundary straight line L is uniquely determined by the structure and material of the MOS transistor and the impurity concentration of the source / drain regions. Therefore, if creep heat treatment is performed within a range of temperature and time having a certain relationship indicated by the boundary line L, dislocation expansion at the pattern edge accompanying ion implantation into the n + high concentration impurity region and subsequent activation heat treatment is performed. Can be suppressed.

Here, the principle of relieving the stress on the silicon substrate of the gate insulating film or the post-oxidized insulating film by the creep process will be described with reference to FIG. FIG. 6 is a relationship diagram showing the temperature dependence of the stress exerted on the silicon substrate from the silicon oxide film, that is, a stress-temperature curve. FIG. 6 shows the stress at the temperature at which a silicon oxide film is formed on one side of the silicon substrate and the substrate is heat-treated. The stress on the + side of the vertical axis in FIG. 6 indicates the magnitude of the tensile stress that the silicon oxide film receives from the silicon substrate (and, at the same time, the compressive stress that the silicon substrate receives from the silicon oxide film). The negative stress indicates the magnitude of the compressive stress that the silicon oxide film receives from the silicon substrate (the tensile stress that the silicon substrate receives from the silicon oxide film).

The stress-temperature curve a in FIG. 6 shows the transition of the stress exerted on the silicon substrate by the silicon oxide film during the temperature rise and fall when the creep heat treatment is not performed. A stress-temperature curve b indicates the stress exerted on the silicon substrate by the silicon oxide film when the temperature is raised and lowered before and after the creep heat treatment. Further, a curve c shows a transition of stress exerted on the silicon substrate by the silicon oxide film at the time of temperature increase / decrease in the heat treatment process after the creep heat treatment. This creep heat treatment was performed at 970 ° C. for about 10 minutes.

Here, by performing creep heat treatment before ion implantation of the source / drain regions, the stress-temperature curve b of the gate insulating film 102 or the post-oxide insulating film 120 with respect to the silicon substrate is high (900 ° C. to 970 ° C.). It moves in the direction to reduce the stress. Therefore, in the subsequent high-temperature treatment when the source / drain region is subjected to activation heat treatment, the stress-temperature curve follows a curve that moves in the direction of decreasing the stress at high temperature. The compressive stress of the film 102 or the post-oxide insulating film 120 can be minimized, and dislocation expansion can be suppressed.

In the second embodiment, the stress due to the side wall can be relieved by performing the creep process after the first gate electrode side wall 104 is formed. Next, a third embodiment of the present invention will be described with reference to FIG. In this embodiment, rapid lamp annealing is performed from the side of the wafer mirror surface where an element is formed using a light transmission prevention mask, a temperature gradient is provided between the gate electrode and the source / drain region, and activation heat treatment is selectively performed. We focused on controlling the recrystallization process and suppressing the expansion of dislocations. FIG. 7 is a diagram showing a plan view of a light transmission preventing mask corresponding to lamp annealing in the activation heat treatment of the source / drain regions for explaining the third embodiment of the present invention, and a relationship diagram of dislocation occurrence rates. FIG. 1 of the first embodiment (
As described in a) and (b), a gate electrode and a side wall of the gate electrode are formed on the silicon substrate, and an n− low concentration impurity region and an n + high concentration impurity region corresponding to each are formed by ion implantation. In the subsequent activation heat treatment of the source / drain regions, a light transmission prevention mask is formed at a specific location such as a gate electrode, and RT from the wafer mirror surface side where the element is formed.
A was performed. RTA in the experiment was performed by lamp annealing, and lamp annealing was performed using a single-side heating method using a halogen lamp. Lamp annealing is performed at 950 ° C in a nitrogen atmosphere.
0 seconds.

The drawing of FIG. 7 is a plan top view showing the state of the semiconductor device formed in FIGS. 1A and 1B. The gate electrode 103, the gate electrode sidewall 104, the source / drain regions 108,
Each element isolation region 130 is shown. The location where the light transmission preventing mask is applied is indicated by the hatched portion in the figure. The light transmission preventing mask used in this example was formed on the substrate by LP-CVD or the like using SiO _2.
A film is formed and formed at a specific location such as a gate electrode by a normal photoetching process.

Here, the light transmission preventing film mask is formed only at the gate electrode (FIG. 7A), the gate electrode and the gate electrode side wall (FIG. 7B), the gate electrode, the gate electrode side wall, the gate edge and the element. Isolation region intersection (FIG. 7C), gate electrode side wall end and element isolation region intersection only (FIG. 7D), no light transmission prevention mask (FIG. 7E), and conventional example Source without light transmission mask. The activation heat treatment of the drain region was performed with six patterns of FA (FIG. 7F), and the occurrence rate of each dislocation was investigated.

FA was performed at 950 ° C. for 10 minutes in a nitrogen atmosphere. The rate of occurrence of dislocation was confirmed by the same method as in the first example. The occurrence rate of dislocations is shown by a histogram in FIG.

As shown in FIG. 7, the activation heat treatment method for the source / drain regions can suppress the occurrence of dislocation when the activation heat treatment is selectively performed with the light transmission preventing mask on the single-sided RTA rather than the FA. In addition, the effect of preventing the light transmission of heat radiation by the mask is reflected, and the effect of preventing the light transmission only by the gate electrode is also effective. In particular, when both the gate electrode side wall end and the isolation region, or the gate electrode and the gate electrode side wall are both prevented from transmitting light, the dislocation generation rate is minimized.

FIG. 8 shows an example in which lamp annealing is performed in the same manner as in the third embodiment. However, in the experiment of FIG. 8, lamp annealing is performed by forming film materials having different light absorption rates on the upper layer portion of the gate electrode and the surfaces of the source / drain regions without covering the gate electrode and the like with a mask. It is an example.

FIG. 8 is a histogram showing the rate of occurrence of dislocations when the material of the film on the upper layer of the gate electrode and the thickness of the SiO ₂ film on the source / drain regions are changed. The material of the gate electrode upper layer portion was an SiN film and a Poly-Si film, and the thickness of the oxide film on the source / drain region was 20 nm and 100 nm. The occurrence rate of dislocation was confirmed in the same manner as in the first example.

FIG. 8 shows that the occurrence rate of dislocation is minimized when Poly-Si is deposited on the gate electrode and the oxide film on the surface of the source / drain region is 100 nm. Here, when the oxide film thickness on the surface of the source / drain region is 100 nm, the reflectance of light becomes weak due to the interference effect,
As a result, it has been found that even if the same oxide film is thick to some extent, the light absorption rate is improved. That is, when the temperature rise on the source / drain regions becomes higher than the temperature rise on the gate electrode in FIG. 8, dislocation is suppressed. Further, when the temperature gradient on the source / drain region and the gate electrode is reversed, that is, the thickness of the oxide film formed on the source / drain region is 2
It was found that even when the thickness was as thin as 0 nm, the occurrence rate of dislocations was reduced as compared with the conventional FA.

The change in the occurrence rate of dislocation due to the difference in the temperature gradient described above will be described with reference to FIG.
FIG. 9A shows that the temperature (T _{S / D} ) on the source / drain region is the temperature (T _G ) on the gate electrode.
9 is a cross-sectional view showing the direction of solid phase growth of the source / drain region in the case of being larger than FIG.
b) is a cross-sectional view showing the direction of solid-phase growth of the source / drain region when the temperature (T _{S / D} ) on the source / drain region is lower than the temperature (T _G ) on the gate electrode.

In FIG. 9A, n + high-concentration impurities are ion-implanted using the side wall of the gate electrode as a mask to form source / drain regions, and then the temperature on the source / drain regions and on the gate electrode is determined by the method described in FIG. A case where the RTA process is performed with a gradient is shown. In this case, the growth of the source / drain regions is dominant in the <100> direction from the center.

In FIG. 9B, n + high-concentration impurities are ion-implanted using the side wall of the gate electrode as a mask to form a source / drain region, and then a temperature gradient is formed on the source / drain region and the gate electrode by the method described in FIG. This shows a case where RTA processing is performed with. In this case, the growth of the source / drain regions is dominant in the <11 0 > direction from the end near the gate edge.

As shown in FIG. 10, when recrystallization in both directions <100> and <11 0 > occurs, dislocation occurs at the gate edge. Therefore, the source / drain region can be obtained by using the single-sided RTA method by lamp annealing. It was found that the temperature gradient on the top and the gate electrode is increased so that the temperature rise on the source / drain region is larger than that on the gate electrode, thereby greatly contributing to the suppression of dislocation expansion.

The material used in the light transmission preventing mask and the like used in the third embodiment is not particularly limited as long as the same effect can be obtained as well as those described in the examples.

Note that, instead of the RTA method, a heat treatment method of 1 s or less shorter than the RTA, for example, spike annealing or flash annealing, can achieve the same effect or higher than the RTA method.

In the above-described embodiment, the MOS transistor having the LDD structure has been described. However, the structure applicable to the present invention is not limited to the LDD structure, and the activation heat treatment after ion implantation of the high-concentration impurities is performed when the source / drain regions are formed. If it applies, it will not specifically limit.

In addition, the sequence of the embodiment is within the scope of the object of the present invention, depending on the structure of the semiconductor element, the type of material used and the application, and the number of times of the ion implantation process and the activation heat treatment process, as necessary. It is possible to select a condition as appropriate and to form a source / drain region, and it is also possible to use the first to third embodiments in combination as required.

Furthermore, in the embodiment, under the activation heat treatment conditions, the temperature, treatment time, atmosphere, and the like can be selected as appropriate. Also, the dose amount, acceleration voltage, and the like are constant in the ion implantation. However, depending on the adjustment of the desired structure and impurity concentration, it is possible to perform processing even if these are changed during the ion implantation step.

FIG. 6 is a process diagram of forming source / drain regions in the semiconductor device using the LDD structure according to the first embodiment of the present invention. The characteristic view which shows the relationship between the film thickness of the 2nd gate electrode side wall in the 1st Embodiment of this invention, and a dislocation generation rate. The flowchart figure of formation of the source-drain area | region in the semiconductor device using the LDD structure in the 2nd Embodiment of this invention. The flowchart figure of formation of the source / drain area | region in the semiconductor device using the LDD structure in another 2nd Embodiment of this invention. The characteristic view which shows the relationship between the temperature of the creep heat processing in 2nd Embodiment of this invention, and processing time. The relationship figure which shows the stress-temperature curve which acts on a silicon substrate from a silicon oxide film. The characteristic view which shows the relationship between the light transmission prevention mask top view of the activation heat processing of the semiconductor device using the LDD structure in the 3rd Embodiment of this invention, and a dislocation generation rate. The characteristic view which shows the relationship between the film material of the gate electrode upper layer part in the 3rd Embodiment of this invention, and the dislocation | regeneration rate by the change of the film thickness of the oxide film of a source / drain region upper layer part. Schematic which showed the solid phase growth in the silicon substrate by the temperature gradient on the gate electrode and source / drain area | region in the 3rd Embodiment of this invention. Sectional drawing which shows the conventional semiconductor device. FIG. 10 is a process diagram of forming source / drain regions in a semiconductor device using a conventional LDD structure.

Explanation of symbols

101 ... P-type silicon substrate, 102 ... Gate insulating film, 103 ... Gate electrode,
104: first gate electrode sidewall, 104a: end of first gate electrode sidewall,
105 ... second gate electrode sidewall, 105a ... second gate electrode sidewall end,
106, 116... N-low concentration impurity region,
107, 117... N + high concentration impurity region,
108, 118 ... source / drain regions, 130 ... element isolation regions

Claims (4)

Forming a gate insulating film on the silicon semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a gate electrode sidewall film on the gate electrode;
Performing a heat treatment to relieve stress on the silicon semiconductor substrate of the gate insulating film after forming the gate electrode sidewall film ;
After performing the heat treatment, as at least part of the mask the gate electrode sidewall film, the impurity is implanted before Symbol silicon semiconductor substrate, forming an amorphous region,
Forming the light transmission preventing film on the gate electrode and the gate electrode sidewall film after forming the amorphous region;
After forming the light transmission preventing film, RTA from the surface side of the gate electrode of the silicon semiconductor substrate is formed by a spike anneal or flash anneal, possess and performing activation heat treatment of the amorphous region,
In the step of performing the activation heat treatment, the temperature of the gate electrode is lower than the temperature of the amorphous region by the light transmission preventing film, and recrystallization of the amorphous region in the <100> direction is caused by the temperature difference. To make growth dominant.
A method for manufacturing a semiconductor device. Forming a gate insulating film on the silicon semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a post-oxide insulating film on the gate electrode;
Forming a gate electrode sidewall film on the post-oxidation insulating film;
After forming the gate electrode sidewall film , performing a heat treatment to relieve stress on the silicon semiconductor substrate of the gate insulating film and the post-oxide insulating film;
After performing the heat treatment, as at least part of the mask the gate electrode sidewall film, the impurity is implanted before Symbol silicon semiconductor substrate, forming an amorphous region,
Forming the light transmission preventing film on the gate electrode and the gate electrode sidewall film after forming the amorphous region;
After forming the light transmission preventing film, RTA from the surface side of the gate electrode of the silicon semiconductor substrate is formed by a spike anneal or flash anneal, possess and performing activation heat treatment of the amorphous region,
In the step of performing the activation heat treatment, the temperature of the gate electrode is lower than the temperature of the amorphous region by the light transmission preventing film, and recrystallization of the amorphous region in the <100> direction is caused by the temperature difference. To make growth dominant.
A method for manufacturing a semiconductor device. Forming a gate insulating film on the silicon semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a gate electrode sidewall film on the gate electrode;
Performing a heat treatment to relieve stress on the silicon semiconductor substrate of the gate insulating film after forming the gate electrode sidewall film ;
After performing the heat treatment, as at least part of the mask the gate electrode sidewall film, the impurity is implanted before Symbol silicon semiconductor substrate, forming an amorphous region,
After forming the amorphous region, forming a material having a different light absorption rate on the surface of the gate electrode and the surface of the amorphous region, and
A step of performing activation heat treatment of the amorphous region by RTA, spike annealing or flash annealing from the surface side of the silicon semiconductor substrate on which the gate electrode is formed after forming the film materials having different light absorption rates It has a door,
In the step of performing the activation heat treatment, (1) the temperature of the gate electrode becomes lower than the temperature of the amorphous region due to the film materials having different light absorption rates, and the amorphous region is recrystallized due to the temperature difference. Or (2) the temperature of the gate electrode is higher than the temperature of the amorphous region, and the recrystallization of the amorphous region is caused by the temperature difference. Make the growth in the <110> direction dominant.
A method for manufacturing a semiconductor device. Forming a gate insulating film on the silicon semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a post-oxide insulating film on the gate electrode;
Forming a gate electrode sidewall film on the post-oxidation insulating film;
After forming the gate electrode sidewall film , performing a heat treatment to relieve stress on the silicon semiconductor substrate of the gate insulating film and the post-oxide insulating film;
After performing the heat treatment, as at least part of the mask the gate electrode sidewall film, the impurity is implanted before Symbol silicon semiconductor substrate, forming an amorphous region,
After forming the amorphous region, forming a material having a different light absorption rate on the surface of the gate electrode and the surface of the amorphous region, and
A step of performing activation heat treatment of the amorphous region by RTA, spike annealing or flash annealing from the surface side of the silicon semiconductor substrate on which the gate electrode is formed after forming the film materials having different light absorption rates It has a door,
In the step of performing the activation heat treatment, (1) the temperature of the gate electrode becomes lower than the temperature of the amorphous region due to the film materials having different light absorption rates, and the amorphous region is recrystallized due to the temperature difference. Or (2) the temperature of the gate electrode is higher than the temperature of the amorphous region, and the recrystallization of the amorphous region is caused by the temperature difference. Make the growth in the <110> direction dominant.
A method for manufacturing a semiconductor device.

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