JP4566860B2 - Semiconductor integrated circuit device design apparatus, wiring method, and program - Google Patents

Description

  The present invention relates to a design apparatus, a wiring method, and a program for a semiconductor integrated circuit device, and more particularly, to a design apparatus, a wiring method, and a program for electrode pads arranged around a chip.

  In a semiconductor integrated circuit device, generally, an electrode pad (hereinafter also simply referred to as a pad or a PAD) is arranged around a chip to enable external connection. When such a pad is provided, it is desirable to realize a semiconductor device having a small size by reducing the area of the pad formation region as much as possible. For this reason, a semiconductor integrated circuit device is known in which some pads and the remaining pads are alternately arranged in a staggered pattern on the input / output buffer one by one. When the input / output buffer connected to such a pad is, for example, a power supply or ground I / O block, it is necessary to lower the wiring impedance to suppress the voltage fluctuation at the pad. Therefore, the pads are wired with wiring called a pad bridge.

  As a technique for wiring pads, Patent Document 1 discloses a bonding pad structure formed of a single layer or a plurality of metal layers of a semiconductor integrated circuit device having a multilayer wiring structure. This semiconductor integrated circuit device has wiring that connects both bonding pads between adjacent bonding pads, and the wiring is formed of a wiring layer other than the uppermost layer of the multilayer wiring. By not providing a via hole for connecting to the uppermost layer of the multilayer wiring in the empty pad part, even if aluminum corrosion occurs in the empty pad part, the part used as wiring is not corroded and does not cause problems such as disconnection Has an effect.

JP-A-3-278551 (FIGS. 1 and 3)

  In recent years, the increase in the scale of semiconductor integrated circuit devices has been remarkable. Along with this, the number of electrode pads has increased, and the number of man-hours for placement and routing has also increased. Conventionally, in the wiring of the pad bridge, the wiring is manually performed after the wiring of the I / O block. When the number of electrode pads is small, it was not a problem, but with the increase in the number of electrode pads, there is a possibility that mistakes will occur in the wiring by manual wiring and the design man-hour may increase. was there.

According to one aspect of the present invention, there is provided a wiring method for a semiconductor integrated circuit device, wherein an electrode pad arrangement region is formed on an input / output circuit region arranged in a peripheral portion of a chip, and wiring to the electrode pad is performed in the electrode pad arrangement region. This is a method in which wiring of a semiconductor integrated circuit device in which electrode pads are arranged in a staggered pattern on a chip end side and an internal circuit region side across a connection region is wired by a design device using computer software . The design apparatus has a first electrode pad on the chip end side wired via a contact from the input / output circuit in the input / output circuit region, and any second on the internal circuit region side facing the first electrode pad. When performing placement and routing based on data obtained by combining the wiring data for wiring the electrode pads and the placement and routing data of the input / output circuit , the design apparatus includes a placement information storage unit, a library storage unit, and a placement type determination unit. And a data synthesizing unit, and the arrangement type determining unit is arranged to face the first electrode pad on the chip end side and the first electrode pad wired from the input / output circuit in the input / output circuit region via the contact. The step of reading the arrangement information of the pad bridge connecting the second electrode pads on the circuit area side and the arrangement information of the input / output circuit from the arrangement information storage unit, and the arrangement type determination unit The arrangement type of the pad bridge indicating whether the second electrode pad exists on the left or right side with respect to the central axis in the longitudinal direction of the input / output circuit arrangement area is determined from the arrangement information of the input / output circuit and the arrangement information of the input / output circuit A step of reading from the library storage unit the layout wiring data of the input / output circuit to which the pad bridge corresponding to the determined layout type is added, and the data synthesis unit having the pad bridge added Synthesizing the placement and routing data in the input / output circuit area based on the placement and routing data of the input / output circuit.

According to one aspect of the present invention, there is provided a semiconductor integrated circuit device design apparatus in which an electrode pad arrangement region is formed on an input / output circuit region provided in a peripheral portion of a chip, and wiring to the electrode pad is performed in the electrode pad arrangement region. This is a design apparatus for a semiconductor integrated circuit device in which electrode pads are arranged in a staggered pattern on the chip end side and the internal circuit region side with the connection region interposed therebetween. This device includes a first electrode pad on the chip end side wired via a contact from an input / output circuit in the input / output circuit region, and a second one on the internal circuit region side facing the first electrode pad. Arrangement information storage unit for storing arrangement information of pad bridges connected to electrode pads and arrangement information of input / output circuits, and library storage unit for storing arrangement / wiring data of input / output circuits to which pad bridges are added And the pad bridge arrangement information and the input / output circuit arrangement information are read from the arrangement information storage unit, and the second electrode pad exists on either side of the central axis in the longitudinal direction of the arrangement area of the input / output circuit. Live or a determining arrangement type determining unit placement type pad bridge showing the to the placement and routing data input and output circuit pad bridge is added corresponding to the determined layout type Read from Li storage unit includes a data synthesizer for synthesizing the placement and routing data in the input-output circuit region.

In a program according to one aspect of the present invention, an electrode pad arrangement region is formed on an input / output circuit region arranged in a peripheral portion of a chip, and the chip is sandwiched between the electrode pad arrangement region and a wiring connection region to the electrode pad. A design device for designing wiring of a semiconductor integrated circuit device in which electrode pads are arranged in a staggered pattern on the end side and the internal circuit region side includes a placement information storage unit and a library storage unit, and a computer constituting the design device In addition, the first electrode pad on the chip end side wired via the contact from the input / output circuit in the input / output circuit region and any second electrode pad on the internal circuit region side facing the first electrode pad and arrangement information of the pad bridge which connects the, reads the arrangement information of the input and output circuit from the layout data storage unit, first to the longitudinal center axis of the arrangement region of the input-output circuit If the determining arrangement type determination processing arrangement type of pad bridges of an electrode pad is present in the left or right side, the placement and routing data input and output circuit pad bridge is added corresponding to the determined layout type Data synthesizing processing that reads from the library storage unit and synthesizes the placement and routing data in the input / output circuit area is executed.

  According to the present invention, the I / O block arrangement and the pad bridge wiring can be automatically performed, and the design man-hour is reduced.

  FIG. 1 is a block diagram showing the configuration of a semiconductor integrated circuit device design apparatus according to an embodiment of the present invention. In FIG. 1, the design device includes a processing device 10, an input device 11, an output device 12, and a storage device 13, and is configured by an engineering workstation, a personal computer, or the like. The processing device 10 includes a CPU and the like, and functions as a design device by executing a placement and routing program 20 built in the storage device 13. The input device 11 functions as a man-machine interface that gives an instruction or the like to the processing device 10 and includes a keyboard, a mouse, and the like. The output device 12 includes a display, a printer, and the like, and displays the output result of the processing device 10 and the like. The storage device 13 is composed of a semiconductor memory, a hard disk, and the like, and stores placement and routing information 14 of the semiconductor integrated circuit device, various libraries 15 necessary for placement and routing, placement and routing result data 18, a placement and routing program 20, and the like. The library 15 includes input / output circuit information 17 and the like.

  Next, a design method executed by the placement and routing program 20 will be described. Here, the description is limited to the arrangement and wiring of the I / O block (input / output circuit) and the pad connected thereto. FIG. 2 is a block diagram showing the configuration of the placement and routing program 20. The placement and routing program 20 mainly functions as a placement type determination unit 21 and a data synthesis unit 22. FIG. 3 is a flowchart showing a procedure of a method for designing a semiconductor integrated circuit device.

  In step S <b> 11, the placement type determination unit 21 inputs I / O block and pad placement and routing data to be designed from the placement and routing information 14 related to the semiconductor integrated circuit device.

  In step S12, the arrangement type determination unit 21 determines the arrangement type of the pad bridge that connects the pads from the I / O block and pad arrangement wiring data. More specifically, the pad bridge arrangement type depends on whether the electrode pad connected to the I / O block is on the left or right side with respect to the central axis in the longitudinal direction of the I / O block arrangement area. Determined.

  In step S <b> 13, the data composition unit 22 reads the input / output circuit information 17 related to the I / O block to which the corresponding pad bridge information is added from the library 15 according to the arrangement type result determined by the arrangement type determination unit 21.

  In step S14, the data synthesizer 22 determines whether or not the information of all the target pads has been read out. If there is any remaining information, the process returns to step S11, and if all are read, the process proceeds to step S15.

  In step S15, the data synthesis unit 22 synthesizes the read input / output circuit information 17 to obtain the placement and routing result data 18 in the I / O block area.

  As described above, the semiconductor integrated circuit device design apparatus operates, and by performing placement and routing based on the placement and routing result data 18, I / O block placement and pad bridge wiring can be performed automatically. A specific design example of the semiconductor integrated circuit device will be described below in accordance with the embodiment.

  FIG. 4 is a diagram schematically showing a configuration of a semiconductor integrated circuit device created by the design method of the present invention. As shown in FIG. 4A, an I / O area 50 exists in the peripheral portion of the chip, and an internal logic area 51 exists on the center side of the chip adjacent to the I / O area 50. In the I / O region 50, pads 40a (PAD1), 40b (PAD2), 40c (PAD3), and 40d (PAD4) are disposed. In addition, I / O blocks 41a and 41b exist on the semiconductor substrate 53 in the I / O region 50, and are connected to the pads 40b and 40c via the wiring portions 42a and 42b, which are pad outlets, respectively. Yes. Further, the pad 40 b and the pad 40 c are connected by a pad bridge 44, and the pad 40 c is wired to the internal logic region 51 by a wiring 43. The wiring portions 42a and 42b and the pad bridge 44 are disposed in a wiring connection region 52 sandwiched between the pads 40a and 40c and the pads 40b and 40d. Here, the number of pads disposed is shown as four, but the number of pads is not limited to this. Moreover, although the case where the wiring 43 is wired to the pad 40c to which the pad bridge 44 is connected is illustrated, the wiring 43 may be wired to a pad to which the pad bridge is not connected.

  FIG. 4B is a cross-sectional view illustrating the X1-Y1 cross section in FIG. The pad bridge 44 and the wiring 43 are wired in the same metal wiring layer as the pads 40b and 40c. A wiring 62a exists under the pad 40b (on the semiconductor substrate side) through a via 61a, and the wiring 62a is connected to the wiring part 42a. A wiring 64a is connected under the wiring 62a through a via 63a, and the wiring 64a is connected to the I / O block 41a on the semiconductor substrate 53 through a via 65a. Further, a wiring 62b is present under the pad 40c through a via 61b, a wiring 64b is connected to the wiring 62b through a via 63b, and the wiring 64b is connected to the I on the semiconductor substrate 53 through the via 65b. / O block 41a is connected.

  FIG. 4C is a cross-sectional view illustrating the X2-Y2 cross section in FIG. The wiring 62b existing under the pad 40c (on the semiconductor substrate side) is connected to the wiring part 42b.

  Here, the pad bridge 44 is illustrated as being the same metal wiring layer as the pads 40b and 40c. However, the pad bridge 44 may be disposed in an arbitrary metal layer to connect the pads as necessary. It may be configured. Further, although the I / O blocks 41a and 41b are illustrated so as to exist in the semiconductor substrate 53, actually, the semiconductor elements on the semiconductor substrate 53 and an insulating film formed thereon are not illustrated. It is comprised by the wiring and contact which used arbitrary metal layers.

  In the I / O region 50 of the semiconductor integrated circuit device configured as described above, pads 40b and 40d are disposed on the chip end side with the wiring connection region 52 in which the wiring portions 42a and 42b and the pad bridge 44 are disposed. Then, pads 40a and 40c are disposed on the internal logic region 51 side, and the respective pads are disposed in a staggered pattern. By disposing the pads in this way, the distance from the wiring connection region to the pads can be shortened, and the wiring impedance can be lowered.

  In addition, with respect to a pad arranged on the side of the internal logic area 51 such as the pad 40a, the wiring impedance of the pad 40a can be further reduced by wiring the wiring 43 directly from the internal logic area 51. Further, by connecting the pad 40b on the chip end side and the pad 40c on the internal logic region 51 side by the pad bridge 44, the wiring impedance to the pad 40b can be further reduced. When the I / O block connected to the pad is an I / O block for power supply or grounding in particular, the wiring impedance is lowered by using the wiring 43 or the pad bridge 44 to suppress fluctuations in the voltage at the pad. Can do.

  Furthermore, in the LSI wafer test, when there is a limit to the number of times of needle contact to the pad and this is the neck of testing, two or more pads are shared by the pad bridge, and the needle contact to each pad The number of needle hits can be increased by performing.

  Next, a method for arranging the pad bridge will be described. FIG. 5A shows the I / O block 41 in which a pad bridge 44r is arranged on the right side via the wiring part 42 with respect to the longitudinal symmetry axis of the rectangular I / O block 41. FIG. 5B shows the I / O block 41 in which a pad bridge 44l is arranged on the left side with respect to the longitudinal axis of symmetry of the rectangular I / O block 41 via the wiring portion. In the layout and wiring of the pad bridge, design data of these two types of I / O blocks is prepared in the library 15 in advance. That is, two types of data obtained by combining pad bridge wiring data and I / O block layout wiring data are prepared as input / output circuit information 17. Then, depending on which chip end side pad and which internal logic region 51 side pad are wired by a pad bridge, data of the I / O block of either type of FIG. 5A or FIG. 5B is used. To select.

  For example, in the I / O block 41a connected to the pad 40b of FIG. 5C, when the pad 40b and the pad 40c are wired by the pad bridge 44a, the data of the I / O block of the type of FIG. To select. Further, in the I / O block 41n connected to the pad 40n in FIG. 5C, when the pad 40m and the pad 40n are wired by the pad bridge 44n, the data of the I / O block of the type in FIG. 5B is used. To select. The pad 40b (PAD2) and the pad 40c (PAD3) are automatically set by the pad bridge 44a by arranging and wiring the data of the selected I / O block in the I / O area 50 on the LSI chip layout. Placed and routed. Further, the pad 40m (PAD9) and the pad 40n (PAD10) are automatically arranged and wired by the pad bridge 44n.

  In this way, I / O block layout data and pad bridge wiring can be automatically performed by using two types of pad bridge layout data in the I / O block. Since no bridge wiring is required, the design man-hour is reduced.

1 is a block diagram illustrating a configuration of a design apparatus for a semiconductor integrated circuit device according to an embodiment of the present invention. It is a block diagram which shows the structure of the place-and-route program which concerns on embodiment of this invention. It is a flowchart which shows the place-and-route method which concerns on embodiment of this invention. It is a figure which shows typically the structure of the semiconductor integrated circuit device produced by the design method of this invention. It is a figure which shows typically the arrangement | positioning wiring of the semiconductor integrated circuit device produced by the design method of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Processing apparatus 11 Input apparatus 12 Output apparatus 13 Storage apparatus 14 Arrangement / wiring information 15 Library 17 Input / output circuit information 18 Arrangement / wiring result data 20 Arrangement / wiring program 21 Arrangement type determination section 22 Data composition section 40a, 40b, 40c, 40d, 40m 40n Pad 41, 41a, 41b, 41n I / O block 42, 42a, 42b, 42n Wiring part 43, 62a, 62b, 64a, 64b Wiring 44, 44a, 44n, 44r, 44l Pad bridge 50 I / O area 51 Internal logic area 52 Wiring connection area 53 Semiconductor substrates 61a, 61b, 63a, 63b, 65a, 65b Vias

Claims (5)

An electrode pad arrangement region is formed on the input / output circuit region disposed in the peripheral portion of the chip, and the electrode pad arrangement region includes the wiring connection region to the electrode pad and the chip end side and the internal circuit region side. A method in which wiring of a semiconductor integrated circuit device having electrode pads arranged in a staggered pattern is wired by computer software using computer software ,
The design apparatus includes a first electrode pad on the chip end side wired via a contact from an input / output circuit in the input / output circuit region, and any of the internal circuit region side facing the first electrode pad. When performing placement and routing based on data obtained by combining the wiring data for wiring the second electrode pad and the placement and routing data of the input / output circuit ,
The design apparatus includes an arrangement information storage unit, a library storage unit, an arrangement type determination unit, and a data synthesis unit,
The arrangement type determination unit is configured such that a first electrode pad on the chip end side wired via a contact from an input / output circuit in the input / output circuit region and the internal circuit region side facing the first electrode pad Reading from the arrangement information storage unit the arrangement information of the pad bridge that connects between the second electrode pads and the arrangement information of the input / output circuit;
The placement type determining unit determines whether the second electrode pad is on the left or right side with respect to the central axis in the longitudinal direction of the placement region of the input / output circuit based on the placement information of the pad bridge and the placement information of the input / output circuit. Determining the placement type of the pad bridge to indicate whether
The data synthesizing unit reads from the library storage unit layout wiring data of an input / output circuit to which a pad bridge corresponding to the determined layout type is added;
The step of synthesizing the placement and routing data in the input / output circuit region based on the placement and routing data of the input / output circuit to which the pad bridge is added;
A method of wiring a semiconductor integrated circuit device, comprising: The pad bridge is the first and the wiring process of a semiconductor integrated circuit device according to claim 1 wherein the second electrode pad and characterized in that it is arranged on the metal layer of the same layer. An electrode pad arrangement region is formed on the input / output circuit region disposed in the peripheral portion of the chip, and the electrode pad arrangement region includes the wiring connection region to the electrode pad and the chip end side and the internal circuit region side. A device for designing a semiconductor integrated circuit device in which electrode pads are arranged in a staggered pattern,
The first electrode pad on the chip end side wired via the contact from the input / output circuit in the input / output circuit region and the second one on the internal circuit region side facing the first electrode pad An arrangement information storage unit for storing arrangement information of a pad bridge connecting between electrode pads and arrangement information of the input / output circuit;
A library storage unit for storing the placement and routing data of the input / output circuit to which the pad bridge is added;
The arrangement information storage unit reads the arrangement information of the pad bridge and the arrangement information of the input / output circuit, and the second electrode pad is positioned on either side of the central axis in the longitudinal direction of the arrangement area of the input / output circuit. An arrangement type determination unit that determines an arrangement type of the pad bridge indicating whether the pad bridge exists on the side ;
A data synthesis unit that reads the layout wiring data of the input / output circuit to which the pad bridge corresponding to the determined layout type is added from the library storage unit, and synthesizes the layout wiring data in the input / output circuit area;
An apparatus for designing a semiconductor integrated circuit device, comprising: 4. The design apparatus of a semiconductor integrated circuit device according to claim 3 , wherein the pad bridge is disposed in the same metal layer as the first and second electrode pads. An electrode pad arrangement region is formed on the input / output circuit region disposed in the peripheral portion of the chip, and the electrode pad arrangement region includes the wiring connection region to the electrode pad and the chip end side and the internal circuit region side. A design device for designing wiring of a semiconductor integrated circuit device in which electrode pads are arranged in a staggered pattern includes an arrangement information storage unit and a library storage unit, and a computer constituting the design device includes:
The output circuit from the output circuit in the region of the internal circuit region side where the first electrode pads of the chip end side which is routed through the contact opposite to the first electrode pad or a second and arrangement information of the pad bridges for connecting the electrode pad, and the arrangement information of the input-output circuit reads from the placement information storage unit, the relative longitudinal center axis of the arrangement region of the input-output circuit first An arrangement type determination process for determining an arrangement type of the pad bridge indicating whether the two electrode pads are on the left or right side ;
Loading arrangement wiring data input and output circuit pad bridge is added corresponding to the determined layout type from the library storage unit, and a data synthesizing process for synthesizing the placement and routing data in said output circuit area,
A program that executes

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