JP4565786B2 - ロックの開始と終了を要求するためのバスコマンドコードポイントの使用の最小化 - Google Patents

ロックの開始と終了を要求するためのバスコマンドコードポイントの使用の最小化 Download PDF

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Publication number
JP4565786B2
JP4565786B2 JP2001505301A JP2001505301A JP4565786B2 JP 4565786 B2 JP4565786 B2 JP 4565786B2 JP 2001505301 A JP2001505301 A JP 2001505301A JP 2001505301 A JP2001505301 A JP 2001505301A JP 4565786 B2 JP4565786 B2 JP 4565786B2
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Japan
Prior art keywords
lock
processor
command
bridge
response
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP2001505301A
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English (en)
Japanese (ja)
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JP2003527652A5 (enExample
JP2003527652A (ja
Inventor
マイヤー，デリック・アール
ルーチャック，ウィリアム・ケー
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of JP2003527652A5 publication Critical patent/JP2003527652A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2001505301A 1999-06-23 2000-01-11 ロックの開始と終了を要求するためのバスコマンドコードポイントの使用の最小化 Expired - Lifetime JP4565786B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/339,351 US6430639B1 (en) 1999-06-23 1999-06-23 Minimizing use of bus command code points to request the start and end of a lock
US09/339,351 1999-06-23
PCT/US2000/000605 WO2000079404A1 (en) 1999-06-23 2000-01-11 Minimizing use of bus command code points to request the start and end of a lock

Publications (3)

Publication Number Publication Date
JP2003527652A JP2003527652A (ja) 2003-09-16
JP2003527652A5 JP2003527652A5 (enExample) 2007-01-18
JP4565786B2 true JP4565786B2 (ja) 2010-10-20

Family

ID=23328620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001505301A Expired - Lifetime JP4565786B2 (ja) 1999-06-23 2000-01-11 ロックの開始と終了を要求するためのバスコマンドコードポイントの使用の最小化

Country Status (6)

Country Link
US (1) US6430639B1 (enExample)
EP (1) EP1190331B1 (enExample)
JP (1) JP4565786B2 (enExample)
KR (1) KR100687822B1 (enExample)
DE (1) DE60002077T2 (enExample)
WO (1) WO2000079404A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6973543B1 (en) * 2001-07-12 2005-12-06 Advanced Micro Devices, Inc. Partial directory cache for reducing probe traffic in multiprocessor systems
US6934806B2 (en) * 2002-09-23 2005-08-23 International Business Machines Corporation Method and system for improving input/output performance by proactively flushing and locking an entire page out of caches of a multiprocessor system
US7076680B1 (en) * 2003-03-14 2006-07-11 Sun Microsystems, Inc. Method and apparatus for providing skew compensation using a self-timed source-synchronous network
DE102006055513A1 (de) * 2006-05-24 2007-11-29 Robert Bosch Gmbh Kommunikationsbaustein
DE102007063291A1 (de) * 2007-12-27 2009-07-02 Robert Bosch Gmbh Sicherheitssteuerung
US9164886B1 (en) * 2010-09-21 2015-10-20 Western Digital Technologies, Inc. System and method for multistage processing in a memory storage subsystem
US10572387B2 (en) * 2018-01-11 2020-02-25 International Business Machines Corporation Hardware control of CPU hold of a cache line in private cache where cache invalidate bit is reset upon expiration of timer
US11163688B2 (en) 2019-09-24 2021-11-02 Advanced Micro Devices, Inc. System probe aware last level cache insertion bypassing

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5016167A (en) * 1987-12-21 1991-05-14 Amdahl Corporation Resource contention deadlock detection and prevention
US5175837A (en) * 1989-02-03 1992-12-29 Digital Equipment Corporation Synchronizing and processing of memory access operations in multiprocessor systems using a directory of lock bits
US5133074A (en) * 1989-02-08 1992-07-21 Acer Incorporated Deadlock resolution with cache snooping
JP2830116B2 (ja) 1989-07-27 1998-12-02 日本電気株式会社 マルチプロセッサシステムにおけるロック制御機構
US5615373A (en) * 1993-08-26 1997-03-25 International Business Machines Corporation Data lock management in a distributed file server system determines variable lock lifetime in response to request to access data object
EP0986008B1 (en) 1993-12-01 2008-04-16 Marathon Technologies Corporation Computer system comprising controllers and computing elements
US5586253A (en) 1994-12-15 1996-12-17 Stratus Computer Method and apparatus for validating I/O addresses in a fault-tolerant computer system
US5706446A (en) * 1995-05-18 1998-01-06 Unisys Corporation Arbitration system for bus requestors with deadlock prevention
US6560682B1 (en) 1997-10-03 2003-05-06 Intel Corporation System and method for terminating lock-step sequences in a multiprocessor system
US9919801B2 (en) * 2015-04-10 2018-03-20 B/E Aerospace, Inc. Articulating foot well divider for adjacent parallel passenger seats

Also Published As

Publication number Publication date
DE60002077T2 (de) 2004-03-04
KR20020012616A (ko) 2002-02-16
KR100687822B1 (ko) 2007-02-28
EP1190331B1 (en) 2003-04-09
JP2003527652A (ja) 2003-09-16
WO2000079404A1 (en) 2000-12-28
EP1190331A1 (en) 2002-03-27
US6430639B1 (en) 2002-08-06
DE60002077D1 (de) 2003-05-15

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